Patent Application
20230369509
The present disclosure relates to integrated circuits, and more particularly, to doped contact regions in thin film transistor structures.
As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, as transistor area decreases, so too do the dimensions for interconnects made to the various transistor structures, such as gate structures, drain regions, and source regions. Structures formed in such interconnect layers may be highly affected by process variations leading to subsequent variations in device performance or low yield of workable devices. Accordingly, there remain a number of non-trivial challenges with respect to the formation of backend structures in integrated circuits.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used.
Techniques are provided herein for forming thin film transistor structures having one or more doped contact regions. While the techniques can be used in any number of applications, they are particularly useful in forming backend (e.g., within the interconnect region) memory structures configured with thin film transistors (TFTs) having doped contact regions (e.g., source and drain regions contacting a semiconductor channel). The addition of certain dopants within a TFT contact region can be used to increase conductivity and provide higher thermal stability in that contact region. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. The access device may include, for example, TFT structure, and the storage device may include a capacitor. In such cases, the TFT structure allows the capacitor to be accessed during write operations (to store a memory bit) and read operations (to read a previously-stored bit). According to some such embodiments, the memory structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, in some cases, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region. The doping concentration may be, for example, consistent throughout a thickness of a given contact or may be graded through a thickness of the contact. Numerous variations and embodiments will be apparent in light of this disclosure.
General Overview
As previously noted above, there are a number of non-trivial challenges with respect to forming backend structures within a given interconnect region of an integrated circuit. For example, metal oxide semiconductor materials such as those used to form thin film transistors (TFTs) can be very susceptible to process variations caused by reducing environments and high temperatures. Such variations can shift the device properties during typical back-end-of-the-line (BEOL) processing, which can lead to poor charge mobility and poor stability in such devices.
Thus, and in accordance with some embodiments of the present disclosure, techniques are provided herein to form a TFT structure having one or more doped contacts to tune the transistor performance. The TFT structure may be implemented, for example, in a backend memory structure and may be part of one memory structure of an array of similar memory structures formed within various levels of interconnect layers over semiconductor devices (e.g., transistors) of a previously-formed device layer. Any kind of memory structure configuration can be used, such as those that provide dynamic random-access memory (DRAM). According to some embodiments, a TFT structure includes a gate electrode, a gate dielectric over the gate electrode (for a backside gate configuration), a semiconductor or channel region (or channel structure) over the gate dielectric, and one or more contacts to the semiconductor region that act as source or drain regions for the transistor. Furthermore, in some embodiments, either or both of the one or more contacts includes a metal oxide semiconductor material doped with one or more elements such as any of oxygen (O), fluorine (F), chlorine (Cl), aluminum (Al), silicon (Si), nitrogen (N), argon (Ar), hydrogen (H), germanium (Ge), magnesium (Mg), hafnium (Hf), tungsten (W), carbon (C), or cobalt (Co), to name a few examples. Various doping techniques may be used such as ion implantation, annealing, plasma treatment, or wet chemical surface treatment. According to some embodiments, the contact regions of the TFT structure can be doped at various times during the contact fabrication process to affect the overall dopant profile. For example, a first doping process may be used to dope the semiconductor region beneath the contacts (e.g., after the contact trench is formed, or during formation of the semiconductor region) while a second doping process is performed to dope a separate contact semiconductor region that is part of the conductive contact formed within the contact trench. The contact semiconductor region may be doped before and/or after metallization (contact fill metal) occurs to complete the formation of the conductive contact.
According to an embodiment, an integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. The contact may land on an uppermost surface of the semiconductor region, or may extend into the semiconductor region. The semiconductor region may be a single continuous layer with or without a dopant concentration gradient, or multiple distinct layers each with or without a dopant concentration gradient. In some embodiments, the conductive contact comprises a contact semiconductor region and a metal fill. In some such cases, the contact semiconductor region has a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material. The at least one dopant element may include, for example, any of O, F, Cl, Al, Si, N, Ar, H, Ge, Mg, W, Hf, or Co, to name a few examples.
According to another embodiment, an integrated circuit includes a plurality of semiconductor devices, an interconnect region above the plurality of semiconductor devices and including a plurality of stacked interconnect layers, and a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers. The TFT structure includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. In some embodiments, the conductive contact comprises a contact semiconductor region and a metal fill. The contact semiconductor region has a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material.
According to another embodiment, an integrated circuit includes a plurality of semiconductor devices, an interconnect region above the plurality of semiconductor devices and having a plurality of stacked interconnect layers, and a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers. The TFT structure includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. The conductive contact includes a contact semiconductor region and a metal fill. The contact semiconductor region has a first dopant profile of least one first dopant element and the portion of the semiconductor region beneath the conductive contact has a second dopant profile of at least one second dopant element. The first dopant element may be the same or different from the second dopant element.
According to another embodiment, a method of forming an integrated circuit includes forming a gate electrode on an underlying interconnect layer within an interconnect region over a plurality of semiconductor devices; forming a gate dielectric on the gate electrode; forming a semiconductor region on the gate dielectric; forming one or more dielectric layers over the semiconductor region; etching a recess through the one or more dielectric layers thus exposing a portion of the semiconductor region; forming at least one contact semiconductor layer within the recess; doping the at least one contact semiconductor layer with at least one dopant element; and forming a metal fill in the recess and over the at least one contact semiconductor layer.
Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX or EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomography (APT); local electrode atom probe (LEAP) techniques; 3D tomography; x-ray photoelectron spectroscopy (XPS), electron energy loss spectroscopy (EELS), x-ray fluorescence (XRF), or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For instance, in some example embodiments, such tools may indicate the presence of one or more dopants, such as any of the dopant elements disclosed above, within any of the conductive contacts of a TFT structure. Electron scattering techniques, such as EDS, may be used to determine the material composition of one or more conductive contact layers, or to detect a material gradient within any of the conductive contact layers or layer due to a given dopant profile. Likewise, the element and amount of doping can be analyzed using a ToF-SIMS, XRF, EELs. The chemical bonds of the doped contact layer can be analyzed, for instance, by XPS. Likewise, to verify the structure and formation of each layer, SEM and TEM with EDX composition analysis can be used. In addition, the improvement of device performance can be detected by electrical characteristic measurement.
It should be readily understood that the meaning of “above” and “over” in the present disclosure should be interpreted in the broadest manner such that “above” and “over” not only mean “directly on” something but also include the meaning of over something with an intermediate feature or a layer therebetween. The meaning of “on” or “directly on” in the present disclosure should be interpreted to mean something that is on something else with no intermediate feature or layer therebetween. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The integrated circuit or structure may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A monolayer is a layer that consists of a single layer of atoms of a given material. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure, with the layer having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A layer can be conformal to a given surface (whether flat or curvilinear) with a relatively uniform thickness across the entire layer. Example layers include, for instance, a liner or barrier layer (e.g., a relatively thin layer of tantalum nitride), an etch stop layer (e.g., a relatively thin layer of silicon nitride), an interconnect layer (e.g., a relatively thick layer that includes dielectric material and one or more conductive interconnect features and/or active devices and/or passive devices), and a device layer (e.g., a relatively thick layer that includes metal oxide semiconductor field effect transistors or MOSFETs along with dielectric materials and conductive materials)
Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not in the other material.
Architecture
According to some embodiments, in addition to semiconductor devices 104, device region 101 may include, for example, one or more other layers or structures associated with the semiconductor devices 104. For example, device region 101 can also include a substrate 102 and one or more dielectric layers 106 that surround active and/or conductive portions of the semiconductor devices 104. Device region 101 may also include one or more conductive contacts 108 that provide electrical contact to transistor elements such as gate structures, drain regions, or source regions. Conductive contacts 108 may include, for example, tungsten, ruthenium, or copper, although other metal or metal alloy materials may be used as well. Some embodiments may include a local interconnect (e.g., via or line) that connects a given contact 108 to an interconnect feature within the interconnect region 103.
Substrate 102 can be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or silicon germanium), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material from and/or upon which transistors can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, backside processing is used to remove substrate 102 and form additional backside interconnect layers. The techniques provided herein may be used to provide multi-tier memory structures within frontside and/or backside interconnect structures, as will be appreciated.
Interconnect region 103 includes any number (n) of interconnect layers 110-1 to 110-n stacked over one another. Each interconnect layer can include a dielectric material 112 along with one or more different conductive interconnect features (e.g., vias and lines), active devices (e.g., transistors, diodes), and/or passive devices (e.g., capacitors, resistors, inductors). Dielectric material 112 can be any dielectric, such as silicon oxide, silicon oxycarbide, silicon nitride, or silicon oxynitride. Dielectric material 112 may be formed using any known dielectric deposition technique such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable CVD, spin-on dielectric, or atomic layer deposition (ALD). The one or more conductive interconnect features can include any number of conductive traces 114 and conductive vias 116 arranged in any pattern across the interconnect layers 110-1 to 110-n to carry signal and/or power voltages to/from the various semiconductor devices 104. As used herein, conducive vias, such as conductive via 116, extend at least partially through an interconnect layer to connect between conductive traces on an upper interconnect layer and/or a lower interconnect layer, while conductive contacts, such as conductive contact 108, extend at least partially through a portion of dielectric layer 106 or any interconnect layer to contact one or more transistor elements. Interconnect layers are sometimes called metallization layers (e.g., such as M0 through M15). In some embodiments, a given metallization layer may include two adjacent interconnect layers with vias in one of the layers and metal traces in the other of the two layers.
Any of conductive traces 114 and conductive vias 116 can include any number of conductive materials, with some examples including copper, ruthenium, tungsten, cobalt, molybdenum, titanium, tantalum, and alloys thereof. In some example cases, any of conductive traces 114 and conductive vias 116 include a relatively thin liner or barrier, such as manganese, ruthenium, titanium nitride, titanium silicide, tungsten carbo-nitride (WCN), physical vapor deposited (PVD) or ALD tungsten, tantalum, or tantalum nitride, to name a few examples.
Note that each of the various conductive vias 116 and conductive contacts 108 are shown with tapered profiles to indicate a more natural appearance due to the etching process used to form the openings, although such tapering may not always be present. Any degree of tapering may be observed depending on the etch parameters used and the thickness of the dielectric layer being etched through. Furthermore, conductive vias may be stacked one over the other through different dielectric layers of interconnect region 103. However, in some examples, a single via recess may be formed through more than one dielectric layer yielding a taller, more tapered conductive via that extends through two or more dielectric layers (e.g., a deep via or supervia).
As can be further seen in this example embodiment, interconnect region 103 also includes tiers of memory arrays 118-1-118m, with each of the m memory arrays having any number of backend memory structures and/or capacitors. Each of the memory arrays may extend vertically across any number of interconnect layers (e.g., one, two or many). In some embodiments, a given memory array 118-1 includes a plurality of TFT structures 120 formed over a given conductive trace, such as conductive trace 114, extending in a first direction. According to some embodiments, a conductive via 122 extends between each TFT structure 120 along the illustrated row of TFT structures and conductive trace 114. In some other embodiments, the TFT structures 120 along the same row sit directly on conductive trace 114.
One or more second conductive traces 124 may each couple to a corresponding contact of a given TFT structure 120. Second conductive traces 124 may extend in a second direction orthogonal to the first direction. Conductive trace 114 may be, for example, a wordline of several parallel wordlines that extend beneath any number of TFT structures 120. Second conductive traces 124 may represent, for example, parallel bitlines extending into and out of the page and each connecting to the contacts of any number of TFT structures 120. TFT structures 120 can include any number of layers to form a transistor with a first source or drain region coupled to a corresponding second conductive trace 124 and a second source or drain region coupled to a conductive via 126. According to some embodiments, conductive via 126 acts as a conductive bridge between the second source or drain contact of a given TFT structure 120 and an electrode of its associated capacitor 128. Capacitors 128 may be, for example, metal-insulator-metal (MIM) capacitors having a U-shaped cross-section as shown, although other capacitor structures may be used as well (e.g., pillar-based capacitors with a dielectric layer sandwiched between an inner conductive core and an outer conductive layer, flat capacitors with a dielectric layer sandwiched between upper and lower conductive layers or between left and right conductive layers). Each capacitor 128 in tandem with its associated TFT structure 120 represents a single memory structure or memory cell for holding a single bit (e.g., a logic zero or one depending on the charge state of capacitor 128). This example shows TFT structure 120 contained within a single interconnect layer, but other embodiments may have TFT structures that extend vertically through two or more such interconnect layers. Further note that, in some embodiments, there is a relatively thin etch stop layer between adjacent interconnect layers, such as between any adjacent interconnect layers 110. Such etch stops may have a thickness in the range of, for example, 2 nm to 10 nm, and may include, for instance, silicon nitride, silicon oxynitride, or silicon oxycarbonitride, to name few examples.
As discussed above, the TFT structures 120 can suffer from process variations which can affect the stability and performance of the transistors. According to some embodiments, TFT structures 120 include one or more contacts that are doped to improve device stability and lower the contact resistance. The doping can occur at different times during the fabrication process to provide the desired doping profile within the contacts themselves and/or within the semiconductor region beneath the contacts. Further details of the fabrication process for a single TFT-based memory structure, including the doped contacts, are provided herein with respect to
TFT structures 120 are formed as individual islands in an array across the plurality of conductive traces 114, according to some embodiments. In this way, conductive traces 114 act as wordlines with each conductive trace 114 coupled to the gate(s) of one or more TFT structures 120 arranged along its length. In this example view, there are four conductive traces 114 shown, and there are three TFT structures 120 along the length of each conductive trace 114.
According to some embodiments, one of the source or drain contacts of TFT structures 120 in a same row are coupled to a same second conductive trace 124 that extends in a different direction (e.g., orthogonally) compared to conductive trace 114. A plurality of parallel second conductive traces 124 may each extend across any number of TFT structures and be coupled to the source or drain contact on each of the TFT structures in the row. In this example view, there are three conductive traces 124 shown, and there are four TFT structures 120 along the length of each conductive trace 124. Accordingly, any given TFT structure 120 of the array has its gate coupled to one of the conductive traces 114 (e.g., wordline) and one of its source or drain contacts coupled to one of the second conductive traces 124 (e.g., bitline) such that each of the TFT structures are individually addressable, in some examples. The other source or drain contact on each TFT structure 120 is coupled to its own conductive via 126, which acts like a conductive bridge between the TFT structure 120 and its corresponding capacitor 128. In an embodiment, TFT structures 120 are formed in a second interconnect layer over the first interconnect layer, second conductive traces 124 and conductive vias 126 are formed in a third interconnect layer over the second interconnect layer, and capacitors 128 are formed in a fourth interconnect layer over the third interconnect layer. In some other embodiments, note that one or more of TFT structures 120 may be a dummy structure (e.g., not connected into a working memory cell or otherwise non-functional).
Fabrication Methodology
The TFT-based memory structure may be part of an overall integrated circuit (e.g., such as a processor or memory chip, or a system-on-chip) that includes, for example, digital logic cells and/or memory cells and analog mixed signal circuitry. Example materials and process parameters are given, but other materials or parameters will be appreciated in light of this disclosure.
First conductive trace 204 may be formed, for example, by first forming a recess within a surrounding dielectric layer (not shown) followed by filling the recess with a conductive material, such as copper, that is deposited using any one of electroplating, electroless plating, CVD, or PECVD, to name a few examples. After deposition of the conductive material within the recess, a polishing process may be performed using, for example, chemical mechanical polishing (CMP) to planarize the given layer down to a top surface of first conductive trace 204. In some embodiments, a thin barrier layer is conformally deposited (e.g., via ALD or CVD) first along the inner surfaces of the recess prior to the deposition of the copper or other conductive fill material. The thin barrier layer may include, for example, tantalum or titanium, or a nitride of these, or some other electromigration inhibitor.
According to some embodiments, another dielectric layer 206 is deposited over first conductive trace 204, and a conductive via 208 is formed within dielectric layer 206 such that conductive via 208 is on first conductive trace 204. In some embodiments, conductive via 208 is one via of a plurality of such conductive vias formed within dielectric layer 206 along a length of first conductive trace 204 and along a length of other such conductive traces parallel to first conductive trace 204.
According to some embodiments, a gate electrode 210 is deposited on dielectric layer 206 and a top surface of conductive via 208. In some other embodiments, dielectric layer 206 is omitted such that gate electrode 210 is deposited directly on first conductive trace 204. In either case, gate electrode 210 is conductively coupled to first conductive trace 204 (either directly or through conductive via 208). As will be appreciated, this particular example refers to a backside-gate configuration, where the gate structure of the access device being formed is on a backside of the device, and the source and drain contacts of that device are on a frontside of the device. Such a configuration facilitates connectivity within a given memory array (e.g., sandwiching a TFT device between a wordline and a bitline), but other connectivity schemes may be used if device density constraints allow for same.
Gate electrode 210 may include any suitable conductive material such as polysilicon, a metal, or a metal alloy. Example suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. Note that gate electrode 210 may contain multiple layers, such as an inner plug or fill metal, with surrounding or outer work function material. According to some embodiments, gate electrode 210 includes one or more n-type work function metals such as platinum, gold, palladium, or cobalt. In some embodiments, gate electrode 210 includes one or more p-type work function metals such as titanium, titanium nitride, tantalum, or tantalum nitride.
According to some embodiments, a doping process can be performed to dope the exposed portions of semiconductor region 214 within recesses 226. Doing so provides dopants within semiconductor region 214 beneath the areas where the conductive contacts land upon the top surface of semiconductor region 214.
Any dopant elements may be used and may depend upon the metal oxide semiconductor material of semiconductor region 214. For example, a semiconductor region 214 rich in gallium can be doped with oxygen and a semiconductor region 214 rich in indium or zinc can be doped with nitrogen. Other dopant elements may include any of F, Cl, Al, Si, Ar, H, Ge, Mg, W, Hf, or Co, to name a few examples. The doping may be performed by any suitable doping process, such as ion implantation, plasma treatment, diffusion, wet chemical surface treatment, or annealing. According to some embodiments, the doping process produces a concentration gradient of the dopants through a thickness of semiconductor region 214 within the regions identified by the dashed lines.
According to some embodiments, contact semiconductor layer(s) 230 may be doped to improve the conductivity of the contact by promoting higher carrier mobility. The doping may occur following the formation of contact semiconductor layer(s) 230 (e.g., before any metallization). Any dopant elements may be used and may depend upon the metal oxide semiconductor material of contact semiconductor layer(s) 230. For example, contact semiconductor layer(s) 230 that are rich in gallium can be doped with oxygen and contact semiconductor layer(s) 230 that are rich in indium or zinc can be doped with nitrogen. Other dopant elements may include any of F, Cl, Al, Si, Ar, H, Ge, Mg, W, Hf, or Co, to name a few examples. The doping may be performed by any suitable doping process, such as ion implantation, plasma treatment, diffusion, wet chemical surface treatment, or annealing. In the case of multiple contact semiconductor layers 230, each of the layers may be doped with a different element or elements. In one particular example, contact semiconductor layers 230 includes a tri-layer arrangement with a first indium-rich layer on semiconductor region 214, a second zinc-rich layer on the first layer, and a third gallium-rich layer on the second layer. According to some embodiments, the doping process produces a concentration gradient of the dopants through a thickness of contact semiconductor layer(s) 230.
In some embodiments, contact semiconductor layers 230 are not exposed during the doping process as damage may occur to the exposed surfaces.
Each of the semiconductor layers 214a-214c may include a different material composition and/or a different doping profile. In some embodiments, any of the semiconductor layers 214a-214c includes a graded doping concentration throughout a thickness of the layer. The description above regarding semiconductor region 214 applies to any of semiconductor layers 214a-214c. Accordingly, each of semiconductor layers 214a-214c may include a metal oxide semiconductor material having one or more dopants that can depend on the metal oxide semiconductor material. For example, a semiconductor layer rich in gallium can be doped with oxygen and a semiconductor layer rich in indium or zinc can be doped with nitrogen. Other dopant elements may include any of F, Cl, Al, Si, Ar, H, Ge, Mg, W, Hf, or Co, to name a few examples.
Second conductive trace 240 may be formed, for example, by first forming a recess within the surrounding dielectric material followed by filling the recess with a conductive material, such as copper, that is deposited using any one of electroplating, electroless plating, CVD, or PECVD, to name a few examples. After deposition of the conductive material within the recess, a polishing process may be performed using, for example, CMP to planarize a top surface of second conductive trace 240 with the surrounding dielectric material. In some embodiments, a thin barrier layer is conformally deposited (e.g., via ALD or CVD) first along the inner surfaces of the recess prior to the deposition of the remaining conductive material. The thin barrier layer may include, for example, tantalum or titanium, or a nitride of these. As discussed above, second conductive trace 240 may be one bitline of a plurality of parallel bitlines formed in the interconnect layer over the TFT structure. Accordingly, second conductive trace 240 may run into and out of the page orthogonally to first conductive trace 204. Second conductive trace 240 conductively contacts one of the contacts of the illustrated TFT structure and further contacts at least one of the contacts of other TFT structures along a row extending into and out of the page, according to some embodiments. Conductive via 242 may be conductively coupled only to one or more contacts of the illustrated TFT structure (and not coupled to any contacts of any other TFT structures). Conductive via 242 may include the same material composition and deposition process as second conductive trace 240.
In the TFT-based memory structure, capacitor 244 stores a bit of information and TFT structure 243 allows for writing and reading that bit. For example, capacitor 244 can either be charged to a first state or discharged to a second state, and these two states represent two bit values of 0 or 1. As illustrated in
According to some embodiments, one or more dielectric layers 252 are formed on electrode 248, prior to the formation of electrode 250. One or more dielectric layers 252 include any suitable dielectric material and form the “I” part of the MIM (metal-insulator-metal) capacitor 244. Note that one or more dielectric layers 252 may include one or more distinct and/or compositionally different layers of dielectric material. For example, one or more dielectric layers 252 may include one or more thin films of one or more metal oxides, such as one or more oxides of hafnium, aluminum, zirconium, titanium, tantalum, or another appropriate metal.
As can be further seen, chip package 300 includes a housing 304 that is bonded to a package substrate 306. The housing 304 may be any standard or proprietary housing, and may provide, for example, electromagnetic shielding and environmental protection for the components of chip package 300. The one or more dies 302 may be conductively coupled to a package substrate 306 using connections 308, which may be implemented with any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid array (BGA), pins, or wire bonds, to name a few examples. Package substrate 306 may be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between the faces of package substrate 306, or between different locations on each face. In some embodiments, package substrate 306 may have a thickness less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of package geometries can be used. Additional conductive contacts 312 may be disposed at an opposite face of package substrate 306 for conductively contacting, for instance, a printed circuit board (PCB). One or more vias 310 extend through a thickness of package substrate 306 to provide conductive pathways between one or more of connections 308 to one or more of contacts 312. Vias 310 are illustrated as single straight columns through package substrate 306 for ease of illustration, although other configurations can be used (e.g., damascene, dual damascene, through-silicon via, or an interconnect structure that meanders through the thickness of substrate 306 to contact one or more intermediate locations therein). In still other embodiments, vias 310 are fabricated by multiple smaller stacked vias, or are staggered at different locations across package substrate 306. In the illustrated embodiment, contacts 312 are solder balls (e.g., for bump-based connections or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). In some embodiments, a solder resist is disposed between contacts 312, to inhibit shorting.
In some embodiments, a mold material 314 may be disposed around the one or more dies 302 included within housing 304 (e.g., between dies 302 and package substrate 306 as an underfill material, as well as between dies 302 and housing 304 as an overfill material). Although the dimensions and qualities of the mold material 314 can vary from one embodiment to the next, in some embodiments, a thickness of mold material 314 is less than 1 millimeter. Example materials that may be used for mold material 314 include epoxy mold materials, as suitable. In some cases, the mold material 314 is thermally conductive, in addition to being electrically insulating.
Method 400 begins with operation 402 where a gate electrode is formed on an underlying interconnect layer within an interconnect region. According to some embodiments, the gate electrode is formed directly on an underlying conductive via while in other embodiments the gate electrode is formed directly on an underlying conductive trace (e.g., a wordline). The gate electrode may include any suitable conductive material such as polysilicon, a metal, or a metal alloy. Example suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. The gate electrode may contain multiple layers, such as an inner plug or fill metal, with surrounding or outer work function material. According to some embodiments, the gate electrode includes one or more n-type work function metals such as platinum, gold, palladium, or cobalt. In some embodiments, the gate electrode includes one or more p-type work function metals such as titanium, titanium nitride, tantalum, or tantalum nitride. The gate electrode may be deposited any suitable deposition technique, such as CVD, PVD, electroplating, or electroless plating.
Method 400 continues with operation 404 where a gate dielectric is formed over the gate electrode. The gate dielectric may be deposited, for example, to a thickness between about 2 nm and about 10. The gate dielectric may include any suitable dielectric material (such as silicon dioxide, and/or a high-k dielectric material) and deposited using any suitable deposition process, such as CVD, ALD, flowable CVD, or spin-on dielectric. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, and lead scandium tantalum oxide. In some cases, the gate dielectric may include multiple different layers, such as a first layer of high-k material (e.g., hafnium oxide) on the gate electrode and at least one other layer of lower-k oxide between the first layer and the semiconductor region that is ultimately formed over the gate dielectric.
Method 400 continues with operation 406 where a semiconductor region is formed over the gate dielectric. The semiconductor region may include any suitable semiconductor material, such as silicon or any III-V or II-VI materials exhibiting semiconducting qualities. The semiconductor region may be deposited to a thickness between about 5 nm and about 16 nm using any suitable deposition technique, such as CVD, PECVD, PVD, ALD, or epitaxial growth, to name a few examples.
Method 400 continues with operation 408 where other dielectric layers are formed over the semiconductor region. According to some embodiments, the other dielectric layers include a passivation layer having a dielectric material that protects the underlying semiconductor region. The passivation layer may include, for example, aluminum oxide, although other metal oxides may be used as well. Any number of passivation and/or interlayer dielectrics (ILD) can be deposited over the passivation layer. According to some embodiments, any of the other dielectric layers may include silicon oxide, silicon oxycarbide, silicon nitride, or silicon oxynitride, to name a few examples.
Method 400 continues with operation 410 where one or more contact openings are formed through the other dielectric layers. According to one example, an anisotropic etching process may be performed through a thickness of the other dielectric layers to expose at least a portion of the underlying semiconductor region. The etched contact openings may take the form of trenches that extend out to the edges of the TFT layers.
Method 400 optionally continues with operation 412 where the exposed portions of the semiconductor region within the contact openings are doped. Any dopant elements may be used and may depend upon the metal oxide semiconductor material of the semiconductor region. For example, a semiconductor region rich in gallium can be doped with oxygen and a semiconductor region rich in indium or zinc can be doped with nitrogen. Other dopant elements may include any of F, Cl, Al, Si, Ar, H, Ge, Al, Mg, W, Hf, or Co, to name a few examples. The doping may be performed by any suitable doping process, such as ion implantation, plasma treatment, diffusion, wet chemical surface treatment, or annealing.
Method 400 continues with operation 414 where one or more contact semiconductor layers are deposited within the contact openings and are doped. According to some embodiments, the one or more contact semiconductor layers include metal oxide semiconductor material such as indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium oxide (InO), or gallium zinc oxide (GaZnO), to name a few examples. Different dopants may be used depending on the metal oxide semiconductor material. For example, one or more contact semiconductor layers that are rich in gallium can be doped with oxygen and one or more contact semiconductor layers that are rich in indium or zinc can be doped with nitrogen. Other dopant elements may include any of F, Cl, Al, Si, Ar, H, Ge, Al, Mg, W, Hf, or Co, to name a few examples. The doping may be performed by any suitable doping process, such as ion implantation, plasma treatment, diffusion, wet chemical surface treatment, or annealing. In some embodiments, the doping is performed before any metallization occurs. In some embodiments, a thin film of metal is deposited over the one or more contact semiconductor layers before doping the one or more contact semiconductor layers.
A metal fill may be formed within any remaining volume of the contact recess after doping the one or more contact semiconductor layers. The metal fill may be any suitable interconnect contact metal, such as copper, ruthenium, tungsten, cobalt, molybdenum, titanium, tantalum, and alloys thereof. In some cases, the metal fill may be formed, for instance, using electroplating within the remaining volume of the contact recesses following the formation of the one or more contact semiconductor layers and the metal film.
Example System
Depending on its applications, computing system 500 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 502. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 500 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., a module including an integrated circuit having interconnect structures that include tiers of backend memory cells having a co-doped semiconductor region). In some embodiments, the inclusion of the backend memory cells may reduce the number of other DRAM chips included within computing system 500. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 506 can be part of or otherwise integrated into the processor 504).
The communication chip 506 enables wireless communications for the transfer of data to and from the computing system 500. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 504 of the computing system 500 includes an integrated circuit die packaged within the processor 504. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more semiconductor devices as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 506 also may include an integrated circuit die packaged within the communication chip 506. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 504 (e.g., where functionality of any chips 506 is integrated into processor 504, rather than having separate communication chips). Further note that processor 504 may be a chip set having such wireless capability. In short, any number of processor 504 and/or communication chips 506 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 500 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
It will be appreciated that in some embodiments, the various components of the computing system 500 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components or any suitable combination of hardware, firmware or software.
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
Example 1 is an integrated circuit that includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. The conductive contact comprises a contact semiconductor region and a metal fill. The contact semiconductor region has a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material.
Example 2 includes the subject matter of Example 1, further comprising a passivation layer between the semiconductor region and the one or more dielectric layers, such that the conductive contact extends through an entire thickness of the passivation layer.
Example 3 includes the subject matter of Example 2, wherein the passivation layer comprises aluminum and oxygen.
Example 4 includes the subject matter of any one of Examples 1-3, wherein the conductive contact is coupled to a metal-insulator-metal (MIM) capacitor.
Example 5 includes the subject matter of any one of Examples 1-4, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
Example 6 includes the subject matter of Example 5, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
Example 7 includes the subject matter of Example 5, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
Example 8 includes the subject matter of any one of Examples 1-7, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers, each layer of the plurality of contact semiconductor layers having a different material composition.
Example 9 includes the subject matter of Example 8, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile.
Example 10 includes the subject matter of any one of Examples 1-9, wherein the at least one dopant element comprises one or more of argon, hydrogen, germanium, nitrogen, chlorine, fluorine, aluminum, magnesium, oxygen, hafnium, tungsten, cobalt, or silicon.
Example 11 includes the subject matter of any one of Examples 1-10, wherein the conductive contact extends into one or more layers of the semiconductor region.
Example 12 includes the subject matter of Example 11, wherein the semiconductor region includes a plurality of compositionally distinct layers, and the conductive contact extends through an uppermost layer of the semiconductor region and lands on or within another layer of the semiconductor region.
Example 13 is a printed circuit board comprising the integrated circuit of any one of Examples 1-12.
Example 14 is an integrated circuit including a plurality of semiconductor devices, an interconnect region above the plurality of semiconductor devices and having a plurality of stacked interconnect layers; and a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers. The TFT structure includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. The conductive contact comprises a contact semiconductor region and a metal fill. The contact semiconductor region has a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material.
Example 15 includes the subject matter of Example 14, wherein the TFT structure further comprises a passivation layer between the semiconductor region and the one or more dielectric layers, such that the conductive contact extends through an entire thickness of the passivation layer.
Example 16 includes the subject matter of Example 15, wherein the passivation layer comprises aluminum and oxygen.
Example 17 includes the subject matter of any one of Examples 14-16, wherein the conductive contact is coupled to a metal-insulator-metal (MIM) capacitor.
Example 18 includes the subject matter of any one of Examples 14-17, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
Example 19 includes the subject matter of Example 18, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
Example 20 includes the subject matter of Example 18, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
Example 21 includes the subject matter of any one of Examples 14-20, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers, each layer of the plurality of contact semiconductor layers having a different material composition.
Example 22 includes the subject matter of Example 21, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile.
Example 23 includes the subject matter of any one of Examples 14-22, wherein the at least one dopant element comprises one or more of argon, hydrogen, germanium, nitrogen, chlorine, fluorine, aluminum, magnesium, oxygen, hafnium, tungsten, cobalt, or silicon.
Example 24 includes the subject matter of any one of Examples 14-23, wherein the TFT structure is a first TFT structure of an array of TFT structures within the one or more interconnect layers.
Example 25 is a printed circuit board comprising the integrated circuit of any one of Examples 14-24.
Example 26 is an electronic device including a chip package having one or more dies. At least one of the one or more dies includes a plurality of semiconductor devices, an interconnect region above the plurality of semiconductor devices and having a plurality of stacked interconnect layers; and a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers. The TFT structure includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. The conductive contact comprises a contact semiconductor region and a metal fill. The contact semiconductor region has a metal oxide semiconductor material and at least one dopant element different from the metal oxide semiconductor material.
Example 27 includes the subject matter of Example 26, wherein the TFT structure further comprises a passivation layer between the semiconductor region and the one or more dielectric layers, such that the conductive contact extends through an entire thickness of the passivation layer.
Example 28 includes the subject matter of Example 27, wherein the passivation layer comprises aluminum and oxygen.
Example 29 includes the subject matter of any one of Examples 26-28, wherein the conductive contact is coupled to a metal-insulator-metal (MIM) capacitor.
Example 30 includes the subject matter of any one of Examples 26-29, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
Example 31 includes the subject matter of Example 30, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
Example 32 includes the subject matter of Example 30, wherein the contact semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
Example 33 includes the subject matter of any one of Examples 26-32, wherein the contact semiconductor region comprises a plurality of contact semiconductor layers, each layer of the plurality of contact semiconductor layers having a different material composition.
Example 34 includes the subject matter of Example 33, wherein each layer of the plurality of contact semiconductor layers includes a different dopant profile.
Example 35 includes the subject matter of any one of Examples 26-34, wherein the at least one dopant element comprises one or more of argon, hydrogen, germanium, nitrogen, chlorine, fluorine, aluminum, magnesium, oxygen, hafnium, tungsten, cobalt, or silicon.
Example 36 includes the subject matter of any one of Examples 26-35, wherein the TFT structure is a first TFT structure of an array of TFT structures within the one or more interconnect layers.
Example 37 includes the subject matter of any one of Examples 26-36, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.
Example 38 is a method of forming an integrated circuit. The method includes forming a gate electrode on an underlying interconnect layer within an interconnect region over a plurality of semiconductor devices; forming a gate dielectric on the gate electrode; forming a semiconductor region on the gate dielectric; forming one or more dielectric layers over the semiconductor region; etching a recess through the one or more dielectric layers thus exposing a portion of the semiconductor region; forming at least one contact semiconductor layer within the recess; doping the at least one contact semiconductor layer with at least one dopant element; and forming a metal fill in the recess and over the at least one contact semiconductor layer.
Example 39 includes the subject matter of Example 38, wherein the at least one contact semiconductor layer comprises a metal oxide semiconductor material.
Example 40 includes the subject matter of Example 38 or 39, wherein the at least one contact semiconductor layer comprises oxygen, indium, gallium, and zinc.
Example 41 includes the subject matter of Example 40, wherein the semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one dopant element comprises nitrogen.
Example 42 includes the subject matter of Example 40, wherein the semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one dopant element comprises oxygen.
Example 43 includes the subject matter of any one of Examples 38-42, wherein forming the metal fill comprises forming a first metal layer over the at least one contact semiconductor layer and doping the at least one contact semiconductor layer through the first metal layer with the at least one dopant element.
Example 44 includes the subject matter of Example 43, wherein forming the metal fill comprises forming a second metal layer over the first metal layer, the second metal layer filling a remaining portion of the recess.
Example 45 is an integrated circuit that includes a plurality of semiconductor devices, an interconnect region above the plurality of semiconductor devices and having a plurality of stacked interconnect layers; and a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers. The TFT structure includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, one or more dielectric layers over the semiconductor region, and a conductive contact that extends through the one or more dielectric layers and contacts a portion of the semiconductor region. The conductive contact comprises a contact semiconductor region and a metal fill. The contact semiconductor region has a first dopant profile of at least one first dopant element, and the portion of the semiconductor region beneath the conductive contact has a second dopant profile of at least one second dopant element.
Example 46 includes the subject matter of Example 45, wherein the conductive contact is coupled to a metal-insulator-metal (MIM) capacitor.
Example 47 includes the subject matter of Example 45 or 46, wherein the contact semiconductor region comprises oxygen, indium, gallium, and zinc.
Example 48 includes the subject matter of Example 47, wherein the contact semiconductor region comprises a higher concentration of indium or zinc compared to any other elements, and the at least one first dopant element comprises nitrogen.
Example 49 includes the subject matter of Example 47, wherein the semiconductor region comprises a higher concentration of gallium compared to any other elements, and the at least one first dopant element comprises oxygen.
Example 50 includes the subject matter of any one of Examples 45-49, wherein the first dopant element is the same as the second dopant element.
Example 51 includes the subject matter of any one of Examples 45-50, wherein the first dopant profile comprises a dopant gradient of the first dopant element across any number of contact semiconductor layers in the contact semiconductor region.
Example 52 includes the subject matter of any one of Examples 45-51, wherein the second dopant profile comprises a dopant gradient of the second dopant element across any number of semiconductor layers in the semiconductor region.
Example 53 includes the subject matter of any one of Examples 45-52, wherein the at least one first and second dopant elements comprise one or more of argon, hydrogen, germanium, nitrogen, chlorine, fluorine, aluminum, magnesium, oxygen, hafnium, or silicon.
Example 54 includes the subject matter of any one of Examples 45-53, wherein the TFT structure is a first TFT structure of an array of TFT structures within the interconnect layer.
Example 55 is a printed circuit board comprising the integrated circuit of any one of Examples 45-54.
The foregoing description of the embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations will be apparent in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto.
