Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor

Abstract

A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application contains subject matter related to a concurrently filed U.S. patent application by Allen S. Yu, Thomas C. Scholer, and Paul J. teffan entitled “SEMICONDUCTOR WITH INCREASED GATE COUPLING COEFFICIENT AND MANUFACTURING METHOD THEREFOR”. The related application is assigned to Advanced Micro Devices, Inc. and is identified by Ser. No. 09/513,261.

TECHNICAL FIELD

The present invention relates generally to semiconductors and more specifically to high gate constant, shallow trench isolation semiconductor memory devices.

BACKGROUND ART

Flash EEPROMs (electrically erasable programmable read only memories) are a class of nonvolatile semiconductor memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon (poly) floating gate overlying the tunnel oxide; an interpoly dielectric overlying the floating gate; and a poly control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.

A Flash EEPROM also includes peripheral portions, which typically include input/output circuitry for selectively addressing individual memory cells.

The process of forming Flash EEPROM cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts”, must be made to connect the stack gated structure, the source region and the drain regions to other part of the chip.

The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch stop or liner layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide such as boro-phospho-tetra-ethyl-ortho silicate (BPTEOS) or borophosphosilicate glass (BPSG), is then deposited over the etch stop layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form a photoresist mask. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings in the oxide layer. The contact openings stop at the source and drain regions in the substrate. The photoresist mask is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called “self-aligned contacts” (conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process, which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.

For miniaturization, it is desirable to dispose the Flash EEPROM cells as closely together as possible. A commonly used process to achieve bit line isolation between the memory cells is local oxidation of silicon (LOCOS) isolation. This LOCOS process consumes silicon, which creates a surface area profile resembling a bird's beak. The reduction in silicon reduces density. The bird's beak surface area profile adds to the minimnum dimension between adjacent Flash EEPROM cells, and it is becoming more problematic as the distance between adjacent memory cells diminishes.

Another problem associated with the Flash EEPROM cells is maintaining the gate coupling coefficient (C G ). The C G is the ratio of the floating voltage with respect to the control voltage. A larger C G corresponds to greater device efficiency.

A solution, which would allow further miniaturization of semiconductor memory device without adversely affecting device performance has long been sought, but has eluded those skilled in the art. As the demand for higher performance devices and miniaturization continues at a rapid pace in the semiconductor field, it is becoming more pressing that a solution be found.

DISCLOSURE OF THE INVENTION

The present invention provides a method for reducing semiconductor device geometry by using shallow trench isolation for bit line isolation of floating gates.

The present invention provides a method for reducing semiconductor device geometry by eliminating the bird's beak phenomenon of local oxidation of silicon (LOCOS) isolation to enable semiconductor gate structures to be positioned closer together.

The present invention provides a method for forming a semiconductor device that provides increased gate coupling coefficient for greater device efficiency.

The present invention provides a method for forming a semiconductor device that increases the surface area of the insulator disposed between the control gate and the floating gate of an EEPROM device for greater device efficiency.

The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (PRIOR ART) is a cross-section view of a conventional semiconductor memory device;

FIG. 2 (PRIOR ART) is a cross-section view of an alternative isolation scheme for a conventional semiconductor memory device;

FIG. 3 is a cross-section view of a semiconductor device in an intermediate state of processing according to the present invention;

FIGS. 4A , 4 B, and 4 C are cross-section views after a step of etching the exposed shallow trench isolation (STI) with respective anisotropic, isotropic and combination etches to produce characteristic surface area profiles;

FIGS. 5A , 5 B, and 5 C are cross-section views after a step of removing the photoresist mask, growing a tunnel oxide (TOX) layer, and depositing a first poly (poly) layer over the entire surface;

FIGS. 6A , 6 B, and 6 C are cross-section views of the present invention which are equivalent to FIG. 2 ;

FIGS. 7A , 7 B, and 7 C are cross-section views after a step of chemical-mechanical polishing (CMP) of the entire surface stopping at the top surface of the STIs;

FIG. 8 illustrates an alternative embodiment manufactured using a conventional photoresist mask; and

FIG. 9 illustrates the semiconductor device after the step of trimming the conventional photoresist mask according to the alternative embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to FIG. 1 (PRIOR ART), therein is shown a cross section of a conventional semiconductor memory device 100 , such as a Flash EEPROM (electrically erasable programmable read only memory), in an intermediate state of processing. The structure shown is the result of a “bit-line” isolation technique called the “local oxidation of silicon” (LOCOS) isolation for making a floating gate. At this stage of processing, the floating gate for the semiconductor memory device 100 is shown on a semiconductor substrate 102 , generally of doped silicon, with field oxide (FOX) regions 104 and 105 , a tunnel oxide (TOX) layer 106 , a first polysilicon (poly) layer 108 , an oxynitride (ONO) layer 110 , and a second poly layer 112 sequentially deposited on the semiconductor substrate 102 . The width of the floating gate is given by W F and the width of the control gate by W C .

A floating gate operates at greatest efficiency when the gate coupling coefficient (C G ) is the largest. The C G is directly proportional to the ratio of the floating voltage with respect to the control voltage: $$ V = Q C $$ the ⁢   ⁢ floating ⁢   ⁢ gate ⁢   ⁢ voltage , V F = Q C TOX = ( Q ) ⁢ ( T TOX ) ( A TOX ) ⁢ ( K TOX ) $$ since ⁢   ⁢ C TOX = A TOX T TOX ⁢ ( K TOX )

Since they are in series, the reciprocal of the total capacitance will equal the sum of the reciprocals of the device's coupled capacitors: $$ 1 C TOTAL = 1 C TOX + 1 C ONO therefore ⁢   ⁢ control ⁢   ⁢ voltage , V C = Q C TOTAL = Q C TOX + Q C ONO and ⁢   ⁢ since ⁢   ⁢ C TOX = A ONO T ONO ⁢ ( K ONO ) V C = ( Q ) ⁢ ( T TOX ) ( A TOX ) ⁢ ( K TOX ) + ( Q ) ⁢ ( T ONO ) ( A ONO ) ⁢ ( K ONO ) By ⁢   ⁢ definition : C G = V F V C So , C G = ( Q ) ⁢ ( T TOX ) ( A TOX ) ⁢ ( K TOX ) Q ⁡ ( T TOX ( A TOX ) ⁢ ( K TOX ) + T ONO ( A ONO ) ⁢ ( K ONO ) ) For ⁢   ⁢ simplicity , assume ⁢   ⁢ K TOX ≅ K ONO

Since the word line completely overlays the floating gates 108 , the surface area that they couple is best described as W=the width of the ONO layer sandwiched between the two poly layers. $$ So ⁢   ⁢ the ⁢   ⁢ ratio ⁢   ⁢ of : A TOX A ONO = W F W C Therefore , C G = 1 1 + ( A TOX A ONO ) ⁢ ( T ONO T TOX ) = W C W C + W F ⁡ ( T ONO T TOX ) So ⁢   ⁢ C G ⁢   ⁢   ⁢ will ⁢   ⁢ increase ⁢   ⁢ as ⁢   ⁢ W F W C ⁢   ⁢ decreases . C TOX = Tunnel ⁢   ⁢ oxide ⁢   ⁢ capacitance C ONO = ONO ⁢   ⁢ capacitance A TOX = Surface ⁢   ⁢ area ⁢   ⁢ of ⁢   ⁢ tunnel ⁢   ⁢ capacitor A ONO = Surface ⁢   ⁢ area ⁢   ⁢ of ⁢   ⁢ ONO ⁢   ⁢ capacitor T TOX = Tunnel ⁢   ⁢ oxide ⁢   ⁢ thickness T ONO = ONO ⁢   ⁢ thickness

In its reduced form, C G is a function of the ratio of the width of the floating gate (W F ) and the width of the control gate (W C ). The larger W C is relative to W F , the greater the device efficiency.

During LOCOS, as the semiconductor substrate 102 is consumed by the oxide, the FOX regions 104 and 105 grow under the TOX layer 106 causing bird's beaks 114 . With dimensions shrinking for ever tighter geometry and greater memory cell density, the LOCOS process becomes inadequate because the bird's beaks 114 encroachment becomes proportionately too large.

Referring now to FIG. 2 (PRIOR ART), therein is shown a relatively new isolation structure in an intermediate state of processing for another conventional semiconductor memory device 200 . The structure now coming into use is the result of a “bit-line” isolation technique called “shallow trench isolation”(STI). At this stage of processing, the floating gate for the Flash EEPROM is shown on a semiconductor substrate 201 with an oxide, shallow trench isolations (STIS) 216 - 218 , a TOX layer 206 , a first poly layer 208 , an ONO layer 210 , and a second poly layer 212 deposited on the semiconductor substrate 202 . This process does not have the bird's beak surface area profile and thus allows for greater density over the LOCOS process. However, the tighter pitch among the STIs 216 - 218 and the more vertical surface area profile of the first poly layer 208 lessens the surface area of the ONO 25 layer 210 . The ONO surface area is directly proportional to C G and is a contributing factor in determining the C G . The lower the ONO surface area the lower the C G . Accordingly, the present STI approach permits greater density of the semiconductor memory devices but lessens the efficiency of each semiconductor memory device.

Referring now to FIGS. 3 through 6 , therein are shown the sequence of process steps for forming a floating gate for an EEPROM device formed on a semiconductor substrate in accordance with the present invention.

Referring now to FIG. 3 , therein is shown a cross section of a semiconductor memory device 300 in an intermediate state of processing. At this stage are shown a semiconductor substrate 302 , embedded STIs 316 - 318 , and a photoresist mask 322 centered on top of each of the STIs 316 - 318 . The STIs 316 - 318 are formed conventionally using processing techniques well known in the art of semiconductor processing. A filn (not shown), preferably silicon nitride, is used to define the height of the STIs 316 - 318 that is exposed above the semiconductor substrate 302 . The photoresist mask 322 is placed above each of the STIs 316 - 318 . For simplicity of illustration, only three of the STIs 316 - 318 are shown.

Referring now to FIG. 4A , therein is shown the semiconductor memory device 300 after the step of etching the exposed STIs 316 - 318 with an anisotropic etch to create the STIs 316 A- 318 A having the single curved surface area profiles 320 A.

Referring now to FIG. 4B , therein is shown the semiconductor memory device 300 after the step of etching the exposed STIs 316 - 318 with an anisotropic etch to create the STIs 316 B- 318 B having the T-shaped surface area profiles 320 B.

Referring now to FIG. 4C , therein is shown the semiconductor memory device 300 after the step of etching the exposed STIs 316 - 318 with an initial isotropic etch to about the midpoint of the exposed STIs 316 - 318 followed by an anisotropic etch to create the STIs 316 C- 318 C having the multi-curved surface area profiles 320 C.

As seen from FIGS. 4A-4C , the different etch processes provide different surface area profiles 320 A- 320 C and different combinations of W F and W C .

Referring now to FIGS. 5A , 5 B, and 5 C, therein are shown the respective FIGS. 4A , 4 B, and 4 C semiconductor memory devices 300 A- 300 C after the steps of removing the photoresist mask 322 , growing TOX layers 306 A- 306 C, respectively, and depositing a first poly layer 308 A- 308 C, respectively. It will be noted that the TOX layers 306 A- 306 C are conformal and have surface area profiles that match the surface area profiles of the STI surface area profiles 320 A- 320 C.

The TOX layers 306 A-C are thin and use the silicon in the semiconductor substrate 302 as a silicon source for formation. Thus, the TOX layers 306 A-C are not formed on top of the STIs 316 A- 316 C through 318 A- 318 C since they contain no silicon.

Specifically, FIG. 5A shows a semiconductor memory device 300 A after the step of removing the photoresist mask 322 , growing the TOX layer 306 A, and depositing a first poly layer 308 A over the entire surface. FIG. 5B shows a semiconductor memory device 300 B after the step of removing the photoresist mask 322 , growing the TOX layer 306 B and depositing a first poly layer 308 B over the entire surface. FIG. 5C shows a semiconductor memory device 300 C after the step of removing the photoresist mask 322 , growing the TOX layer 306 C, and depositing a first poly layer 308 C over the entire surface.

Referring now to FIGS. 6A , 6 B, and 6 C, therein are shown the semiconductor memory devices 300 A- 300 C after the step of chemical-mechanical polishing (CMP) of the first poly layers 308 A- 308 C, respectively, stopping at the top surfaces of the STIs 316 A- 318 A through 316 C- 318 C, respectively. For FIG. 6A , the surface area profile of the first poly layer 308 A among the STIs 316 A- 316 C appears as large curves. For FIG. 6B , the surface area profile of the first poly layer 308 B among the STIs 317 A- 317 C appears as multiple slight curves. For FIG. 6C , the surface area profile of the first poly layer 308 C among the STIs 316 A- 316 C appears as slight curves. It would be understood that the first poly layers 308 A- 308 C would appear flat if the layers were sufficiently thick.

Referring now to FIGS. 7A , 7 B, and 7 C, therein are shown the semiconductor memory devices 300 A- 300 C after the steps of forming ONO layers 310 A- 310 C on top of the first poly layers 308 A- 308 C, respectively, and depositing second poly layers 312 A- 312 C on top of the ONO layers 310 A- 310 C, respectively. The etching of the STIs provides increased surface area profiles for the ONO layers 310 A- 310 C which improves the device efficiencies of the semiconductor devices 300 A- 300 C.

For FIG. 7A , the surface area profile of the STIs 316 A- 318 A appears as large concave curves. For FIG. 7B , the surface area profile of the STIs 316 B- 318 B appears as multiple small curves including small concave curves. For FIG. 7C , the surface area profile of the STIs 316 C- 318 C appears as multiple small and large concave curves. In each embodiment, the top concave curve is adjacent the ONO layers 310 A-C. It would be understood that the second poly layers 312 A- 312 C are flattened out by the underlying STI's and the first poly layers 320 A-C and would appear flat if the layers were sufficiently thick.

The ratio of W C and W F is large and the surface area for the ONO layers 310 A- 310 C is also increased level by the varying pitch of the first poly layers 308 A- 308 C. Accordingly, a gate structure for EEPROMS having STIs to achieve bit line isolation and high device efficiency is provided. The STIs afford production of EEPROM cells with greater density for tighter geometry and greater memory cell density.

Referring now to FIG. 8 , therein is shown a cross section of a semiconductor memory device 400 in an intermediate state of processing where STIs 416 - 418 have had a conventional photoresist mask 422 deposited and developed.

In the normal course of events, smaller semiconductor geometry requires the use of a more expensive, lithographic illuminating radiation source to print a minimum feature size image in the photoresist mask 422 . The present invention eliminates the need for this more expensive equipment by using an additional step of trimming the photoresist mask 422 .

Referring now to FIG. 9 , therein is shown the semiconductor memory device 400 after a step of trimming the photoresist mask 422 on top of the STIs 416 - 418 . Dotted lines show the outline of the original photoresist mask 422 . A short, well-controlled plasma stripping process employing oxygen chemistry is used to trim the photoresist mask.

The trimming of the photoresist mask 422 is followed by one of the etching steps of FIGS. 4A-4C to obtain the desired surface area profile but with smaller semiconductor geometry. Accordingly, using this additional step provides similar results as those achieved with more precise and more expensive lithographic illuminating radiation sources.

In summary, FIGS. 3 through 6C illustrate an embodiment of the present invention for fabricating a semiconductor floating gate for an EEPROM with STIs for isolation of the bit lines. A photoresist is deposited, patterned using conventional lithographic illuminating radiation sources, and developed. The photoresist acts as a mask during the anisotropic, isotropic, or combination anisotropic/isotropic etch to achieve increased surface area profiles of the STIs. The increased surface area profiles for the subsequently formed ONO layer increase the C G for the devices. Accordingly, the present invention provides gate structures having STIs that afford higher C G .

Alternatively and/or in addition, the photoresist mask is trimmed in-situ with the short, well-controlled, plasma oxide etch employing an oxygen containing chemistry in combination with some polymer forming gas species prior to the STI etch. This reduces the size of the resist and allows closer spacing and more precisely defined STI surface area profiles which result in more dense geometry.

The present invention involves a double self-alignment process. In the first self-alignment, the step of chemical-mechanical polishing (CMP) of the first poly layers 308 A- 308 C, respectively, and stopping at the top surfaces of the STIs 316 A- 318 A through 316 C- 318 C, respectively, aligns the floating gates.

In the second self-alignment, the large overlay tolerance for the STI resist is compensated. Since there is a high likelihood that the resist, which forms the STI, will cover part of the active silicon, the resist trimming process reduces the size of the resist in all directions so that it will self-align or cover only the STI and not the active silicon region. This is exemplified by the placement of the resist mask 322 or 422 . The resist mask 322 needs perfect alignment within the STIs 316 C, 317 C, and 318 C, and is a critical mask since it requires an expensive radiation source or complex (phase shift) mask to print. The present invention allows a standard I-line radiation source to be used and the resist mask trimmed to fit inside the STIs 316 - 318 .

While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations, which fall within the spirit and scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims

1. A semiconductor device comprising:a semiconductor substrate; insulator shallow trench isolations (STIs) having selected surface area profiles and disposed in the semiconductor substrate, the selected surface area profiles including multiple first and second concave curves, the multiple first concave curves having greater radii than the radii of the multiple second concave curves; a tunnel oxide (TOX) layer disposed on the semiconductor substrate between the shallow trench isolations; a first polysilicon (poly) layer disposed over the TOX layer and between the insulator shallow trench isolations to form a floating gate; an oxynitride (ONO) layer disposed over the first poly layer and the shallow trench isolations, the shallow trench isolation having the multiple first concave curves adjacent the ONO layer; and a second poly layer disposed over the ONO layer to form a control gate.

2. The semiconductor device as claimed in claim 1 wherein the selected surface area profiles include the multiple first concave curves above the multiple second concave curves.

3. The semiconductor device as claimed in claim 1 wherein the selected surface area profiles include multiple convex curves.

4. The semiconductor device as claimed in claim 1 wherein the selected surface area profiles include multiple convex curves having the same radii as the multiple second concave curves.

5. The semiconductor device as claimed in claim 1 wherein the selected surface area profiles include the multiple first and second concave curves joined by multiple convex curves.

6. The semiconductor device as claimed in claim 1 wherein the STIs have top surfaces and the ONO layer extends below the top surfaces of the STIs.

7. The semiconductor device as claimed in claim 1 wherein the STIs have top surfaces and the ONO layer has a curve extending below the top surfaces of the STIs.

8. The semiconductor device as claimed in claim 1 wherein the STIs have top surfaces and the ONO layer has a upward concave curve extending below the top surfaces of the STIs.

9. The semiconductor device as claimed in claim 1 wherein the STIs have flat top surfaces and the ONO layer has a flat portion on and extending beyond the top surfaces of the STIs.