Patent Application
20090045475
Conventional integrated processing chips, also referred to as semiconductor devices, are generally manufactured with a signal processing circuit located on one side of the chip. Recently, signal processing circuits have been formed using both sides of the chip with through-wafer vias and back-side interconnections providing electronic communication from one device or circuit element to the other. Some integrated processing chips have begun to integrate fabricated sensing elements and control circuitry on a front side of a wafer. Other integrated processing chips are more segregated in that the sensing elements and the signal processing circuitry are located adjacent one another on a same side of the chip.
The present invention provides a high density integrated processing and sensing chip having an integrated signal processing circuit on one side and a magnetic sensor element on the other side of a single chip. In one embodiment, the integrated signal processing circuit and the magnetic sensor are electrically connected to one another through vias or through metallic trace elements or through package assembly.
In one aspect of the invention, an integrated chip includes a substrate; a signal processing control circuit supportably arranged on a first side of the substrate; and a magnetic sensor element supportably positioned on an opposing side of the substrate.
In another aspect of the invention, a method for manufacturing a double-sided integrated chip includes arranging a signal processing control circuit on a first surface of the substrate; arranging a magnetic sensor element on an opposite surface of the substrate; and electrically connecting the signal processing control circuit with the magnetic sensor element.
In yet another aspect of the invention, a method for manufacturing a double-sided integrated chip includes arranging a signal processing control circuit on a first wafer; arranging a magnetic sensor element on a second wafer; and attaching the first wafer and the second wafer to a substrate, wherein the signal processing control circuit is positioned on an opposite of the substrate from the magnetic sensor element.
Preferred and alternative embodiments of the present invention are described in detail below with reference to the following drawings:
At least one embodiment is generally directed to an integrated processing and sensing chip that is as small as possible in terms of size and weight using known semiconductor fabrication techniques. Many magnetic sensor applications require miniature magnetic sensing elements and signal processing circuitry integrated on a single substrate. The substrate may be silicon or an equivalent semiconductor material such as gallium arsenide, Germanium or Indium Phosphide, etc.
In a preferred embodiment, the integrated processing and sensing chip is a high density, multi-functional chip with a silicon substrate structure that supports a magnetic sensor element on one side of the substrate and control circuitry on an opposing side of the substrate. Forming the chip with the magnetic sensor element and the control circuitry on opposing sides of the substrate advantageously reduces the overall size of the chip while managing to increase the chip's overall functionality. By way of example, applicants have found during the development of the invention that locating the control circuitry on one side of the substrate and the magnetic sensor element on the other side may reduce the overall size of the chip by about fifty percent (50%). In addition, forming connections to both sides of the chip may also help reduce the overall size of the chip. The integrated processing and sensing chip simplifies the integration of both processing and sensing functions, provides greater flexibility during fabrication of the chip because the front and back sides of the chip may be fabricated in different parts of a facility or even in different facilities. Consequently, the integrated processing and sensing chip may provide manufacturing, functionality, size, weight, and economic advantages
In the illustrated embodiment, the signal processing circuit 102 is positioned on a first optional layer 103, which may be a silicon layer located adjacent the first surface 104 of the substrate layer 106. In addition, a dielectric layer 112, which may be made of Silicon Dioxide, helps protect the signal processing circuit 102 and is located at least partially on an exterior surface 114 of the signal processing circuit 102. The magnet sensor element 108, on the other hand, abuts the opposite surface 110 of the substrate layer 106. Layer 107 is another dielectric layer, which may be made from silicon dioxide and helps protect the magnetic sensor element 108. Layer 107 is located adjacent the opposite surface 110 of the substrate layer 106.
In one embodiment, vias 116 are formed through the substrate layer 106. Metal trace elements 118, such as an aluminum alloy or other conductive element, are provided adjacent the vias 116 to provide an electronic communication path between a circuit interconnection layer 120 and a sensor interconnection layer 122. The circuit interconnection layer 120 may be coupled to the trace elements 118 using an intermediate a circuit connection element 124 that extends through the circuit protection layer 112. The sensor interconnection layer 122 is arranged such that a majority of the sensor interconnection layer 122 abuts the dielectric layer 107 while another portion 126 is in direct contact with the magnetic sensor element 108.
The integrated processing and sensing wafer 100 further includes a first scratch protection layer 128 located on the circuit interconnection layer 120 and a second scratch protection layer 130 located on the sensor interconnection layer 122. The scratch protection layer may be silicon nitride or other similar, scratch resistant material. In addition, openings 132 are etched in at least the first scratch protection layer 128 for wire bond or solder bump connections and it is appreciated that similar opening may be etched or formed in the second scratch protection layer 130.
By way of example, there are several techniques of forming the wafer 100. In one embodiment, the signal processing circuit 102 and the magnetic sensor element 108 are fabricated separately and then later combined to complete the wafer 100. By way of example, the signal processing circuit 102 may be fabricated as a first layer and the magnetic sensor element 108, which may include one or more miniature magnetic sensor elements, may be fabricated as a second layer. The assembly comprised of layers 102 with 103 and 107 with 108 may be bonded to the substrate layer 106 using an adhesive or a spin-on glass layer, for example. With this technique, electrical connections between the signal processing circuit 102 and the magnetic sensor element 108 may be provided using wire bond or solder bump connections coupled to an externally conductive frame (not shown).
In another embodiment, the signal processing circuit 102 and the magnetic sensor element 108 are fabricated as a single unit. In this embodiment, the electrical connections between the signal processing circuit 102 and the magnetic sensor element 108 may provided the vias 116 and metal trace elements 118 as described above.
The primary difference between the present embodiment 200 and the above-described embodiment 100 is that the present embodiment 200 does not include any vias 116 (
The magnetic sensor elements 108, 208 may be formed using known technologies, such as Hall, anisotropic magnetoresistance (AMR), giant magnetoresistance (GMR), and giant magneto-impedance (GMI), all of which are thin film technologies that are generally compatible with integrated circuit fabrication.
While the preferred embodiment of the invention has been illustrated and described, as noted above, many changes can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is not limited by the disclosure of the preferred embodiment. Instead, the invention should be determined entirely by reference to the claims that follow.
