Patent Grant
8224281
1. Field of the Invention
The present invention relates to down-conversion and up-conversion of electromagnetic (EM) signals. More particularly, the present invention relates to reducing or eliminating DC offset voltages and re-radiation that occurs during down-conversion of EM signals to intermediate frequency or baseband signals.
2. Related Art
Electromagnetic (EM) information signals (baseband signals) include, but are not limited to, video baseband signals, voice baseband signals, computer baseband signals, etc. Baseband signals include analog baseband signals and digital baseband signals.
It is often beneficial to propagate EM signals at higher frequencies. This is generally true regardless of whether the propagation medium is wire, optic fiber, space, air, liquid, etc. To enhance efficiency and practicality, such as improved ability to radiate and added ability for multiple channels of baseband signals, up-conversion to a higher frequency is utilized. Conventional up-conversion processes modulate higher frequency carrier signals with baseband signals. Modulation refers to a variety of techniques for impressing information from the baseband signals onto the higher frequency carrier signals. The resultant signals are referred to herein as modulated carrier signals. For example, the amplitude of an AM carrier signal varies in relation to changes in the baseband signal, the frequency of an FM carrier signal varies in relation to changes in the baseband signal, and the phase of a PM carrier signal varies in relation to changes in the baseband signal.
In order to process the information that was in the baseband signal, the information must be extracted, or demodulated, from the modulated carrier signal. However, because conventional signal processing technology is limited in operational speed, conventional signal processing technology cannot easily demodulate a baseband signal from higher frequency modulated carrier signal directly. Instead, higher frequency modulated carrier signals must be down-converted to an intermediate frequency (IF), from where a conventional demodulator can demodulate the baseband signal.
Conventional down-converters include electrical components whose properties are frequency dependent. As a result, conventional down-converters are designed around specific frequencies or frequency ranges and do not work well outside their designed frequency range.
Conventional down-converters generate unwanted image signals and thus must include filters for filtering the unwanted image signals. However, such filters reduce the power level of the modulated carrier signals. As a result, conventional down-converters include power amplifiers, which require external energy sources.
When a received modulated carrier signal is relatively weak, as in, for example, a radio receiver, conventional down-converters include additional power amplifiers, which require additional external energy.
Briefly stated, the present invention is directed to methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal, and applications thereof. The present invention is further directed to reducing or eliminating DC offset voltages and re-radiation generated when down-converting an electromagnetic (EM) signal. The present invention is still further directed to improving receiver dynamic range.
Generally, the invention operates by receiving an EM signal. The invention also receives an aliasing signal having an aliasing rate. The invention aliases the EM signal according to the aliasing signal to down-convert the EM signal.
In an embodiment, the invention down-converts the EM signal to an intermediate frequency (IF) signal.
In another embodiment, the invention down-converts the EM signal to a demodulated baseband information signal.
In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.
In another embodiment, the EM signal is an I/Q modulated signal, which is down-converted to an in-phase information signal and a quadrature-phase information signal.
The invention is applicable to any type of EM signal, including but not limited to, modulated carrier signals (the invention is applicable to any modulation scheme or combination thereof) and unmodulated carrier signals.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is generally indicated by the left-most digit(s) in the corresponding reference number.
The invention shall be described with reference to the accompanying figures, wherein:
The present invention is directed to receivers implemented using universal frequency translation (UFT) modules. The UFT modules perform frequency translation operations. Embodiments of the present invention incorporating various applications of the UFT module are described below.
Receivers exhibit multiple advantages by using UFT modules. These advantages include, but are not limited to, lower power consumption, longer power source life, fewer parts, lower required package size, lower package weight, lower cost, less tuning, and more effective signal transmission and reception. The receivers of the present invention can receive and transmit signals across a broad frequency range. Furthermore, the DC offset voltages and re-radiation generated by receivers are the present invention are reduced or eliminated in embodiments. The structure and operation of embodiments of the UFT module, and various applications of the same, utilizing DC offset/re-radiation reduction, are described in detail in the following sections.
2. Universal Frequency Translation
The present invention is related to frequency translation, and applications of same. Such applications include, but are not limited to, frequency down-conversion, frequency up-conversion, enhanced signal reception, unified down-conversion and filtering, and combinations and applications of same.
As indicated by the example of
Generally, the UFT module 102 (perhaps in combination with other components) operates to generate an output signal from an input signal, where the frequency of the output signal differs from the frequency of the input signal. In other words, the UFT module 102 (and perhaps other components) operates to generate the output signal from the input signal by translating the frequency (and perhaps other characteristics) of the input signal to the frequency (and perhaps other characteristics) of the output signal.
An example embodiment of the UFT module 103 is generally illustrated in
As noted above, some UFT embodiments include other than three ports. For example, and without limitation,
The UFT module is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications.
For example, a UFT module 115 can be used in a universal frequency down-conversion (UFD) module 114, an example of which is shown in
As another example, as shown in
These and other applications of the UFT module are described below. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. In some applications, the UFT module is a required component. In other applications, the UFT module is an optional component.
3. Frequency Down-Conversion
The present invention is directed to systems and methods of universal frequency down-conversion, and applications of same.
In particular, the following discussion describes down-converting using a Universal Frequency Translation Module. The down-conversion of an EM signal by aliasing the EM signal at an aliasing rate is fully described in co-pending U.S. patent application entitled “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference. A relevant portion of the above mentioned patent application is summarized below to describe down-converting an input signal to produce a down-converted signal that exists at a lower frequency or a baseband signal.
In one implementation, aliasing module 2000 down-converts the input signal 2004 to an intermediate frequency (IF) signal. In another implementation, the aliasing module 2000 down-converts the input signal 2004 to a demodulated baseband signal. In yet another implementation, the input signal 2004 is a frequency modulated (FM) signal, and the aliasing module 2000 down-converts it to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal. Each of the above implementations is described below.
In an embodiment, the control signal 2006 includes a train of pulses that repeat at an aliasing rate that is equal to, or less than, twice the frequency of the input signal 2004. In this embodiment, the control signal 2006 is referred to herein as an aliasing signal because it is below the Nyquist rate for the frequency of the input signal 2004. Preferably, the frequency of control signal 2006 is much less than the input signal 2004.
A train of pulses 2018 as shown in
Exemplary waveforms are shown in
As noted above, the train of pulses 2020 (i.e., control signal 2006) control the switch 2008 to alias the analog AM carrier signal 2016 (i.e., input signal 2004) at the aliasing rate of the aliasing signal 2018. Specifically, in this embodiment, the switch 2008 closes on a first edge of each pulse and opens on a second edge of each pulse. When the switch 2008 is closed, input signal 2004 is coupled to the capacitor 2010, and charge is transferred from the input signal 2004 to the capacitor 2010. The charge transferred during a pulse is referred to herein as an under-sample. Exemplary under-samples 2022 form down-converted signal portion 2024 (
The waveforms shown in
The aliasing rate of control signal 2006 determines whether the input signal 2004 is down-converted to an IF signal, down-converted to a demodulated baseband signal, or down-converted from an FM signal to a PM or an AM signal. Generally, relationships between the input signal 2004, the aliasing rate of the control signal 2006, and the down-converted output signal 2012 are illustrated below:
(Freq. of input signal 2004)=n·(Freq. of control signal 2006)±(Freq. of down-converted output signal 2012)
For the examples contained herein, only the “+” condition will be discussed. The value of n represents a harmonic or sub-harmonic of input signal 2004 (e.g., n=0.5, 1, 2, 3, . . . ).
When the aliasing rate of control signal 2006 is off-set from the frequency of input signal 2004, or off-set from a harmonic or sub-harmonic thereof, input signal 2004 is down-converted to an IF signal. This is because the under-sampling pulses occur at different phases of subsequent cycles of input signal 2004. As a result, the under-samples form a lower frequency oscillating pattern. If the input signal 2004 includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the down-converted IF signal. For example, to down-convert a 901 MHZ input signal to a 1 MHZ IF signal, the frequency of the control signal 2006 would be calculated as follows:
(Freqinput−FreqIF)/n=Freqcontrol
(901MHZ−1MHZ)/n=900/n
For n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 2006 would be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.
Exemplary time domain and frequency domain drawings, illustrating down-conversion of analog and digital AM, PM and FM signals to IF signals, and exemplary methods and systems thereof, are disclosed in co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.
Alternatively, when the aliasing rate of the control signal 2006 is substantially equal to the frequency of the input signal 2004, or substantially equal to a harmonic or sub-harmonic thereof, input signal 2004 is directly down-converted to a demodulated baseband signal. This is because, without modulation, the under-sampling pulses occur at the same point of subsequent cycles of the input signal 2004. As a result, the under-samples form a constant output baseband signal. If the input signal 2004 includes lower frequency changes, such as amplitude, frequency, phase, etc., or any combination thereof, the charge stored during associated under-samples reflects the lower frequency changes, resulting in similar changes on the demodulated baseband signal. For example, to directly down-convert a 900 MHZ input signal to a demodulated baseband signal (i.e., zero IF), the frequency of the control signal 2006 would be calculated as follows:
(Freqinput−FreqIF)/n=Freqcontrol
(900MHZ−0MHZ)/n=900MHZ/n
For n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 2006 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc.
Exemplary time domain and frequency domain drawings, illustrating direct down-conversion of analog and digital AM and PM signals to demodulated baseband signals, and exemplary methods and systems thereof, are disclosed in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.
Alternatively, to down-convert an input FM signal to a non-FM signal, a frequency within the FM bandwidth must be down-converted to baseband (i.e., zero IF). As an example, to down-convert a frequency shift keying (FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (a subset of PM), the mid-point between a lower frequency F1 and an upper frequency F2 (that is, [(F1+F2)÷2]) of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F1 equal to 899 MHZ and F2 equal to 901 MHZ, to a PSK signal, the aliasing rate of the control signal 2006 would be calculated as follows:
Frequency of the down-converted signal=0 (i.e., baseband)
(Freqinput−FreqIF)/n=Freqcontrol
(900MHZ−0MHZ)/n=900MHZ/n
For n=0.5, 1, 2, 3, etc., the frequency of the control signal 2006 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. The frequency of the down-converted PSK signal is substantially equal to one half the difference between the lower frequency F1 and the upper frequency F2.
As another example, to down-convert a FSK signal to an amplitude shift keying (ASK) signal (a subset of AM), either the lower frequency F1 or the upper frequency F2 of the FSK signal is down-converted to zero IF. For example, to down-convert an FSK signal having F1 equal to 900 MHZ and F2 equal to 901 MHZ, to an ASK signal, the aliasing rate of the control signal 2006 should be substantially equal to:
(900MHZ−0MHZ)/n=900MHZ/n, or
(901MHZ−0MHZ)/n=901MHZ/n.
For the former case of 900 MHZ/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 2006 should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. For the latter case of 901 MHZ/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 2006 should be substantially equal to 1.802 GHz, 901 MHZ, 450.5 MHZ, 300.333 MHZ, 225.25 MHZ, etc. The frequency of the down-converted AM signal is substantially equal to the difference between the lower frequency F1 and the upper frequency F2 (i.e., 1 MHZ).
Exemplary time domain and frequency domain drawings, illustrating down-conversion of FM signals to non-FM signals, and exemplary methods and systems thereof, are disclosed in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.
In an embodiment, the pulses of the control signal 2006 have negligible apertures that tend towards zero. This makes the UFT module 2002 a high input impedance device. This configuration is useful for situations where minimal disturbance of the input signal may be desired.
In another embodiment, the pulses of the control signal 2006 have non-negligible apertures that tend away from zero. This makes the UFT module 2002 a lower input impedance device. This allows the lower input impedance of the UFT module 2002 to be substantially matched with a source impedance of the input signal 2004. This also improves the energy transfer from the input signal 2004 to the down-converted output signal 2012, and hence the efficiency and signal to noise (s/n) ratio of UFT module 2002.
Exemplary systems and methods for generating and optimizing the control signal 2006, and for otherwise improving energy transfer and s/n ratio, are disclosed in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals,” Ser. No. 09/176,022.
When the pulses of the control signal 2006 have non-negligible apertures, the aliasing module 2000 is referred to interchangeably herein as an energy transfer module or a gated transfer module, and the control signal 2006 is referred to as an energy transfer signal. Exemplary systems and methods for generating and optimizing the control signal 2006 and for otherwise improving energy transfer and/or signal to noise ratio in an energy transfer module are described below.
3.1. Optional Energy Transfer Signal Module
In an embodiment, the optional energy transfer signal module 4702 includes an aperture generator, an example of which is illustrated in
The width or aperture of the pulses 4626 is determined by delay through the branch 4622 of the aperture generator 4620. Generally, as the desired pulse width increases, the difficulty in meeting the requirements of the aperture generator 4620 decrease. In other words, to generate non-negligible aperture pulses for a given EM input frequency, the components utilized in the example aperture generator 4620 do not require as fast reaction times as those that are required in an under-sampling system operating with the same EM input frequency.
The example logic and implementation shown in the aperture generator 4620 are provided for illustrative purposes only, and are not limiting. The actual logic employed can take many forms. The example aperture generator 4620 includes an optional inverter 4628, which is shown for polarity consistency with other examples provided herein.
An example implementation of the aperture generator 4620 is illustrated in
In an embodiment, the input signal 4624 is generated externally of the energy transfer signal module 4702, as illustrated in
The type of down-conversion performed by the energy transfer system 4701 depends upon the aliasing rate of the energy transfer signal 4506, which is determined by the frequency of the pulses 4626. The frequency of the pulses 4626 is determined by the frequency of the input signal 4624. For example, when the frequency of the input signal 4624 is substantially equal to a harmonic or a sub-harmonic of the EM signal 4504, the EM signal 4504 is directly down-converted to baseband (e.g. when the EM signal is an AM signal or a PM signal), or converted from FM to a non-FM signal. When the frequency of the input signal 4624 is substantially equal to a harmonic or a sub-harmonic of a difference frequency, the EM signal 4504 is down-converted to an intermediate signal.
The optional energy transfer signal module 4702 can be implemented in hardware, software, firmware, or any combination thereof.
3.2 Smoothing the Down-Converted Signal
Referring back to
3.3. Impedance Matching
The energy transfer module 2000 has input and output impedances generally defined by (1) the duty cycle of the switch module (i.e., UFT 2002), and (2) the impedance of the storage module (e.g., capacitor 2010), at the frequencies of interest (e.g. at the EM input, and intermediate/baseband frequencies).
Starting with an aperture width of approximately ½ the period of the EM signal being down-converted as a preferred embodiment, this aperture width (e.g. the “closed time”) can be decreased. As the aperture width is decreased, the characteristic impedance at the input and the output of the energy transfer module increases. Alternatively, as the aperture width increases from ½ the period of the EM signal being down-converted, the impedance of the energy transfer module decreases.
One of the steps in determining the characteristic input impedance of the energy transfer module could be to measure its value. In an embodiment, the energy transfer module's characteristic input impedance is 300 ohms. An impedance matching circuit can be utilized to efficiently couple an input EM signal that has a source impedance of, for example, 50 ohms, with the energy transfer module's impedance of, for example, 300 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary impedance directly or the use of an impedance match circuit as described below.
Referring to
The output characteristic impedance can be impedance matched to take into consideration the desired output frequencies. One of the steps in determining the characteristic output impedance of the energy transfer module could be to measure its value. Balancing the very low impedance of the storage module at the input EM frequency, the storage module should have an impedance at the desired output frequencies that is preferably greater than or equal to the load that is intended to be driven (for example, in an embodiment, storage module impedance at a desired 1MHz output frequency is 2K ohm and the desired load to be driven is 50 ohms). An additional benefit of impedance matching is that filtering of unwanted signals can also be accomplished with the same components.
In an embodiment, the energy transfer module's characteristic output impedance is 2K ohms. An impedance matching circuit can be utilized to efficiently couple the down-converted signal with an output impedance of, for example, 2K ohms, to a load of, for example, 50 ohms. Matching these impedances can be accomplished in various manners, including providing the necessary load impedance directly or the use of an impedance match circuit as described below.
When matching from a high impedance to a low impedance, a capacitor 5014 and an inductor 5016 can be configured as shown in
The configuration of the input impedance match module 4806 and the output impedance match module 4808 are considered to be initial starting points for impedance matching, in accordance with the present invention. In some situations, the initial designs may be suitable without further optimization. In other situations, the initial designs can be optimized in accordance with other various design criteria and considerations.
As other optional optimizing structures and/or components are utilized, their affect on the characteristic impedance of the energy transfer module should be taken into account in the match along with their own original criteria.
3.4 Tanks and Resonant Structures
Resonant tank and other resonant structures can be used to further optimize the energy transfer characteristics of the invention. For example, resonant structures, resonant about the input frequency, can be used to store energy from the input signal when the switch is open, a period during which one may conclude that the architecture would otherwise be limited in its maximum possible efficiency. Resonant tank and other resonant structures can include, but are not limited to, surface acoustic wave (SAW) filters, dielectric resonators, diplexers, capacitors, inductors, etc.
An example embodiment is shown in
As is apparent to one skilled in the relevant art(s), parallel tank circuits provide:
In the illustrated example of
An energy transfer signal 6042 controls a switch 6014. When the energy transfer signal 6042 controls the switch 6014 to open and close, high frequency signal components are not allowed to pass through tank1 or tank2. However, the lower signal components (50Mhz in this embodiment) generated by the system are allowed to pass through tank1 and tank2 with little attenuation. The effect of tank1 and tank2 is to further separate the input and output signals from the same node thereby producing a more stable input and output impedance. Capacitors 6018 and 6040 act to store the 50 MHz output signal energy between energy transfer pulses.
Further energy transfer optimization is provided by placing an inductor 6010 in series with a storage capacitor 6012 as shown. In the illustrated example, the series resonant frequency of this circuit arrangement is approximately 1 GHz. This circuit increases the energy transfer characteristic of the system. The ratio of the impedance of inductor 6010 and the impedance of the storage capacitor 6012 is preferably kept relatively small so that the majority of the energy available will be transferred to storage capacitor 6012 during operation. Exemplary output signals A and B are illustrated in
In
The example tank and resonant structures described above are for illustrative purposes and are not limiting. Alternate configurations can be utilized. The various resonant tanks and structures discussed can be combined or utilized independently as is now apparent.
3.5 Charge and Power Transfer Concepts
Concepts of charge transfer are now described with reference to
In
Where the voltage V is represented by Equation 11, Equation 10 can be rewritten as Equation 12. The change in charge Δq over time t is illustrated as in Equation 13 as Δq(t), which can be rewritten as Equation 14. Using the sum-to-product trigonometric identity of Equation 15, Equation 14 can be rewritten as Equation 16, which can be rewritten as equation 17.
Note that the sin term in Equation 11 is a function of the aperture T only. Thus, Δq(t) is at a maximum when T is equal to an odd multiple of π(i.e., π, 3π, 5π, . . . ). Therefore, the capacitor 7106 experiences the greatest change in charge when the aperture T has a value of it or a time interval representative of 180 degrees of the input sinusoid. Conversely, when T is equal to 2π, 4π, 6π, . . . , minimal charge is transferred.
Equations 18, 19, and 20 solve for q(t) by integrating Equation 10, allowing the charge on the capacitor 7106 with respect to time to be graphed on the same axis as the input sinusoid sin(t), as illustrated in the graph of
Power/charge relationships are illustrated in Equations 21-26 of
Concepts of insertion loss are illustrated in
3.6 Optimizing and Adjusting the Non-Negligible Aperture Width/Duration
3.6.1 Varying Input and Output Impedances
In an embodiment of the invention, the energy transfer signal (i.e., control signal 2006 in
In
An example method of altering the energy transfer signal 5106 of
It can be shown that by varying the delay of the signal propagated by the inverter 4908, the width of the pulses in the doubler output signal 4904 can be varied. Increasing the delay of the signal propagated by inverter 4908, increases the width of the pulses. The signal propagated by inverter 4908 can be delayed by introducing a R/C low pass network in the output of inverter 4908. Other means of altering the delay of the signal propagated by inverter 4908 will be well known to those skilled in the art.
3.6.2 Real Time Aperture Control
In an embodiment, the aperture width/duration is adjusted in real time. For example, referring to the timing diagrams in
In an alternative implementation, the inverted clock signal 6422 is delayed relative to the original clock signal 6414, and then ANDed with the original clock signal 6414. Alternatively, the original clock signal 6414 is delayed then inverted, and the result ANDed with the original clock signal 6414.
Operation of the real time aperture control circuit is described with reference to the timing diagrams of
The delayed clock signal 6424 is optionally amplified by the optional amplifier 6428, before being presented to the AND gate 6408. Amplification is desired, for example, where the RC constant of the RC circuit 6404 attenuates the signal below the threshold of the AND gate 6408.
The AND gate 6408 ANDs the delayed clock signal 6424, the inverted clock signal 6422, and the optional Enable signal 6410, to generate the energy transfer signal 6416. The apertures 6420 are adjusted in real time by varying the voltage to the voltage variable capacitor 6412.
In an embodiment, the apertures 6420 are controlled to optimize power transfer. For example, in an embodiment, the apertures 6420 are controlled to maximize power transfer. Alternatively, the apertures 6420 are controlled for variable gain control (e.g. automatic gain control—AGC). In this embodiment, power transfer is reduced by reducing the apertures 6420.
As can now be readily seen from this disclosure, many of the aperture circuits presented, and others, can be modified as in circuits illustrated in
3.7 Adding a Bypass Network
In an embodiment of the invention, a bypass network is added to improve the efficiency of the energy transfer module. Such a bypass network can be viewed as a means of synthetic aperture widening. Components for a bypass network are selected so that the bypass network appears substantially lower impedance to transients of the switch module (i.e., frequencies greater than the received EM signal) and appears as a moderate to high impedance to the input EM signal (e.g., greater that 100 Ohms at the RF frequency).
The time that the input signal is now connected to the opposite side of the switch module is lengthened due to the shaping caused by this network, which in simple realizations may be a capacitor or series resonant inductor-capacitor. A network that is series resonant above the input frequency would be a typical implementation. This shaping improves the conversion efficiency of an input signal that would otherwise, if one considered the aperture of the energy transfer signal only, be relatively low in frequency to be optimal.
For example, referring to
The following discussion will demonstrate the effects of a minimized aperture and the benefit provided by a bypassing network. Beginning with an initial circuit having a 550 ps aperture in
3.8 Modifying the Energy Transfer Signal Utilizing Feedback
Generally, the amplitude of the down-converted signal 4708B varies as a function of the frequency and phase differences between the EM signal 4504 and the energy transfer signal 4506. In an embodiment, the down-converted signal 4708B is used as the feedback 4706 to control the frequency and phase relationship between the EM signal 4504 and the energy transfer signal 4506. This can be accomplished using the example logic in
In the example of
The DAC 5206 controls an input to a voltage controlled oscillator, VCO 5208. VCO 5208 controls a frequency input of a pulse generator 5210, which, in an embodiment, is substantially similar to the pulse generator shown in
In an embodiment, the state machine 5204 operates in accordance with a state machine flowchart 5219 in
The amplitude of the down-converted signal 4708B can be made to vary with the amplitude of the energy transfer signal 4506. In an embodiment where the switch module 6502 is a FET as shown in
3.9 Other Implementations
The implementations described above are provided for purposes of illustration. These implementations are not intended to limit the invention. Alternate implementations, differing slightly or substantially from those described herein, will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternate implementations fall within the scope and spirit of the present invention.
3.10 Example Energy Transfer Down-Converters
Example implementations are described below for illustrative purposes. The invention is not limited to these examples.
4. Frequency Up-Conversion
The present invention is directed to systems and methods of frequency up-conversion, and applications of same.
An example frequency up-conversion system 300 is illustrated in
An input signal 302 (designated as “Control Signal” in
The output of switch module 304 is a harmonically rich signal 306, shown for example in
Harmonically rich signal 608 is comprised of a plurality of sinusoidal waves whose frequencies are integer multiples of the fundamental frequency of the waveform of the harmonically rich signal 608. These sinusoidal waves are referred to as the harmonics of the underlying waveform, and the fundamental frequency is referred to as the first harmonic.
The relative amplitudes of the harmonics are generally a function of the relative widths of the pulses of harmonically rich signal 306 and the period of the fundamental frequency, and can be determined by doing a Fourier analysis of harmonically rich signal 306. According to an embodiment of the invention, the input signal 606 may be shaped to ensure that the amplitude of the desired harmonic is sufficient for its intended use (e.g., transmission).
A filter 308 filters out any undesired frequencies (harmonics), and outputs an electromagnetic (EM) signal at the desired harmonic frequency or frequencies as an output signal 310, shown for example as a filtered output signal 614 in
Also in
The invention is not limited to the UFU embodiment shown in
For example, in an alternate embodiment shown in
The purpose of the pulse shaping module 502 is to define the pulse width of the input signal 302. Recall that the input signal 302 controls the opening and closing of the switch 406 in switch module 304. During such operation, the pulse width of the input signal 302 establishes the pulse width of the harmonically rich signal 306. As stated above, the relative amplitudes of the harmonics of the harmonically rich signal 306 are a function of at least the pulse width of the harmonically rich signal 306. As such, the pulse width of the input signal 302 contributes to setting the relative amplitudes of the harmonics of harmonically rich signal 306.
Further details of up-conversion as described in this section are presented in pending U.S. application “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998, incorporated herein by reference in its entirety.
5. Enhanced Signal Reception
The present invention is directed to systems and methods of enhanced signal reception (ESR), and applications of same.
Referring to
Modulating baseband signal 2102 is preferably any information signal desired for transmission and/or reception. An example modulating baseband signal 2202 is illustrated in
Each transmitted redundant spectrum 2106a-n contains the necessary information to substantially reconstruct the modulating baseband signal 2102. In other words, each redundant spectrum 2106a-n contains the necessary amplitude, phase, and frequency information to reconstruct the modulating baseband signal 2102.
Transmitted redundant spectrums 2206b-d are centered at f1, with a frequency spacing f2 between adjacent spectrums. Frequencies f1 and f2 are dynamically adjustable in real-time as will be shown below.
Received redundant spectrums 2110a-n are substantially similar to transmitted redundant spectrums 2106a-n, except for the changes introduced by the communications medium 2108. Such changes can include but are not limited to signal attenuation, and signal interference.
As stated above, demodulated baseband signal 2114 is extracted from one or more of received redundant spectrums 2210b-d.
An advantage of the present invention should now be apparent. The recovery of modulating baseband signal 2202 can be accomplished by receiver 2112 in spite of the fact that high strength jamming signal(s) (e.g. jamming signal spectrum 2211) exist on the communications medium. The intended baseband signal can be recovered because multiple redundant spectrums are transmitted, where each redundant spectrum carries the necessary information to reconstruct the baseband signal. At the destination, the redundant spectrums are isolated from each other so that the baseband signal can be recovered even if one or more of the redundant spectrums are corrupted by a jamming signal.
Transmitter 2104 will now be explored in greater detail.
Transmitter 2301 operates as follows. First oscillator 2302 and second oscillator 2309 generate a first oscillating signal 2305 and second oscillating signal 2312, respectively. First stage modulator 2306 modulates first oscillating signal 2305 with modulating baseband signal 2202, resulting in modulated signal 2308. First stage modulator 2306 may implement any type of modulation including but not limited to: amplitude modulation, frequency modulation, phase modulation, combinations thereof, or any other type of modulation. Second stage modulator 2310 modulates modulated signal 2308 with second oscillating signal 2312, resulting in multiple redundant spectrums 2206a-n shown in
Redundant spectrums 2206a-n are substantially centered around f1, which is the characteristic frequency of first oscillating signal 2305. Also, each redundant spectrum 2206a-n (except for 2206c) is offset from f1 by approximately a multiple of f2 (Hz), where f2 is the frequency of the second oscillating signal 2312. Thus, each redundant spectrum 2206a-n is offset from an adjacent redundant spectrum by f2 (Hz). This allows the spacing between adjacent redundant spectrums to be adjusted (or tuned) by changing f2 that is associated with second oscillator 2309. Adjusting the spacing between adjacent redundant spectrums allows for dynamic real-time tuning of the bandwidth occupied by redundant spectrums 2206a-n.
In one embodiment, the number of redundant spectrums 2206a-n generated by transmitter 2301 is arbitrary and may be unlimited as indicated by the “a-n” designation for redundant spectrums 2206a-n. However, a typical communications medium will have a physical and/or administrative limitations (i.e. FCC regulations) that restrict the number of redundant spectrums that can be practically transmitted over the communications medium. Also, there may be other reasons to limit the number of redundant spectrums transmitted. Therefore, preferably, the transmitter 2301 will include an optional spectrum processing module 2304 to process the redundant spectrums 2206a-n prior to transmission over communications medium 2108.
In one embodiment, spectrum processing module 2304 includes a filter with a passband 2207 (
As shown in
Redundant spectrums 2208a-n are centered on unmodulated spectrum 2209 (at f1 Hz), and adjacent spectrums are separated by f2 Hz. The number of redundant spectrums 2208a-n generated by generator 2311 is arbitrary and unlimited, similar to spectrums 2206a-n discussed above. Therefore, optional spectrum processing module 2304 may also include a filter with passband 2325 to select, for example, spectrums 2208c,d for transmission over communications medium 2108. In addition, optional spectrum processing module 2304 may also include a filter (such as a bands top filter) to attenuate unmodulated spectrum 2209. Alternatively, unmodulated spectrum 2209 may be attenuated by using phasing techniques during redundant spectrum generation. Finally, (optional) medium interface module 2320 transmits redundant spectrums 2208c,d over communications medium 2108.
Receiver 2112 will now be explored in greater detail to illustrate recovery of a demodulated baseband signal from received redundant spectrums.
In one embodiment, optional medium interface module 2402 receives redundant spectrums 2210b-d (
Referring to
The error detection schemes implemented by the error detection modules include but are not limited to: cyclic redundancy check (CAC) and parity check for digital signals, and various error detections schemes for analog signal.
Further details of enhanced signal reception as described in this section are presented in pending U.S. application “Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed Oct. 21, 1998, incorporated herein by reference in its entirety.
6. Unified Down-Conversion and Filtering
The present invention is directed to systems and methods of unified down-conversion and filtering (UDF), and applications of same.
In particular, the present invention includes a unified down-converting and filtering (UDF) module that performs frequency selectivity and frequency translation in a unified (i.e., integrated) manner. By operating in this manner, the invention achieves high frequency selectivity prior to frequency translation (the invention is not limited to this embodiment). The invention achieves high frequency selectivity at substantially any frequency, including but not limited to RF (radio frequency) and greater frequencies. It should be understood that the invention is not limited to this example of RF and greater frequencies. The invention is intended, adapted, and capable of working with lower than radio frequencies.
The effect achieved by the UDF module 1702 is to perform the frequency selectivity operation prior to the performance of the frequency translation operation. Thus, the UDF module 1702 effectively performs input filtering.
According to embodiments of the present invention, such input filtering involves a relatively narrow bandwidth. For example, such input filtering may represent channel select filtering, where the filter bandwidth may be, for example, 50 KHz to 150 KHz. It should be understood, however, that the invention is not limited to these frequencies. The invention is intended, adapted, and capable of achieving filter bandwidths of less than and greater than these values.
In embodiments of the invention, input signals 1704 received by the UDF module 1702 are at radio frequencies. The UDF module 1702 effectively operates to input filter these RF input signals 1704. Specifically, in these embodiments, the UDF module 1702 effectively performs input, channel select filtering of the RF input signal 1704. Accordingly, the invention achieves high selectivity at high frequencies.
The UDF module 1702 effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof.
Conceptually, the UDF module 1702 includes a frequency translator 1708. The frequency translator 1708 conceptually represents that portion of the UDF module 1702 that performs frequency translation (down conversion).
The UDF module 1702 also conceptually includes an apparent input filter 1706 (also sometimes called an input filtering emulator). Conceptually, the apparent input filter 1706 represents that portion of the UDF module 1702 that performs input filtering.
In practice, the input filtering operation performed by the UDF module 1702 is integrated with the frequency translation operation. The input filtering operation can be viewed as being performed concurrently with the frequency translation operation. This is a reason why the input filter 1706 is herein referred to as an “apparent” input filter 1706.
The UDF module 1702 of the present invention includes a number of advantages. For example, high selectivity at high frequencies is realizable using the UDF module 1702. This feature of the invention is evident by the high Q factors that are attainable. For example, and without limitation, the UDF module 1702 can be designed with a filter center frequency fc on the order of 900 MHZ, and a filter bandwidth on the order of 50 KHz. This represents a Q of 18,000 (Q is equal to the center frequency divided by the bandwidth).
It should be understood that the invention is not limited to filters with high Q factors. The filters contemplated by the present invention may have lesser or greater Qs, depending on the application, design, and/or implementation. Also, the scope of the invention includes filters where Q factor as discussed herein is not applicable.
The invention exhibits additional advantages. For example, the filtering center frequency fC of the UDF module 1702 can be electrically adjusted, either statically or dynamically.
Also, the UDF module 1702 can be designed to amplify input signals.
Further, the UDF module 1702 can be implemented without large resistors, capacitors, or inductors. Also, the UDF module 1702 does not require that tight tolerances be maintained on the values of its individual components, i.e., its resistors, capacitors, inductors, etc. As a result, the architecture of the UDF module 1702 is friendly to integrated circuit design techniques and processes.
The features and advantages exhibited by the UDF module 1702 are achieved at least in part by adopting a new technological paradigm with respect to frequency selectivity and translation. Specifically, according to the present invention, the UDF module 1702 performs the frequency selectivity operation and the frequency translation operation as a single, unified (integrated) operation. According to the invention, operations relating to frequency translation also contribute to the performance of frequency selectivity, and vice versa.
According to embodiments of the present invention, the UDF module generates an output signal from an input signal using samples/instances of the input signal and samples/instances of the output signal.
More particularly, first, the input signal is under-sampled. This input sample includes information (such as amplitude, phase, etc.) representative of the input signal existing at the time the sample was taken.
As described further below, the effect of repetitively performing this step is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency, such as an intermediate frequency (IF) or baseband.
Next, the input sample is held (that is, delayed).
Then, one or more delayed input samples (some of which may have been scaled) are combined with one or more delayed instances of the output signal (some of which may have been scaled) to generate a current instance of the output signal.
Thus, according to a preferred embodiment of the invention, the output signal is generated from prior samples/instances of the input signal and/or the output signal. (It is noted that, in some embodiments of the invention, current samples/instances of the input signal and/or the output signal may be used to generate current instances of the output signal). By operating in this manner, the UDF module preferably performs input filtering and frequency down-conversion in a unified manner.
In the example provided by
VO=α1z−1VI−β1z−1VO−β0z−2VO EQ. 1
It should be noted, however, that the invention is not limited to band-pass filtering. Instead, the invention effectively performs various types of filtering, including but not limited to bandpass filtering, low pass filtering, high pass filtering, notch filtering, all pass filtering, band stop filtering, etc., and combinations thereof. As will be appreciated, there are many representations of any given filter type. The invention is applicable to these filter representations. Thus, EQ. 1 is referred to herein for illustrative purposes only, and is not limiting.
The UDF module 1922 (shown in
As further described below, in the example provided by
Preferably, each of these switches closes on a rising edge of φ1 or φ2, and opens on the next corresponding falling edge of φ1 or φ2. However, the invention is not limited to this example. As will be apparent to persons skilled in the relevant art(s), other clock conventions can be used to control the switches.
In the example provided by
The example UDF module 1922 has a filter center frequency of 900.2 MHZ and a filter bandwidth of 570 KHz. The pass band of the UDF module 1922 is on the order of 899.915 MHZ to 900.485 MHZ. The Q factor of the UDF module 1922 is approximately 1879 (i.e., 900.2 MHZ divided by 570 KHz).
The operation of the UDF module 1922 shall now be described with reference to a Table 1802 (
At the rising edge of φ1 at time t−1, a switch 1950 (shown in
The manner in which the down-convert and delay module 1924 performs frequency down-conversion is further described elsewhere in this application, and is additionally described in pending U.S. application “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998, which is herein incorporated by reference in its entirety.
Also at the rising edge of φ1 at time t−1, a switch 1958 (shown in
Also at the rising edge of φ1 at time t−1, a switch 1966 (shown in
At the rising edge of φ2 at time t−1, a switch 1954 (shown in
The UDF module 1922 may optionally include a unity gain module 1990A (shown in
Also at the rising edge of φ2 at time t−1, a switch 1962 (shown in
Also at the rising edge of φ2 at time t−1, a switch 1970 (shown in
At time t, at the rising edge of φ1, the switch 1950 in the down-convert and delay module 1924 closes. This allows the capacitor 1952 to charge to VIt, such that node 1902 is at VIt. This is indicated in cell 1816 of Table 1802.
Also at the rising edge of φ1 at time t, the switch 1958 in the first delay module 1928 closes, thereby allowing the capacitor 1960 to charge to VOt. Accordingly, node 1906 is at VOt. This is indicated in cell 1820 in Table 1802.
Further at the rising edge of φ1 at time t, the switch 1966 in the second delay module 1930 closes, allowing a capacitor 1968 to charge to the level of the capacitor 1964. Therefore, the capacitor 1968 charges to VOt−1, such that node 1910 (shown in
At the rising edge of φ2 at time t, the switch 1954 in the down-convert and delay module 1924 closes, allowing the capacitor 1956 to charge to the level of the capacitor 1952. Accordingly, the capacitor 1956 charges to VIt, such that node 1904 is at VIt. This is indicated by cell 1828 in Table 1802.
Also at the rising edge of φ2 at time t, the switch 1962 in the first delay module 1928 closes, allowing the capacitor 1964 to charge to the level in the capacitor 1960. Therefore, the capacitor 1964 charges to VOt, such that node 1908 is at VOt. This is indicated by cell 1832 in Table 1802.
Further at the rising edge of φ2 at time t, the switch 1970 in the second delay module 1930 closes, allowing the capacitor 1972 in the second delay module 1930 to charge to the level of the capacitor 1968 in the second delay module 1930. Therefore, the capacitor 1972 charges to VOt−1, such that node 1912 (shown in
At time t+1, at the rising edge of φ1, the switch 1950 in the down-convert and delay module 1924 closes, allowing the capacitor 1952 to charge to VIt+1. Therefore, node 1902 is at VIt+1, as indicated by cell 1838 of Table 1802.
Also at the rising edge of φ1 at time t+1, the switch 1958 in the first delay module 1928 closes, allowing the capacitor 1960 to charge to VOt+1. Accordingly, node 1906 is at VOt+1, as indicated by cell 1842 in Table 1802.
Further at the rising edge of φ1 at time t+1, the switch 1966 in the second delay module 1930 closes, allowing the capacitor 1968 to charge to the level of the capacitor 1964. Accordingly, the capacitor 1968 charges to VOt, as indicated by cell 1846 of Table 1802.
In the example provided by
At time t+1, the values at the inputs of the summer 1926 (shown in
At the rising edge of φ1 at time t+1, a switch 1991 (shown in
Further details of unified down-conversion and filtering as described in this section are presented in pending U.S. application “Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998, incorporated herein by reference in its entirety.
7. Example Application Embodiments of the Invention
As noted above, the UFT module of the present invention is a very powerful and flexible device. Its flexibility is illustrated, in part, by the wide range of applications in which it can be used. Its power is illustrated, in part, by the usefulness and performance of such applications.
Example applications of the UFT module were described above. In particular, frequency down-conversion, frequency up-conversion, enhanced signal reception, and unified down-conversion and filtering applications of the UFT module were summarized above, and are further described below. These applications of the UFT module are discussed herein for illustrative purposes. The invention is not limited to these example applications. Additional applications of the UFT module will be apparent to persons skilled in the relevant art(s), based on the teachings contained herein.
For example, the present invention can be used in applications that involve frequency down-conversion. This is shown in
The present invention can be used in applications that involve frequency up-conversion. This is shown in
The present invention can be used in environments having one or more transmitters 902 and one or more receivers 906, as illustrated in
The invention can be used to implement a transceiver. An example transceiver 1002 is illustrated in
Another transceiver embodiment according to the invention is shown in
As described elsewhere in this application, the invention is directed to methods and systems for enhanced signal reception (ESR). Various ESR embodiments include an ESR module (transmit) in a transmitter 1202, and an ESR module (receive) in a receiver 1210. An example ESR embodiment configured in this manner is illustrated in
The ESR module (transmit) 1204 includes a frequency up-conversion module 1206. Some embodiments of this frequency up-conversion module 1206 may be implemented using a UFT module, such as that shown in
The ESR module (receive) 1212 includes a frequency down-conversion module 1214. Some embodiments of this frequency down-conversion module 1214 may be implemented using a UFT module, such as that shown in
As described elsewhere in this application, the invention is directed to methods and systems for unified down-conversion and filtering (UDF). An example unified down-conversion and filtering module 1302 is illustrated in
Unified down-conversion and filtering according to the invention is useful in applications involving filtering and/or frequency down-conversion. This is depicted, for example, in
For example, receivers, which typically perform filtering, down-conversion, and filtering operations, can be implemented using one or more unified down-conversion and filtering modules. This is illustrated, for example, in
The methods and systems of unified down-conversion and filtering of the invention have many other applications. For example, as discussed herein, the enhanced signal reception (ESR) module (receive) operates to down-convert a signal containing a plurality of spectrums. The ESR module (receive) also operates to isolate the spectrums in the down-converted signal, where such isolation is implemented via filtering in some embodiments. According to embodiments of the invention, the ESR module (receive) is implemented using one or more unified down-conversion and filtering (UDF) modules. This is illustrated, for example, in
The invention is not limited to the applications of the UFT module described above. For example, and without limitation, subsets of the applications (methods and/or structures) described herein (and others that would be apparent to persons skilled in the relevant art(s) based on the herein teachings) can be associated to form useful combinations.
For example, transmitters and receivers are two applications of the UFT module.
Also, ESR (enhanced signal reception) and unified down-conversion and filtering are two other applications of the UFT module.
The invention is not limited to the example applications of the UFT module discussed herein. Also, the invention is not limited to the example combinations of applications of the UFT module discussed herein. These examples were provided for illustrative purposes only, and are not limiting. Other applications and combinations of such applications will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such applications and combinations include, for example and without limitation, applications/combinations comprising and/or involving one or more of: (1) frequency translation; (2) frequency down-conversion; (3) frequency up-conversion; (4) receiving; (5) transmitting; (6) filtering; and/or (7) signal transmission and reception in environments containing potentially jamming signals.
Additional examples are set forth below describing applications of the UFT module with circuits that reduce or eliminate unwanted DC offset and re-radiation, and improve dynamic range.
7.0 DC Offset, Re-Radiation, and Dynamic Range Considerations and Corrections
Various embodiments related to the method(s) and structure(s) described herein are presented in this section (and its subsections). Problems related to DC offset, re-radiation, and dynamic range are described below. Applications of the UFT module are provided in relation to circuits used to reduce or eliminate problems of DC offset and re-radiation, and to improve dynamic range.
These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.1 Overview of DC Offset and Re-Radiation
Receivers, and other electronic circuits, may suffer from problems of DC offset and re-radiation. Generally, “DC offset” refers to a DC voltage level that is added to a signal of interest by related circuitry. The related circuitry creates the DC offset voltage through a variety of mechanisms that are well known. Some of these mechanisms are discussed in further detail below. If a DC offset voltage value is significant, it can degrade the quality of the signal of interest. In a receiver, for example, the signal of interest may be a down-converted signal. Unless reduced or eliminated, the added DC offset voltage level may undesirably change the voltage value of the down-converted signal. As a result, the actual voltage value of the down-converted signal may be difficult to ascertain by down-stream processing.
Generally, “re-radiation” is an undesired phenomenon where a signal comprising one or more frequency components generated by receiving circuitry is transmitted by an antenna. For example, the frequency components may be generated by a local oscillator of the receiving circuitry. When transmitted, these frequency components may undesirably interfere with nearby receivers, or may be received back by the same antenna that transmitted them. When the frequency components are received back by the same antenna that transmitted them, this may be referred to “re-radiation recapture”. The phenomenon of re-radiation recapture may further impair signals that are down-converted, and/or may cause undesirable DC offset voltages that may impair the down-converted signals. For instance, the re-radiated and recaptured signal may appear to the receiver as unwanted noise, within or without the frequency band(s) of interest, or may combine with local signals to create an undesired DC offset voltage. The phenomenon of creating a DC offset voltage by re-radiation recapture is described further below. Solutions provided herein for eliminating unwanted DC offset voltages apply to eliminating DC offset voltages produced from re-radiation recapture.
Furthermore, signals in a receiver circuit may travel or radiate to other receiver circuit sections, causing problems similar to those of re-radiation recapture described above, including problems of noise and DC offset voltages. For instance, local oscillator signals may undesirably transmit through the circuit substrate, through the air, or through other paths, to other receiver circuit sections, causing unwanted noise problems and problems with unwanted DC offset voltages being generated. Circuits provided herein for solving problems with DC offsets, re-radiation, and re-radiation recapture also apply to solving problems of noise and unwanted DC offset voltages caused by this phenomenon.
The concepts of DC offset and re-radiation are further described in the following sub-sections. Furthermore, example methods and systems are provided in subsequent sections below for reducing or eliminating unwanted DC offset and re-radiation. Such methods and systems can be used alone, or in combination with each other, to address offset issues.
7.1.1 Introduction
Embodiments of the UFT module may be used in many communications applications. For some of these applications, the signal space may include waveforms with near DC content. Such waveforms exist, for example, in signals transmitted at radio frequencies. Hence, it may be advantageous to limit the amount of artificial DC insertion or DC offsets contributed by the UFT module or its complimentary demodulation architecture.
This section presents an overview of DC offset contributions of the UFT module, and related circuitry, relevant for zero IF implementation. In addition, embodiments of the present invention are presented for reducing the adverse impacts of the DC offsets.
7.1.2 DC Offset Model Overview
There are at least three significant categories of offsets.
1. Clock Excitation or Charge Injected
2. Re-radiation Offsets
3. Intermodulation Distortion
Each category possesses its own mechanisms.
The following definitions in Table 1 set the backdrop for analysis and understanding of the offset phenomena from a high level model. At least some of the phenomena relevant to the discussion in terms of device physics may be lumped into one or more of the following model parameters.
R(t)=[r(t)+k1k2CA(t′A)+k2kBCB(t′B))+kLNA+kACA(t′A)+kBCB(t′B)C(t)+<|{tilde over (C)}(t)|>kcλ Eq. 29
(*The charge injection path associated with kff has been ignored in Eq. 29. This component will be addressed separately in a subsequent section.)
There may be additional leakage terms, which are not illustrated in the model.
7.1.3 Clock Modulation Via PN Code
A system and method for addressing DC offset, according to an embodiment of the present invention, involves modifying the LO (local oscillator) in such a manner that the offsets are randomized and spectrally spread. After some amount of amplification the randomized signal may be de-spread coherently. At least some of the offset, particularly that offset which is due to LO re-radiation, may be removed.
Although only a single down-conversion channel is illustrated in
R′(t)=kBBR(t−tBB)(CPN(t′)) Eq. 30
Which may be expanded to:
R′(t)kBB[(r(t−tBB)C(t′)+(t−tBB))kLNA+X(t−tBB)]CPN(t)+(<|{tilde over (C)}(t−tBB)|>kcλkBB)CPN(t′) Eq. 31
where:(t)=(k1kAC(t′1A)+k2kBCB(t′2B))C(t)X(t)=(kAC(t′A)+kBCB(t′B))C(t)t′XΔ(t−tX)C(t){tilde over (−)}CA(t′) Eq. 32
It will be apparent to persons skilled in the relevant art(s) from the teaching herein that examination of these equations, combined with the knowledge that C(t) can be a pseudo random sequence, will reveal interesting cross correlations for the math provided above.
For the moment, delays on the order of sub-carrier cycle times and carrier cycle times may be ignored, thereby considering many of the delay terms to be zero. While this may not actually be the case, this does provide a substantially worst case bounding view of cross-correlation properties of the described signal in one dimension. The general result would apply to the I/Q complex signal representation. However, the first step for a single dimension is instructive and therefore provided. The cross-correlation RXX is calculated as follows:
RXX(t)Δ<kBBR(t)CPN(t)>≈<kBBR(t−tBB)CPN(t′)> Eq. 33
The result is:
RXX(t){tilde over (−)}<[kBBkLNAr(t)+k1AkLNAkBBC(t)CA(t)CPN(t′)+k2BkLNAkBBC(t)CB(t)CPN(t′)+kBBkACA(t′)C(t)+kBBkBCB(t)CPN(t′)+<|{tilde over (C)}(t)|>kcλ·kBBCPN(t′)[> Eq. 34
CPN(t), CA(t), r(t), and CB(t) average to zero over a long term, if CPN(t) is augmented. Even if r(t) does not average to zero, r(t) is not considered because it is the signal of interest. (NOTE: An “augmented” sequence refers to the process of chip stuffing as required to provide ideal code balance.)
It will be known to persons skilled in the relevant art(s) that C(t) and CB(t) are uncorrelated. It is also known that |{tilde over (C)}(t)| and CPN(t) are uncorrelated when CPN(t) is bipolar. If the cross-correlations indicated above are in fact indicative of the process, then RXX(t) would approximately reduce to:
RXX(t)≈→0 Eq. 35
RXX(t) represents the DC offset that exists due to LO re-radiation leaking into the front end of UFD module 7402 by some ancillary path, such that it is converted into band at the output of UFD module 7402 for the case where the leakage is synchronous in part or whole to the UFD module transform, plus charge injected offset. This synchronicity is actually rare for cases where k1A or kA is large. Typically those gains would be much less than 1.
What the above equation reveals is that little or no DC offset effects remain if CPN(t) and C(t) are balanced, bipolar sequences.
In this case, a spreading sequence, spreading rate, and sequence length are selected. This selection typically requires careful examination of the signaling scheme, data rate, etc. Also, the C1 path involving kff has not been accounted for in this analysis.
7.1.3.1 Interpretation of Rxx(t) and Required Leakage
It may be desirable that Rxx(t) be 3.16×10−6 volts peak in a 50Ω system for a number of applications. For a system design where the UFD module possesses an output impedance of 1KΩ, a signal level of 63.2 μV peak may be tolerated (−100 dBm).
In embodiments, clock port or control port signals may swing as much as 2V peak internal to the UFD module. If 2 volts must be reduced to 63.2 μV at the UFD module output, then:
Eq. 37 implies that the effective isolation from charge injected DC must be on the order of 90 dB (power) or greater at the UFD module in various embodiments.
In embodiments, it is unlikely that 90 dB of chip isolation would be achieved in a system-on-a-chip design. It may be more difficult to maintain isolations over temperature and production lots. In an embodiment, the suppression is such that the LO re-radiation in band @ 2450 MHZ for a n=5 system is −20 dBm.
A similar calculation for the aggregate LO re-radiation components reveals the requirement of approximately 100 dB suppression, effectively.
7.1.3.2 Charge Injected DC Offset
The charge injected DC offset phenomena may be modeled as some rectification of the clock or control port energy weighted by some gain constant, kcλ. The amount of DC offset introduced at the output of the UFD module may be given as:
CIUFD DCΔ(<|{tilde over (C)}(t)|>)kcλ Eq. 38
However, it may also be of value to construct a picture more closely associated with how this term arises. Consider a down-conversion circuit 7500 shown in
The amount of charge injected DC voltage variation at the output of UFD module 7502 is related to one or more of at least the following factors:
Because , and ZC, and are all complex impedances, there is always the chance that resonance's may occur for certain COLeff, such that VOCI could possess local maxima even as COLeff decreases. In the case where
,
, and
are dominated by real parts, the injection attenuation gains in dropping COLeff from 120 pf to 2 pf are enormous. These attenuation gains may be roughly 35 dB in power, and half that in voltage. Hence, DC offset due to charge injection may be significantly attenuated by process control. An example of process control may be related to moving from CMOS (Complementary Metal Oxide Semiconductor) to DMOS (Double Diffused Metal Oxide Semiconductor). There are processes available which may include both CMOS and DMOS on the same substrate, possibly providing important performance options, particularly in the domain of gate overlap capacitance control. The effective gate overlap capacitance COLeff is a chief offender, which results from process oxide capacitance in conjunction with overlap parasitics related to transistor geometries.
Another method of artificially decreasing COLeff is by changing to incorporate a series capacitor, which is much lower than COLeff. However, this must be done carefully to avoid negative substrate transients. A further useful circuit model allows
An embodiment of this circuit is shown in
where:
This model has some practical application because it can be used to predict compromises in the charge injection DC offset due to UFD module 7602 process parameters and the output capacitor C. For example, the model can predict, to a reasonable approximation, the results of a corresponding simulation. In the situations where and
may not be precisely known, a circuit designer may at least select approximate specifications for UFD module 7602 designs using the simple model, and add more accurate impedances as they become known. Furthermore, to the degree COX, W, L, VT, and Vcp can be manipulated, the more VOCI can be reduced.
7.1.3.3 Clock Waveform Impact on CI Induced Offsets
The previous section illustrated that the clock waveform can impact the efficiency of CI DC offset build up. This is an important concept because clock design is integral to the UFD module theory. The following formulation provides a Fourier series representation for a general clock pulse, and provides some insight into the frequency content of the excitation clock. The DC introduced by charge injection is a strong function of complex impedances around the UFD module. Signals which stimulate the UFD module may also play a role in the DC offset, depending on the clock signal's Fourier signature.
Clock pulse train VC(t) may be represented by a Fourier series as follows:
An ideal rectangular clock pulse is illustrated in
The calculated Fourier series for VC(t) is a well known result for sampling devices. As TA decreases, the Fourier spectrum extends ever greater in the frequency domain with significant harmonics.
A sequence of plots in
The circuitry surrounding UFD module 7802 may affect overall circuit performance. For example,
The previous plots related to cases with clock waveforms VC(t) possessing 10 ps rise and fall times.
It is interesting to note that there are two local minima for the DC offset performance with fast rise times representing one of those cases. This implies resonance in the complex impedances surrounding (and including) UFD module 7802. Different circuit topologies will behave differently and different component types would operate differently due to their own parasitic elements. In addition, stretching to a 3× or 5× aperture would produce different results.
7.1.3.4 Bench Example
Experiments were conducted with hardware designed to operate in the 2.4 GHz ISM (Industry, Scientific, and Medical) band. 5th harmonic mode was utilized for the clock, with the clock rate being varied between 482.4 MHZ and 492.4 MHZ. The UFD module configuration was an I/Q receiver with matching networks and DC coupling. The input to the I/Q assembly was terminated with 50Ω.
The charts shown in
7.1.3.5 Complementary Architecture
Up to this point the UFD module cores analyzed have been based on a non-complimentary structure. Complementary structures can be used with the important advantage of lower UFD module losses and greater IP2, IP3 performance. In addition, some charge injection cancellation should be possible. The results in
7.1.3.6 Spreading Code Results
Sections 7.1.3 and 7.1.3.1 outline the concept of using a local PN code to reduce the DC offset generated at a UFD module, or created due to LO re-radiation recapture. Maximal length codes, balanced codes, and other related code types may be used. Furthermore, the statistical properties of a code may be tailored in the time domain or frequency domain to accomplish desired DC reduction while minimizing the impact to the desired signal.
Experiments have been accomplished with UFD module circuit embodiments to illustrate the potential of these techniques.
Where:
As predicted by equations in section 7.1.3, the DC offset at a UFD module output may be canceled using a special sequence, its correlation properties, and its effective system processing gain.
The signal illustrated in
A goal is to choose an effective system processing gain PGsys, which is high enough to drive significant variance from the low pass result. PGsys is defined as follows:
The example run in the lab utilized a 10 kHz baseband signal bandwidth and a spreading rate of 5MHz. In addition, the code was modified as an R type. This technique may not provide all of the DC cancellation required but can be a powerful tool for many applications.
7.1.4 UFD Module DC Offsets from Non-Linearities
Because the UFD module is at least a conversion device, an intercept point will determine output waveform integrity to a large extent. Two tone 2nd order intercept and two tone 3rd order intercept points are important. In particular, the two tone second order intercept point, IP2IN, relates to DC offset. As the input begins to approach the UFD module rails, harmonic spectrums are generated in the signal path. Because the UFD module clock may excite harmonics, each harmonic spectrum may down-convert to DC, adding some DC offset. Because the phases of the down-conversion harmonics generally are complicated, the resulting DC offset may be non-systematic, even though the process is predictable by using complex math.
Another concept useful in considering the IP2IN mechanism comes from a different view on the frequency doubling phenomena. Frequency doubling occurs in a square law device. Hence, for the 2nd order term, the non-linearity from the UFD module output may be approximated by;
(Ã(t)cos(ω0t+φ(t)))2=½Ã(t)2(1+cos(2ω0t+2φ(t))) Eq. 46
Ã(t) could represent the complex envelope of modulation from information impressed on the carrier (as well as noise). Likewise, φ(t) could contain information modulated onto the carrier as well as phase noise. The above equation illustrates that the 2× frequency component can be formed from the non-linearity but that Ã(t)2 is also formed. The equation indicates that a DC component results from the squared envelope. This DC component is not desirable. Likewise, higher order intermodulation can contribute to the problem, particularly even order terms.
In general, the output voltage of a non-linear system can be expanded in terms of its input voltage by a power series of the form shown in
yn(t)=∫−∞∞ . . . ∫kn(u1,u2, . . . un)X(t−u1)X(t−u2) . . . X(t−undu1,du2, . . . dun) Eq. 47
where yn(t) is the system output and X(t) is the system input. This is the so called nth order impulse response for the system, found by an n-fold convolution kernel.
y1(t) is the desired linear impulse response of the system. y2(t) is the two-dimensional system convolution involving X(t). y3(t) is the three-dimensional convolution of X(t) and the impulse response h3 (u1,u2,u3), etc. This is known as the Volterra functional series representation of a system. For weak non-linearities, the first 3 terms of the series may provide enough information to characterize a system. This is the case for many communications systems.
Such nth order analysis in practice is often complex and tedious, yielding only a general feel for the expected result, unless circuit and network models are extraordinarily accurate. Nevertheless, in the approximation, the 2nd order term relating to the two tone 2nd order input intercept (IP2IN) is one useful metric for measuring down-conversion linearity. Essentially, the DC offset from (IP2IN is bounded at the upper end by the power of the 2nd order harmonic.
For instance, suppose that it is desired to suppress the power of the 2nd order term by 20 dB in a direct down-conversion device (no interference present). If the highest expected input RF signal of interest is −25 dBm, the system will require an input intercept (IP2IN) of −5 dBm. This establishes a signal-to-DC offset ratio of at least 20 dB due to the 2nd order non linearity.
Now consider the case where other unwanted signals are present at the input to the non-linearity along with the signal of interest. Suppose the RF signal is at a level of −101 dBm, while the interference tone is a level of −30 dBm. Furthermore, assume that the system noise floor is near enough to −101 under linear conditions such that we desire an additional 10 dB margin on any 2nd order non-linearity folded back in band, so that our benchmark at 101 dBm is not affected.
IP2IN=(−30+111)−30=51dBm Eq. 48
Therefore, IP2IN can become a significant specification when an interference or blocking tone is considered, and unfiltered due to a zero IF architecture.
This type of non-linear effect is dependent on input signal power to a great extent. Because the phenomenon is based on even-order intermods, differential design can cancel a significant portion of the difficulty, but imbalance may not remove it all. For instance, suppose that the input to the UFD module is at −15 dBm due to an LNA in front of the down-conversion. Suppose this is an interfering tone. Also, assume a 1KΩ baseband operating impedance and a 12 dB UFD module conversion loss. The suppression of the IP2IN at the UFD module output is then:
DC(IP2)≦−15−12−81 Eq. 49
If the desired suppression is 81 dB, the output offset into 1KΩ is less than 0.126 mV due to 2nd order non linearities. This may be accommodated with an op amp circuit, for example. If a differential architecture is assumed, then arguably this signal can be processed in terms of common mode range.
In fact, in embodiments a UFD module with IP2IN of +40 dBm could be tolerated if 10 dB of cancellation is available from a differential architecture. Differential architectures may extend as great as a 30 dB benefit, for example, without special trimming.
7.2 Example Embodiments to Address DC Offset and Re-Radiation Problems
Section 7.1 above discussed problems related to DC offset and re-radiation that occur during and after the down-conversion process, and were provided for illustrative purposes, and are not limiting. Embodiments were also provided for reducing or eliminating unwanted DC offset and re-radiation using techniques of spectral spreading followed by de-spreading, according to the present invention. Various embodiments related to the problems, method(s), and structure(s) described above are presented in this section (and its subsections). In particular, further applications of the UFT module are provided below in circuit configurations that reduce or eliminate problems of DC offset and re-radiation.
These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.2.1 DC Offset
Exemplary embodiments are provided below for reducing or eliminating unwanted DC offset voltages. These unwanted DC offset voltages include unwanted DC offset voltages created by any source, including non-ideal circuit component operation, re-radiation recapture, local circuit signals traveling or radiating to other circuit sections, etc. The embodiments provided below are not limited to this use, but may have additional applications. For example, these embodiments may be applicable to reducing or eliminating unwanted circuit re-radiation.
7.2.1.1 Reducing DC Offset by Spectral Spreading and De-Spreading
Embodiments for reducing DC offset by spectral spreading and de-spreading, as described above, are further described in the following sub-sections, and additional related embodiments are presented.
7.2.1.1.1 Conventional Wireless Communications Receiver
Down-conversion module 8702 down-converts a modulated carrier signal 8706, according to at least one local oscillator signal 8708, to a down-converted baseband signal 8710.
Down-converted baseband signal 8710 is input to amplifier 8704. Amplifier 8704 amplifies, filters, and/or otherwise processes down-converted signal 8710, and outputs baseband signal 8712.
As described above, and shown in
7.2.1.1.2 Spread/De-Spread Receiver Embodiments of the Present Invention
An embodiment of the present invention addresses undesired DC offsets described above by modifying the local oscillator in such a manner that offsets are randomized and spectrally spread. This pseudo-random local oscillator signal is used to down-convert an input signal, such as a modulated carrier signal, and spread the spectrum of the down-converted signal. After some amount of amplification, filtering, and/or other optional processing, the randomized down-converted signal may be spectrally de-spread to a baseband signal. Because the down-converted signal is spectrally de-spread, offsets are spectrally spread. At least some of the offset, particularly the offset due to local oscillator re-radiation, is reduced or removed from the resulting baseband signal. The offset is spread over a frequency range.
Oscillator 8826 outputs oscillating signal 8830.
Code generator 8832 outputs coded sequence signal 8816. Coded sequence signal 8816 is preferably a signal coded according to a pseudo-random code sequence. For example, acceptable pseudo-random coding includes PN coding. Other applicable code schemes such as are also within the scope of the present invention, such as square waves and Manchester encoding.
First multiplier 8806 receives oscillating signal 8830 and coded sequence signal 8816. First multiplier 8806 multiplies oscillating signal 8830 and coded sequence signal 8816, and outputs a coded oscillating signal 8814. Coded oscillating signal 8814 comprises at least some cycles of oscillating signal 8830 modified (or spread or coded) according to coded sequence signal 8816.
In a preferred embodiment, when coded sequence signal 8816 is a “high” signal and/or represents a “1”, the phase of corresponding cycle(s) of oscillating signal 8830 are not modified, and when coded sequence signal 8816 is a “low” signal and/or represents a “0” or a “−1”, the phase of corresponding cycle(s) of coded oscillating signal 8814 are shifted 180 degrees. For example, as shown in
Pulse-shaping circuit 8828 inputs coded oscillating signal 8814. The output of pulse-shaping circuit 8828 is a coded control signal 8818, which preferably comprises a string of pulses. Coded control signal 8818 comprises at least some pulses that are modified (or spread or coded) according to coded sequence signal 8816.
UFD module 8802 receives an input RF signal 8812 (although it could be an unmodulated signal) and coded control signal 8818.
For example,
Down-converted spread spectrum signal 8820 is optionally amplified and/or otherwise processed by amplifier 8804 (or other circuitry or processing modules), and a processed down-converted spread spectrum signal 8822 results.
Unwanted DC offset may be summed into down-converted spread spectrum signal 8820 during and after down-conversion and spectral spreading, and during and after processing by amplifier 8804.
Second multiplier 8808 receives coded sequence signal 8816 and processed down-converted spread spectrum signal 8822. Second multiplier 8808 multiplies coded sequence signal 8816 and amplified down-converted spread spectrum signal 8822. Down-converted spread spectrum signal 8822 is spectrally de-spread in second multiplier 8808, and baseband signal 8824 is output.
For example, in an embodiment using PN coding, for a positive PN code chip, amplified down-converted spread spectrum signal 8822 is multiplied by 1 (not inverted) in second multiplier 8808. For a negative PN code chip, the amplified down-converted spread spectrum signal 8822 is multiplied by −1 (inverted). In this manner down-converted spread spectrum signal 8822 is spectrally de-spread.
Although only a single down-conversion channel is illustrated in the example embodiment of
In step 10802, an input signal is down-converted. In embodiments, the input signal is down-converted with a universal frequency down-conversion module according to a coded control signal.
In step 10804, the down-converted input signal is spectrally spread to a down-converted spread spectrum signal. In embodiments, step 10804 may be at least partially integral with step 10802.
In step 10806, the down-converted spread spectrum signal is processed. For instance, the down-converted spread spectrum signal may be amplified, filtered, or otherwise processed, as further described above. Furthermore, a DC offset voltage may be summed with the down-converted spread spectrum signal, as described further above.
In step 10808, the down-converted spread spectrum signal is spectrally de-spread to a baseband signal. The down-converted spread spectrum signal is multiplied with a code used to code the control signal. Furthermore, during this step, the DC offset voltage is spectrally spread, as further described above.
For illustrative purposes, the operation of the invention is often represented by flowcharts, such as flowchart 10800 in
7.2.1.3 Charge Injection Reduction Embodiment
The spectral spreading/de-spreading embodiments described above reduce or eliminate DC offset from a variety of sources. In this section, an alternative embodiment, according to the present invention, is provided for reducing or eliminating DC offset due at least to charge injection.
An input RF signal 9014 is received by a first terminal 9028 of MOSFET 9008. A control signal 9018 is received by a second terminal 9030 of MOSFET 9008. A third terminal 9032 of MOSFET 9008 is coupled to a first terminal 9034 of storage device 9004. A second terminal 9036 of storage device 9004 is coupled to reference potential 9006 such as a ground 9012, or some other potential. In an embodiment, MOSFET 9008 contained within UFT module 9002 opens and closes as a function of control signal 9018. As a result of the opening and closing of this switch, a down-converted signal, referred to as output signal 9016, results.
A well known phenomenon called charge injection may occur in such a switching environment. As control signal 9018 applies a pulse waveform to the gate of MOSFET 9008, MOSFET 9008 is caused to open and close. During this operation, charge allowed to flow along a DC path 9024 may build on the gate-to-drain and/or gate-to-source junctions of MOSFET 9008, as indicated on
In step 10902, an input signal is coupled by a series capacitor to an input of a universal frequency down-conversion module.
In step 10904, the input signal is frequency down-converted with the universal frequency down-conversion module to a down-converted signal. The input signal is down-converted according to a control signal. The control signal under-samples the input signal.
In step 10906, a DC offset voltage in the down-converted signal generated during step 10904 is reduced. In an embodiment, the DC offset voltage is generated at least by charge injection effects due to interaction of the control signal with the universal frequency down-conversion module, as further described above.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.2.1.4 Auto-Zero Compensation
Unwanted DC offset may be injected by circuit components in the intermediate frequency (IF) processing path or baseband processing path following a UFD module. In some cases, this DC offset voltage must be reduced or eliminated. In some situations, the output signal down-converted by the UFD module may be a low level signal, where even small DC offsets inserted by components following the UFD module may undesirably affect its value.
The previous section described inserting a series capacitor prior to the UFD module to reduce DC offset voltages due to charge injection. In embodiments, a capacitor may be added in series in the baseband processing path after a UFD module to reduce or eliminate DC offset voltages. In some situations, however, adding a capacitor in series in the baseband processing path after the UFD module is not desirable. For instance, in some situations, it may be difficult to charge such a series capacitor reliably.
UFD module 9246, filter 9248, amplifier 9202, and optional IF down-converter 9250 may each add a DC offset voltage to their respective outputs signals. As described above, the DC offset voltage may undesirably affect the value of the down-converted signal. It would be desirable to provide a circuit that may be inserted for any of the components shown in
In the example circuit shown, auto-zero compensation circuit 9200 is located following amplifier 9202 (see also
Amplifier 9202 receives an input signal 9260, and outputs an amplified input signal 9262. Amplified input signal 9262 may comprise an unwanted DC offset voltage due to amplifier 9202. While an ideal amplifier has zero input offset voltage (i.e., DC offset voltage referred to the input) and no offset voltage drift, most actual amplifiers have offset voltages due to a mismatch of input transistors and resistors on the monolithic circuit. This input offset voltage may drift across temperature, and hence most amplifiers are specified with an input offset voltage temperature coefficient. An amplifier may suffer from further offset voltage from input bias currents. While an ideal amplifier has zero current flowing into and out of its inputs, most actual amplifiers have non-zero input bias currents flowing into and out of their inputs. These currents can create an input voltage that resembles a DC offset voltage when they flow through resistors coupled to the amplifier inputs. Auto-zero compensation circuit 9200 removes DC offset voltages and voltage drift created by these mechanisms.
A first terminal 9226 of resistor 9204 and a first terminal 9228 of switch 9206 are coupled to amplified input signal 9262. A second terminal 9230 of resistor 9204 and a second terminal 9232 of switch 9206 are coupled to a first terminal 9234 of capacitor 9208 and a first input terminal 9236 of second summer 9212. A third terminal 9244 of switch 9206 is coupled to a receive mode signal 9242. A second terminal 9238 of capacitor 9208 is coupled to first voltage reference 9214. A second input terminal 9240 of second summer 9212 is coupled to second voltage reference 9216. First and second voltage references 9214 and 9216 may or may not be equal to the same voltage value.
A receiver system may incorporate one or more auto-zero compensation circuits 9200 in its down-converted signal path. When such a receiver system enters a receive mode, i.e., it has entered a mode where it is ready to down-convert received signals, a receive mode signal 9242 is activated. Receive mode signal 9242 causes switch 9206 to close, and capacitor 9208 charges to the output voltage of amplifier 9202. Hence, capacitor 9208 attains, or is charged with the value of the output of amplifier 9202, which comprises any DC offset voltage due to amplifier 9202. Capacitor 9208 may be a relatively large value capacitor, such as 1.0-0.1 μF, but the invention is not limited to this range.
After switch 9206 is closed for a length of time sufficient to charge capacitor 9208 to the value of amplified output signal 9262, (the output of amplifier 9202), receive mode signal 9242 causes switch 9206 to open. When switch 9206 is open, the path from amplifier 9202 to the first terminal 9234 of capacitor 9208 is through resistor 9204. Resistor 9204 may be a relatively large value resistor, but the invention is not limited to this example. In this configuration, capacitor 9208 relatively slowly follows the voltage of the output of amplifier 9202. In this way, capacitor 9208 maintains the DC offset voltage value of amplifier 9202, following any DC offset voltage drift due to changes in environmental temperature and the like.
Second summer 9212 adds the voltage stored in capacitor 9208 with the value of second voltage reference 9216, and outputs adjusted DC offset voltage 9224. Second voltage reference 9216 may be used to adjust or center the circuit output voltage, as described below. In alternate embodiments, second voltage reference 9216 and second summer 9212 are not present, and the first terminal 9234 of capacitor 9208 is coupled to first summer 9210.
First summer 9210 subtracts the adjusted DC offset voltage 9224 from amplified input signal 9262, and outputs DC offset adjusted output signal 9220 (which is received by the IF down-converter 9250 in the example of
In step 11002, a DC offset voltage in an input signal is stored while in a signal non-receive mode.
In step 11004, the mode is changed to a signal receive mode.
In step 11006, the input signal is followed relatively slowly to maintain the DC offset voltage and any DC offset voltage drift.
In step 11008, the maintained DC offset voltage is summed with a centering voltage to form an adjusted DC offset voltage signal. A centering voltage such as second voltage reference 9216 may be used.
In step 11010, the adjusted DC offset voltage signal is subtracted from the input signal to form a DC offset adjusted output signal.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to this embodiment. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.2.1.5 Reducing DC Offset with Differential Configurations
DC offset voltages due to charge injection may also be reduced or eliminated through the use of differential UFD module configurations. Furthermore, circuit re-radiation may be reduced or eliminated through the use of differential UFD module configurations. Exemplary differential UFD module circuit embodiments are described below. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
In an embodiment, two UFD modules are arranged in a differential configuration, where a first UFD module receives an actual RF signal as an input, and a second UFD module receives circuit ground, or some other circuit voltage, as an input. Furthermore, both UFD modules receive the same control signal. As a result, the two UFD modules produce substantially similar DC offset voltages due to charge injection. The UFD module output signals may be subtracted from each other, and as a result the DC offset voltage due to charge injection in the output of the first UFD module will be subtracted out.
Optional LNA 9302 receives an input RF signal 9324 and outputs an amplified input RF signal 9326.
Amplified input RF signal 9326 is received by a first terminal 9356 of first UFT module 9304. A second terminal 9338 of first UFT module 9304 is coupled to a first terminal 9340 of first capacitor 9308. First capacitor 9308 may be any type of applicable storage device. A third terminal 9342 of first UFT module 9304 receives a control signal 9328. Control signal 9328 is generated by control signal generator 9310. First UFT module 9304 down-converts amplified input RF signal 9326 according to control signal 9328 in a manner as described elsewhere herein. First UFT module 9304 outputs actual output signal 9330 (it is called the “actual” output signal 9330 because it is derived from input RF signal 9324), which is stored on first capacitor 9308. As described above, first UFT module 9304 may add unwanted DC offset voltage to actual output signal 9330, due to charge injection effects.
A first terminal 9344 of second UFT module 9316 receives dummy input signal 9332 (it is called a “dummy” input signal 9332 because it is not a received signal, but is instead generated to address offset issues) from a first terminal 9346 of dummy impedance 9312. A second terminal 9348 of dummy impedance 9312 is coupled to second voltage reference 9314. Second voltage reference 9314 is a circuit voltage, preferably ground. Impedance 9312 approximates for second UFT module 9316 the input impedance presented to the input of first UFT module 9304 (that is, impedance 9312 is substantially equal to the input impedance of first UFT module 9304). Impedance 9312 is implemented using any well known combination of circuit elements. A second terminal 9350 of second UFT module 9316 is coupled to a first terminal 9352 of second capacitor 9318. A third terminal 9354 of second UFT module 9316 receives control signal 9328. Second UFT module 9316 down-converts dummy input signal 9332 according to control signal 9328 in a similar fashion as described above. Second UFT module 9316 outputs dummy output signal 9334, which is stored on second capacitor 9318. Dummy output signal 9334 comprises unwanted DC offset voltage due to charge injection effects in second UFT module 9316, similar to that generated by first UFT module 9304. The DC offset voltages due to charge injection on actual output signal 9330 and dummy output signal 9334 are substantially similar due to the similar UFT module configurations.
Summer 9322 subtracts dummy output signal 9334 from actual output signal 9330, and outputs output signal 9336. Output signal 9336 is a down-converted version of input RF signal 9324, with DC offset due to charge injection in UFT module 9304 substantially reduced or eliminated by subtracting out the DC offset similarly created in UFT module 9316.
Preferably, the noise entering on first terminals 9356 and 9344 of UFT modules 9304 and 9316 is matched. If the frequency spectrum of the noise entering first UFT module 9304 on input RF signal 9324 is different than the noise entering second UFT module 9316 from second voltage reference 9314, the difference may show up on output signal 9336. One example of where the noise spectrums may be different is when there is a filter on input RF signal 9324 prior to first UFT module 9304, which filters out some noise frequencies. This difference may be solved, for example, by placing a similar filter at the input of second UFT module 9316.
In step 11102, an input signal is received.
In step 11104, the input signal is frequency down-converted with a first universal frequency down-conversion module to an actual down-converted signal.
In step 11106, a dummy input signal is received. In an embodiment, a dummy impedance is matched with the input impedance of an input of the first universal frequency down-conversion module. The matched dummy impedance is coupled to an input of the second universal frequency down-conversion module to form the dummy input signal.
In step 11108, the dummy signal is frequency down-converted with a second universal frequency down-conversion module to a dummy down-converted signal.
In step 11110, the dummy down-converted signal is subtracted from the actual down-converted signal to form an output signal. DC offset voltages due to said first and said second universal frequency down-conversion modules are canceled by the subtraction of step 11110, as further described above.
Buffer/inverter 9402 receives an input RF signal 9424.
First and second UFT modules 9404 and 9416 operate similarly to first and second UFT modules 9304 and 9316 of
Second UFT module 9416 receives inverted amplified input RF signal 9414. Second UFT module 9416 down-converts inverted amplified input RF signal 9414 according to control signal 9428, and outputs inverted output signal 9432. Inverted output signal 9432 comprises DC offset voltage due to charge injection in second UFT module 9416.
Summer 9422 subtracts inverted output signal 9432 from non-inverted output signal 9430, and outputs an output signal 9426.
Additionally, re-radiation may be substantially reduced or eliminated due to this configuration. Control signal noise produced in first and second UFT modules 9404 and 9416 due to pulses on control signal 9428 may travel back through buffer/inverter 9402. If first and second UFT modules 9404 and 9416 are configured in a substantially similar fashion and receive the same control signal, they will produce substantially equivalent control signal noise. Because the control signal noise from second UFT module 9416 will be inverted by buffer/inverter 9402 when passing back through buffer/inverter 9402, it will cancel when combined with the non-inverted control signal noise from first UFT module 9404 passing back through buffer/inverter 9402. Furthermore, the noise matching concerns of the prior differential circuit embodiment of
In step 11202, an input signal is received.
In step 11204, the received input signal is amplified to a non-inverted output signal and an inverted output signal.
In step 11206, the non-inverted output signal is down-converted with a first universal frequency down-conversion module to a non-inverted down-converted signal.
In step 11208, the inverted output signal is down-converted with a second universal frequency down-conversion module to an inverted down-converted signal.
In step 11210, the inverted down-converted signal is subtracted from the non-inverted down-converted signal to form an output signal. DC offset voltages in the non-inverted down-converted signal and the inverted down-converted signal produced by the first and second universal frequency down-conversion modules, respectively, are canceled.
In step 11212, the first universal frequency down-conversion module and the second universal frequency down-conversion module are configured to generate substantially equal DC offset voltages given the same input signal.
It should be understood that the above examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.2.1.6 Reducing DC Offset with Differential Outputs
Unwanted DC offset voltages may be reduced or canceled through the use of differential receiver circuit outputs.
First and second impedance match 9502 and 9504 are optional, the necessity of which being determined on an application-by-application basis. In a preferred embodiment, first impedance match 9502 is a first inductor 9514. In a preferred embodiment, second impedance match 9504 is a second inductor 9516. However, other impedance match circuits may be used.
Tank circuit 9506 is optional, the necessity of which being determined on an application-by-application basis. In a preferred embodiment, tank circuit 9506 comprises a first capacitor 9518 and a third inductor 9520, although other circuits may be used.
In a preferred embodiment, differential UFD module 9508 comprises a first UFT module 9522, a second UFT module 9524, and a storage module 9534. In a preferred embodiment, storage module 9534 comprises a second capacitor 9526.
A positive or “plus” signal input of a differential RF input signal 9528 is input through first impedance match 9502 to a first terminal 9536 of tank circuit 9506. A negative or “minus” signal input of differential RF input signal 9528 is input through second impedance match 9504 to a second terminal 9538 of tank circuit 9506.
First UFT module 9522 is coupled to first terminal 9536 of tank circuit 9506, and receives the “plus” signal input of differential RF input signal 9528. Second UFT module 9524 is coupled to second terminal 9538 of tank circuit 9506, and receives the “minus” signal input of differential RF input signal 9528.
First and second UFT modules 9522 and 9524 down-convert differential RF input signal 9528 according to a control signal 9532, which is output by control signal generator 9510, in a manner as described elsewhere herein. The outputs of first and second UFT modules 9522 and 9524 are stored in storage module 9534, and output as differential output signal 9530.
First UFT module 9522 outputs a “plus” output of differential output signal 9530. Second UFT module 9524 outputs a “minus” output of differential output signal 9530. Differential output signal 9530 is equal to the difference voltage between these “plus” and “minus” outputs.
A first terminal 9540 of storage module 9534 is coupled to the “plus” output of differential output signal 9530. A second terminal 9542 of storage module 9534 is coupled to the “minus” output of differential output signal 9530.
Resistor 9512 is optional, the necessity of which being determined on an application-by-application basis. Resistor 9512, when present, operates as a load resistance, the value of which may be determined on an application-by-application basis. A first terminal 9544 of resistor 9512 is coupled to the “plus” output of differential output signal 9530. A second terminal 9546 of resistor 9512 is coupled to the “minus” output of differential output signal 9530.
Due to their similar layout and circuit configuration, and due to control signal 9532, first UFT module 9522 and second UFT module 9524 each generate substantially equal DC offset voltages due to charge injection effects. The DC offset voltage generated by first UFT module 9522 is applied to first terminal 9540 of storage module 9534. The DC offset voltage generated by second UFT module 9524 is applied to second terminal 9542 of storage module 9534. Because differential output signal 9532 is measured across storage module 9534, the DC offset voltages due to first and second UFT module 9522 and 9524 substantially cancel each other out.
In step 11302, an input signal is differentially received. For example, a positive node input signal and a negative node input signal are received.
In step 11304, the differentially received input signal is down-converted with a differential universal frequency down-conversion module to a differential down-converted signal. The differential down-converted signal comprises a positive node down-converted signal and a negative node down-converted signal. In an embodiment, the differential universal frequency down-conversion module comprises a positive node switch (UFT) module and a negative node switch (UFT) module. The positive node switch module and the negative node switch module are configured to generate substantially equal DC offset voltages in the positive node down-converted signal and the negative node down-converted signal, respectively, as described above.
In step 11306, the differential down-converted signal is measured between the positive node down-converted signal and the negative node down-converted signal. The DC offset voltages in the positive node down-converted signal and the negative node down-converted signal substantially cancel, as described above.
Further differential circuit configurations for canceling DC offset voltages will be apparent to persons skilled in the relevant art(s) from the teaching herein. Exemplary differential receiver circuit output embodiments are described above. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.2.2 Re-Radiation
Re-radiation, as described above, is an undesirable phenomenon where a signal comprising one or more frequency components generated by receiving circuitry is transmitted by an antenna.
As described above, re-radiation may be undesirably received back by the same antenna that transmitted the re-radiation. As shown in
For at least these reasons, it is desirable to reduce or eliminate circuit re-radiation. Exemplary embodiments are provided below for reducing or eliminating circuit re-radiation. The embodiments provided below are not limited to this use, but may have additional applications. For example, these embodiments may be applicable to reducing or eliminating unwanted DC offset voltages.
7.2.2.1 Reducing Re-Radiation by Adjusting Control Signal Attributes
In the present invention, a local oscillator may be used to generate a control signal used to down-convert received RF signals. The control signal may comprise frequency components related to the local oscillator frequency and its harmonics. As described above, one or more frequency components of the local oscillator signal may leak from a nearby antenna as circuit re-radiation. As a result, attributes of circuit re-radiation are directly related to attributes of control signal frequency components. Hence, re-radiation potentially may be reduced or eliminated by adjusting one or more attributes of the control signal frequency components. Control signal attributes that may be adjusted at least include control pulses width, control pulse amplitude, and/or control pulse phase.
In an exemplary embodiment for changing the frequency content of the re-radiated signal, the pulse width of the control pulses of the control signal may be lengthened. As shown in
Frequency components of potential re-radiation can be lowered more by further widening the control pulses. For example,
A pulse width can be widened even more as would be understood by persons skilled in the relevant arts from the teachings herein. To what degree the pulse width may be widened will be determined on an application by application basis. The pulse width may be varied by whole increments of π, or any fraction thereof. It should be understood that the above pulse width examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
In step 11402, an input signal is frequency down-converted with a universal frequency down-conversion module to a down-converted signal. The input signal is down-converted according to a control signal comprising a train of pulses having pulse widths.
In step 11404, a signal related to the control signal is re-radiated.
In step 11406, the pulse widths are increased to decrease a frequency of the re-radiated signal. In an embodiment, the pulse widths may be selected according to the equation: pulse width=180+360·n degrees of a frequency of said input signal, wherein n is any integer ≧zero. As n is increased, a frequency of the re-radiated signal is decreased.
7.2.2.1.1 I/Q Modulation Receiver Control Signal Considerations and Embodiments
Design considerations exist for I/Q modulation receiver circuits in regard to control signals. The embodiments provided above for changing control signal pulse widths are applicable to I/Q modulation receiver circuits. However, when modifying control signal pulse widths in regards to I/Q modulation receiver circuits to overcome problems with re-radiation as described above, or other problems, certain design constraints may need to be considered. For instance, in some embodiments, such as described below, pulses of the I-phase control signal and pulses of the Q-phase control signal may not overlap, and must be configured such that they do not overlap to fulfill this requirement. In alternate embodiments, such as described below, an I/Q modulation receiver circuit may be configured such that I-phase and Q-phase control signals may overlap. Exemplary embodiments are provided below for overcoming at least some design constraints related to control signal pulses for I/Q modulation receiver circuits, according to the present invention.
It should be understood that the following I/Q modulation receiver examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.2.2.1.1.1 Non-Overlapping I/Q Control Signal Pulses Embodiments
An input RF I/Q signal 9722 is received by first UFD module 9702. First UFD module 9702 down-converts the I-phase signal portion of input RF I/Q signal 9722 according to a control signal 9728, which is output by control signal generator 9706. First UFD module 9702 outputs an I output signal 9724.
In an embodiment, first UFD module 9702 comprises a first UFT module 9710, a first storage module 9712, and a first voltage reference 9714.
Control signal 9728 is received by phase shifter 9708. In an I/Q modulation embodiment, phase shifter 9708 preferably shifts the phase of control signal 9728 by 90 degrees, although other phase shifts are possible. Phase shifter 9708 outputs phase-shifted control signal 9730.
Input RF I/Q signal 9722 is received by second UFD module 9704. Second UFD module 9704 down-converts the Q-phase signal portion of input RF I/Q signal 9722 according to phase-shifted control signal 9730. Second UFD module 9704 outputs a Q output signal 9726.
In an embodiment, second UFD module 9704 comprises a second UFT module 9716, a second storage module 9718, and a second voltage reference 9720. First and second voltage references 9714 and 9720 may or may not be equal to the same voltage value.
For example, an I-control signal 9802 is shown in
As illustrated in
In an another example,
The overlap problem may be overcome by creating control signals with non-overlapping pulses. For example,
In a further example,
Further control signal waveform configurations exist for implementing non-overlapping pulses, according to embodiments of the present invention, as would be recognized by persons skilled in the relevant art(s) from the teachings herein. I- and Q-control signal pulses may be widened, or made more narrow. I- and Q-control signal pulses may be made to occur further apart or closer together. A Q-control signal may be phase-shifted from a corresponding I-control signal by 90 degrees, 270 degrees, 450 degrees, 630 degrees, and so on, such that the I-control signal is matched with the I-phase input RF signal component, and the Q-control signal is matched with the Q-phase input RF signal component. Pulses on an I-phase control signal may be shifted from each other by any multiple of 180 (with one or more inverters possibly required, as described above) or 360 degrees. I- and Q-control signals may be formed to these requirements for use in I/Q modulation receiver circuit 9700 of
In step 11502, an input RF I/Q modulated signal is frequency down-converted with a first universal frequency down-conversion module according to a control signal. The input signal is down-converted to an in-phase information signal. The control signal comprises a train of pulses. In an embodiment, the train of pulses are generated to have apertures approximately equal to 180+360·n degrees of a frequency of said input RF I/Q modulated signal, wherein n is any integer greater than or equal to 0.
In step 11504, the control signal is phase-shifted. In embodiments, the control signal is phase-shifted by 90 degrees of a frequency of said input RF I/Q modulated signal. In alternative embodiments, the control signal may be shifted by 90+m·180 degrees, wherein m is any integer greater than or equal to 1. In embodiments, the control signal may be phase shifted such that pulses on the control signal do not overlap pulses on the phase-shifted control signal.
In step 11506, the input RF I/Q modulated signal is frequency down-converted with a second universal frequency down-conversion module according to the phase-shifted control signal. The input signal is down-converted to a quadrature-phase information signal.
7.2.2.1.1.2 Buffered I/Q Modulation Receiver Embodiment
Exemplary embodiments are provide below for I/Q modulation receiver circuits where control signal pulses may overlap. Such embodiments may provide advantages where it is desirable to modify control signal pulse attributes as described above to solve problems with circuit re-radiation, and other problems. Additional and alternate embodiments will be recognized by persons skilled in the relevant art(s) from the teachings herein, and are within the scope of the present invention.
Buffered I/Q modulation receiver circuit 9900 comprises an optional splitter 9902, a first low noise amplifier (LNA) 9904, a second LNA 9908, a control signal generator 9910, a first UFD module 9912, a second UFD module 9914, and a phase shifter 9916. Buffered I/Q modulation receiver circuit 9900 is configured substantially similar to, and operates in a similar fashion to I/Q modulation receiver circuit 9700 of
Optional splitter 9902 optionally splits an input RF I/Q signal 9930, and outputs a first split input RF I/Q signal 9944 to first LNA 9904, and a second split input RF I/Q signal 9946 to second LNA 9908.
First LNA 9904 buffers and optionally amplifies first split input RF I/Q signal 9944, and outputs a first buffered input RF I/Q signal 9936.
Second LNA 9908 buffers and optionally amplifies second split input RF I/Q signal 9946, and outputs a second buffered input RF I/Q signal 9938.
First UFD module 9912 receives first buffered input RF I/Q signal 9936. First UFD module 9912 down-converts first buffered input RF I/Q signal 9936 according to a control signal 9940, which is output by control signal generator 9910. First UFD module 9912 outputs I output signal 9932. In an embodiment, first UFD module 9912 comprises a first UFT module 9918, a first storage module 9920, and a first voltage reference 9922.
Phase shifter 9916 receives control signal 9940, and outputs a phase-shifted control signal 9942. Phase-shifted control signal 9942 is preferably shifted by 90 degrees from control signal 9940, but may also be shifted by 270 degrees, 450 degrees, 630 degrees, and so on.
Second UFD module 9914 receives second buffered input RF I/Q signal 9938. Second UFD module 9914 down-converts second buffered input RF I/Q signal 9938 according to phase-shifted control signal 9942. Second UFD module 9914 outputs Q output signal 9934. In an embodiment, second UFD module 9914 comprises a second UFT module 9924, a second storage module 9926, and a second voltage reference 9928.
As described elsewhere herein, when first UFT module 9918 transfers energy from first buffered input RF I/Q signal 9936, first buffered input RF I/Q signal 9936 will be distorted to some degree. Likewise, when second UFT module 9924 transfers energy from second buffered input RF I/Q signal 9938, second buffered input RF I/Q signal 9938 will be distorted to some degree. First and second LNA 9904 and 9908 buffer the input RF I/Q signals entering first and second UFD modules 9912 and 9914 from input RF I/Q signal 9930. Hence, input RF I/Q signal 9930 will not be substantially distorted by energy transfer occurring in either of first and second UFD module 9912 and 9914. Because of this, the I- and Q-control signals used to cause first and second UFD modules 9912 and 9914 to down-convert their respective input RF I/Q signals may have overlapping I- and Q-pulses. Hence, for example, control signal 9940 may appear as I-control signal 9802 of
In step 11602, an input RF I/Q modulated signal is buffered with a first low noise amplifier and a second low noise amplifier. In an alternative embodiment, instead of or in addition to buffering the input RF I/Q modulated signal as just described, the input RF I/Q modulated signal may be split into a first split RF I/Q modulated signal and a second split RF I/Q modulated signal.
In step 11604, the first buffered (and/or first split) RF I/Q modulated signal is frequency down-converted with a first universal frequency down-conversion module according to a control signal. The input signal is down-converted to an in-phase information signal. The control signal comprises a train of pulses. In an embodiment, the train of pulses are generated to have apertures approximately equal to 180+360·n degrees of a frequency of said input RF I/Q modulated signal, wherein n is any integer greater than or equal to 0.
In step 11606, the control signal is phase-shifted. In embodiments, the control signal is phase-shifted by 90+m·180 degrees of a frequency of said input RF I/Q modulated signal, wherein m is any integer greater than or equal to 0. In embodiments, the control signal may be phase shifted such that pulses on the control signal overlap pulses on the phase-shifted control signal.
In step 11608, the second buffered (and/or second split) RF I/Q modulated signal is frequency down-converted with a second universal frequency down-conversion module according to the phase-shifted control signal. The input signal is down-converted to a quadrature-phase information signal.
7.2.2.2 Reducing Re-Radiation with Placebo Down-Conversion Modules
Control signal frequency components may be adjusted or shifted through the use of one or more UFT modules, called “placebo” UFT modules, and one or more corresponding “placebo” control signals. In a placebo embodiment, an “actual” UFT module receives and down-converts a received RF input signal with an “actual” control signal as described elsewhere herein. Furthermore, a placebo UFT module receives a placebo control signal, and may also down-convert the received RF input signal, to output a down-converted signal. The actual control signal and one or more placebo control signals may cause circuit re-radiation. This resulting circuit re-radiation will be related to a combination of the actual control signal waveform and the one or more placebo control signal waveforms. Hence, attributes of the resulting circuit re-radiation may be manipulated by using various placebo control signal waveforms, to cause overall circuit re-radiation to be less harmful to circuit performance. Characteristics of a particular placebo control signal waveform may be determined on an application-by-application basis. The term “placebo” is used because the signal down-converted by the placebo circuitry is not necessarily used by subsequent signal processing hardware and software, but may actually remain unutilized. The signal down-converted by the “actual” circuitry is used by subsequent signal processing.
Receiver 10000 with placebo circuit 10004 comprises an actual UFD module 10002, a placebo UFD module 10004, a control signal generator 10006, and a phase shifter 10008.
Actual UFD module 10002 receives an input RF signal 10022. Actual UFD module 10002 down-converts actual input RF signal 10022 according to a control signal 10028, which is output by control signal generator 10006, in a manner as described elsewhere herein. Actual UFD module 10002 outputs an actual output signal 10024. In an embodiment, actual UFD module 10002 comprises an actual UFT module 10010, an actual storage module 10012, and an actual voltage reference 10014.
Phase shifter 10008 receives control signal 10028, and outputs a phase-shifted placebo control signal 10030. Phase-shifted placebo control signal 10030 is preferably shifted such that pulses on phase-shifted placebo control signal 10030 do not overlap with pulses on control signal 10028. In other embodiments, pulses on phase-shifted placebo control signal 10030 may overlap pulses on control signal 10028, as would be understood by persons skilled in the relevant art(s) from the teachings herein.
Placebo UFD module 10004 receives input RF signal 10022. Placebo UFD module 10004 down-converts input RF signal 10022 according to phase-shifted placebo control signal 10030. Placebo UFD module 10004 outputs placebo output signal 10026. In an embodiment, placebo UFD module 10004 comprises a placebo UFT module 10016, a placebo storage module 10018, and a placebo voltage reference 10020.
In a receiver circuit embodiment that does not include a placebo UFD module 10004, potential circuit re-radiation (and the frequency spectrum of such re-radiation) will be related to the control signal waveform being used, such as control signal waveform 10102. In a receiver circuit embodiment that includes a placebo UFD module 10004, the potential circuit re-radiation (and the frequency spectrum of such re-radiation) will be related to the control signal being used, such as control signal waveform 10102, and the placebo control signal waveform being used, such as placebo control signal waveform 10104.
Furthermore, as shown in
In embodiments, placebo output signal 10026 is not used in down-stream information signal processing. In alternative embodiments, placebo output signal 10026 may be used in down-stream information signal processing.
In step 11702, an input signal is frequency down-converted with a first universal frequency down-conversion module to a first down-converted signal, wherein the input signal is down-converted according to a control signal, wherein the control signal comprises a train of pulses, wherein pulses of the control signal occur every 360+360·n degrees of a frequency of the input signal, wherein n is equal to any integer greater or equal 0.
In step 11704, the control signal is phase-shifted, wherein the control signal is phase shifted in a range between 0 degrees and 360+360·n degrees of a frequency of the input signal (pulses of control signal and phase-shifted control signal may overlap). In alternative embodiments, the pulses are of width m degrees, and the control signal is phase-shifted in a range between m degrees and 360−m+360·n degrees of a frequency of the input signal (no overlap of pulses between control signal and phase-shifted control signal). In embodiments, the control signal is phase shifted to a phase-shifted control signal in order to adjust at least one frequency of the re-radiated signal. In further embodiments, the control signal is phase shifted to a phase-shifted control signal in order to adjust at least one frequency of the re-radiated signal to be above a frequency range of interest of the input signal.
In step 11706, the input signal is frequency down-converted with a second universal frequency down-conversion module to a second down-converted signal, wherein the input signal is down-converted according to the phase-shifted control signal. The second universal frequency down-conversion module is used as a placebo universal frequency down-conversion module.
In step 11708, a signal is re-radiated that is at least a function of the control signal and the phase-shifted control signal.
Exemplary receiver with placebo circuit embodiments are described above. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, further placebo UFD modules with additional placebo control signals may be added. The invention is intended and adapted to include such alternate embodiments.
7.2.2.3 Reducing Re-Radiation with Adjacent Apertures
Potential control signal circuit re-radiation may be reduced or eliminated by the use of adjacent control signal pulses or apertures. By creating control signal pulses that are adjacent, the rising and falling edges of adjacent pulses may partially or entirely cancel out any re-radiation due to the individual pulses.
An input RF signal 10214 is received by first UFD module 10202. First UFD module 10202 down-converts input RF signal 10214 according to a control signal 10220, which is output by control signal generator 10206, in a manner as described elsewhere herein. First UFD module 10202 outputs first output signal 10216. First UFD module 10202 comprises a first UFT module 10210.
Phase shifter 10208 receives control signal 10220, and outputs a phase-shifted control signal 10222. In an embodiment, the width of pulses on control signal 10220 and on phase-shifted control signal 10222 approach π radians, although other values could be used. Phase-shifted control signal 10222 is preferably shifted by π radians from control signal 10220, although other values could be used.
Input RF signal 10214 is received by second UFD module 10204. Second UFD module 10204 down-converts input RF signal 10214 according to phase-shifted control signal 10222, in a manner as described elsewhere herein. Second UFD module 10204 outputs second output signal 10218. Second UFD module 10204 comprises a second UFT module 10212.
Because the width of pulses on control signal waveform 10302 and π-shifted control signal waveform 10304 are equal to or less than π radians, their combined potentially re-radiated signal will be related to combined signal waveform 10306. As control signal waveform 10302 and π-shifted control signal waveform 10306 approach having pulse widths equal to π radians, combined signal waveform 10306 will approach the equivalent of a DC level, with a voltage level substantially equivalent to the pulse amplitudes. In other words, combined signal waveform 10306 will approach a DC level because as pulses of waveforms 10302 and 10304 approach a width of π, the rising and falling edges of the waveforms 10302 and 10304 will increasingly cancel each other.
The use of adjacent apertures may lead to reduced levels of circuit re-radiation, and improved circuit performance. Re-radiated signal components will be due to combined signal waveform 10306. Specifically, re-radiated signal components will be due to transitions from low to high and high to low in waveform 10306, shown as spikes 10308, but the frequency content of such re-radiated signal components due to spikes 10308 will primarily be above the frequency bands of interest.
In step 11802, an input signal is frequency down-converted with a first universal frequency down-conversion module to a first down-converted signal, wherein the input signal is down-converted according to a control signal, wherein the control signal comprises a train of pulses, wherein the pulses have widths less than or equal to 180+360·n degrees of a frequency of the input signal, wherein n is any integer greater than or equal to 0.
In step 11804, the control signal is phase shifted, wherein the control signal is phase-shifted by 180+360·n degrees of a frequency of the input signal. In an embodiment, the pulses of the control signal are substantially adjacent to pulses of the phase-shifted control signal.
In step 11806, the input signal is frequency down-converted with a second universal frequency down-conversion module to a second down-converted signal, wherein the input signal is down-converted according to the phase-shifted control signal.
In step 11808, a signal is re-radiated that is at least a function of the control signal and the phase-shifted control signal. In an embodiment, a spike is formed in the re-radiated signal at a transition of the adjacent pulses of the control signal and the phase-shifted control signal. In an embodiment, a voltage amplitude of the spike approaches zero as the pulses of the control signal and the pulses of the phase-shifted control signal approach 180+360·n degrees in width (i.e., the pulses become more adjacent). In an embodiment, at least one frequency of the spike is above a frequency range of interest of the input signal. In embodiments, as the pulse widths approach 180+360·n degrees of a frequency of the input signal, the re-radiated signal approaches a DC level.
In alternate embodiments, other adjacent control signal pulse configurations may be used.
Additional control signals may be used to produce even longer strings of adjacent pulses.
Furthermore, the use of adjacent apertures may reduce the need for input impedance matching and tank circuitry. This is because with adjacent apertures, the UFT modules in combination are closed for longer fractions of a control signal cycle and hence, the input signal is being stored more continuously (by a storage module, for example). Because the input signal is being stored more continuously, there is less opportunity or need to store the input signal in one or more input tank circuits during the periods when the UFT modules are open. In other words, more of the energy of the input waveform is being stored and used with adjacent apertures. Furthermore, having the UFT module(s) closed for longer periods of time affects the circuit input impedance, and may alter or decrease the need for input impedance matching.
In step 11810, a phase-shifted control signal is phase shifted to a further phase-shifted control signal. The phase-control signal is phase shifted by the same amount as the prior phase shifter. This causes the current aperture or pulse to be the same width as, and adjacent to, the prior aperture.
In step 11812, the input signal is frequency down-converted with a further universal frequency down-conversion module to a corresponding down-converted signal, wherein the input signal is down-converted according to the further phase-shifted control signal.
In step 11814, a signal is re-radiated that is a function of at least the control signal and the phase-shifted control signals.
In step 11816, operation proceeds to step 11810 if the number of universal frequency down-conversion modules (adjacent apertures) is less than some desired number x. This process forms a chain of adjacent apertures, of a number of pulses x.
Exemplary receivers using adjacent apertures embodiments are described above. However, it should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, control signals with pulses of widths other than π radians where the control signals have different pulse widths, may be used. The invention is intended and adapted to include such alternate embodiments.
7.2.3 Additional DC Offset and Re-Radiation Reduction Embodiments
Exemplary embodiments for DC Offset and/or re-radiation reduction or cancellation are described above. Such embodiments may be used alone or in combination, based on the application and on implementation issues. It should be understood that these examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. For example, many of the components described herein are optional, whether or not explicitly indicated as such. The invention is intended and adapted to include such alternate embodiments.
7.3 Example Embodiments to Improve Dynamic Range
Receivers, amplifiers, and other electronic circuits, may suffer from problems related to dynamic range. Generally, “dynamic range” refers to the ratio of the maximum to minimum signal input capability over which an amplifier or other component can operate within some specified range of performance. For instance, if an input signal to an amplifier causes the amplifier to exceed its dynamic range, i.e., the input signal amplitude is too large, the amplifier may no longer amplify properly, the amplifier may rail, and/or may operate in a non-linear region. In a receiver, the signal being amplified may be a down-converted signal. If the dynamic range of the amplifier, or other component, is exceeded, the value of the down-converted signal may be adversely affected.
The concept of dynamic range is further described in the following sub-sections. Furthermore, example methods and systems are provided in subsequent sections below for improving dynamic range.
7.3.1 Adjusting Universal Frequency Down-Conversion Module Dynamic Range
Some circuit implementations may suffer from a lack of dynamic range. For instance, when input RF signals become too high or too low, they may cause a switch in a UFT module to remain continuously open or closed, regardless of the level of the control signal. This may result in problems with output signal linearity and output signal clipping, which may lead to errors in decoding the baseband output signal.
In an embodiment, impedance match 10502 comprises an inductor 10510. The operation of the present and of additional embodiments for impedance match 10502 are further described elsewhere herein.
In an embodiment, tank circuit 10504 comprises a capacitor 10512 and an inductor 10514. The operation of the present and of additional embodiments for tank circuit 10504 are further described elsewhere herein.
UFD module 10506 comprises a UFT module 10516, a storage module 10520, and a first voltage reference 10524. The operation of the present and of additional embodiments for UFD module 10506 are further described elsewhere herein. UFT module 10516 comprises a MOSFET switch 10518 in the example embodiment of
An input RF signal 10540 is input through impedance match 10502 to be received by a first terminal 10550 of UFD module 10506. First terminal 10550 of UFD module 10506 is coupled to a first terminal 10552 of tank circuit 10504. MOSFET switch 10518 in UFD module 10506 down-converts input RF signal 10540 according to a control signal 10548, which is output by control signal generator 10526. The output of MOSFET switch 10518 is stored in storage module 10520. MOSFET switch 10518 outputs an output signal 10542. In the example embodiment of
Control signal generator 10526 generates control signal 10548, as described elsewhere herein. Control signal 10548 preferably comprises a periodic signal, which preferably comprises a string of pulses. These pulses vary between a minimum and maximum voltage. For example, control signal 10548 may output pulses that vary between 0 volts and 2 volts, as shown in
Input RF signal 10540 also comprises a range of signal values. For instance, input RF signal 10540 may vary between +0.75 volts and −0.75 volts, as shown in FIG. 106B. In the current example, when the value of input RF signal 10540 is equal to −0.75 volts, this value is less than the minimum voltage of control signal 10548 (0 volts) applied to MOSFET switch 10518, and hence MOSFET switch 10518 will be in the closed state for all values of control signal 10548 because the voltage from terminal 10568 (gate) to terminal 10564 of MOSFET switch 10518 is always positive, causing MOSFET switch 10518 to always conduct.
Likewise, it will be recognized by persons skilled in the relevant art(s) that input RF signal 10540 may comprise signal amplitudes greater than the maximum voltage of control signal 10548 (not illustrated in
One solution is to modify the voltage swing of control signal 10548 such that it varies from +0.75 to −0.75 volts or greater, as does input RF signal 10540. This solution may not be possible in all situations, however. For instance, this solution may not be possible when only a single voltage supply is available.
A further solution for this problem is to bias input RF signal 10540 such that it varies within the maximum and minimum voltage range of pulses of control signal 10548. Thus, as long as input RF signal 10540 varies within the voltage range of control signal 10548, control signal 10548 will control the turning on and turning off of MOSFET switch 10518.
Bias circuit 10508 is used to adjust the bias applied to input RF signal 10540. (It is noted that other bias configurations could alternatively be used.) Bias circuit 10508 comprises a second voltage reference 10528, a first resistor 10530, an optional capacitor 10532, a third voltage reference 10534, a second resistor 10536, and a fourth voltage reference 10538.
A first terminal 10554 of first resistor 10530 is coupled to a first voltage reference 10528. A second terminal 10556 of first resistor 10530 is coupled to a first terminal 10558 of second resistor 10536 to create a bias point 10546. Bias point 10546 is coupled to a second terminal 10560 of tank circuit 10504. A second terminal 10562 of second resistor 10536 is coupled to fourth voltage reference 10538.
First resistor 10530 and second resistor 10536 form a voltage divider circuit, to create bias point 10546, as would be understood by persons skilled in the relevant art(s) from the teachings herein. Bias point 10546 provides a biasing voltage for input RF signal 10540. A biased input RF signal 10544 is equal to input RF signal 10540 adjusted (e.g., added or subtracted) by the amount of voltage at bias point 10546. In a preferred embodiment, biased input RF signal 10544 may be biased at the midpoint of the voltage swing of control signal 10548. For example, biased input RF signal 10544 may be biased by bias point 10546 with a level of one volt, for a 0 volt to 2 volt varying control signal 10548.
Optional capacitor 10532 coupled between bias point 10546 and third voltage reference 10534 may be optionally inserted to aid in stabilizing bias point 10546.
Other embodiments for bias circuit 10508 will be apparent to persons skilled in the relevant art(s) from the teachings herein. For instance,
In step 11902, a bias voltage is applied to an input signal. In embodiments, the center voltage of the input signal is adjusted by application of the bias voltage. In embodiments, the input signal is coupled to a center terminal of a resistor divider circuit, which supplies the bias voltage. In an embodiment, a tank circuit is used to couple the input signal to the center terminal of the resistor divider circuit.
In step 11904, the biased input signal is frequency down-converted with a first universal frequency down-conversion module to a down-converted signal.
Other embodiments for improving dynamic range include the use of complementary FETs. Complementary FET embodiments are further described in the co-pending U.S. patent application entitled “Method and System for Down-converting Electromagnetic Signals Having Optimized Switch Structures,” Ser. No. 09/293,095. Complementary FETs also have the advantage of using control signals of opposite polarity, which tends to reduce or cancel re-radiation due to a control signal.
Other circuit embodiments for improving dynamic range include modifying control signal pulse amplitude, and/or modifying the switch, or FET, size, as would be understood by persons skilled in the relevant art(s) from the teachings herein. It should be understood that the above bias circuit examples are provided for illustrative purposes only. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.4 Example Receiver and Transmitter Embodiments for Addressing DC Offset and Re-Radiation
In this section, embodiments, according to the present invention, are provided for reducing or eliminating DC offset and/or reducing or eliminating circuit re-radiation in receivers, including I/Q modulation receivers and other modulation scheme receivers. These embodiments are described herein for purposes of illustration, and not limitation. The invention is not limited to these embodiments. Alternate embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The invention is intended and adapted to include such alternate embodiments.
7.4.1 Example I/Q Modulation Receiver Embodiments
I/Q modulation receiver 2500 comprises a first UFD module 2502, a first optional filter 2504, a second UFD module 2506, a second optional filter 2508, a third UFD module 2510, a third optional filter 2512, a fourth UFD module 2514, a fourth filter 2516, an optional LNA 2518, a first differential amplifier 2520, a second differential amplifier 2522, and an antenna 2572.
I/Q modulation receiver 2500 receives, down-converts, and demodulates a I/Q modulated RF input signal 2582 to an I baseband output signal 2584, and a Q baseband output signal 2586. I/Q modulated RF input signal comprises a first information signal and a second information signal that are I/Q modulated onto an RF carrier signal. I baseband output signal 2584 comprises the first baseband information signal. Q baseband output signal 2586 comprises the second baseband information signal.
Antenna 2572 receives I/Q modulated RF input signal 2582. I/Q modulated RF input signal 2582 is output by antenna 2572 and received by optional LNA 2518. When present, LNA 2518 amplifies I/Q modulated RF input signal 2582, and outputs amplified I/Q signal 2588.
First UFD module 2502 receives amplified I/Q signal 2588. First UFD module 2502 down-converts the I-phase signal portion of amplified input I/Q signal 2588 according to an I control signal 2590. First UFD module 2502 outputs an I output signal 2598.
In an embodiment, first UFD module 2502 comprises a first storage module 2524, a first UFT module 2526, and a first voltage reference 2528. In an embodiment, a switch contained within first UFT module 2526 opens and closes as a function of I control signal 2590. As a result of the opening and closing of this switch, which respectively couples and de-couples first storage module 2524 to and from first voltage reference 2528, a down-converted signal, referred to as I output signal 2598, results. First voltage reference 2528 may be any reference voltage, and is preferably ground. I output signal 2598 is stored by first storage module 2524.
In a preferred embodiment, first storage module 2524 comprises a first capacitor 2574. In addition to storing I output signal 2598, first capacitor 2574 reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on I output signal 2598, in a similar fashion to that of capacitor 9126 shown in
I output signal 2598 is received by optional first filter 2504. When present, first filter 2504 is a high pass filter to at least filter I output signal 2598 to remove any carrier signal “bleed through”. In a preferred embodiment, when present, first filter 2504 comprises a first resistor 2530, a first filter capacitor 2532, and a first filter voltage reference 2534. Preferably, first resistor 2530 is coupled between I output signal 2598 and a filtered I output signal 2507, and first filter capacitor 2532 is coupled between filtered I output signal 2507 and first filter voltage reference 2534. Alternately, first filter 2504 may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). First filter 2504 outputs filtered I output signal 2507.
Second UFD module 2506 receives amplified I/Q signal 2588. Second UFD module 2506 down-converts the inverted I-phase signal portion of amplified input I/Q signal 2588 according to an inverted I control signal 2592. Second UFD module 2506 outputs an inverted I output signal 2501.
In an embodiment, second UFD module 2506 comprises a second storage module 2536, a second UFT module 2538, and a second voltage reference 2540. In an embodiment, a switch contained within second UFT module 2538 opens and closes as a function of inverted I control signal 2592. As a result of the opening and closing of this switch, which respectively couples and de-couples second storage module 2536 to and from second voltage reference 2540, a down-converted signal, referred to as inverted I output signal 2501, results. Second voltage reference 2540 may be any reference voltage, and is preferably ground. Inverted I output signal 2501 is stored by second storage module 2536.
In a preferred embodiment, second storage module 2536 comprises a second capacitor 2576. In addition to storing inverted I output signal 2501, second capacitor 2576 reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on inverted I output signal 2501, in a similar fashion to that of capacitor 9126 shown in
Inverted I output signal 2501 is received by optional second filter 2508. When present, second filter 2508 is a high pass filter to at least filter inverted I output signal 2501 to remove any carrier signal “bleed through”. In a preferred embodiment, when present, second filter 2508 comprises a second resistor 2542, a second filter capacitor 2544, and a second filter voltage reference 2546. Preferably, second resistor 2542 is coupled between inverted I output signal 2501 and a filtered inverted I output signal 2509, and second filter capacitor 2544 is coupled between filtered inverted I output signal 2509 and second filter voltage reference 2546. Alternately, second filter 2508 may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). Second filter 2508 outputs filtered inverted I output signal 2509.
First differential amplifier 2520 receives filtered I output signal 2507 at its non-inverting input and receives filtered inverted I output signal 2509 at its inverting input. First differential amplifier 2520 subtracts filtered inverted I output signal 2509 from filtered I output signal 2507, amplifies the result, and outputs I baseband output signal 2584. Other suitable subtractor and/or amplification modules may be substituted for first differential amplifier 2520, and second differential amplifier 2522, as would be understood by persons skilled in the relevant art(s) from the teachings herein. Because filtered inverted I output signal 2509 is substantially equal to an inverted version of filtered I output signal 2507, I baseband output signal 2584 is substantially equal to filtered I output signal 2509, with its amplitude doubled. Furthermore, filtered I output signal 2507 and filtered inverted I output signal 2509 may comprise substantially equal noise and DC offset contributions of the same polarity from prior down-conversion circuitry, including first UFD module 2502 and second UFD module 2506, respectively. When first differential amplifier 2520 subtracts filtered inverted I output signal 2509 from filtered I output signal 2507, these noise and DC offset contributions substantially cancel each other.
Third UFD module 2510 receives amplified I/Q signal 2588. Third UFD module 2510 down-converts the Q-phase signal portion of amplified input I/Q signal 2588 according to an Q control signal 2594. Third UFD module 2510 outputs an Q output signal 2503.
In an embodiment, third UFD module 2510 comprises a third storage module 2548, a third UFT module 2550, and a third voltage reference 2552. In an embodiment, a switch contained within third UFT module 2550 opens and closes as a function of Q control signal 2594. As a result of the opening and closing of this switch, which respectively couples and de-couples third storage module 2548 to and from third voltage reference 2552, a down-converted signal, referred to as Q output signal 2503, results. Third voltage reference 2552 may be any reference voltage, and is preferably ground. Q output signal 2503 is stored by third storage module 2548.
In a preferred embodiment, third storage module 2548 comprises a third capacitor 2578. In addition to storing Q output signal 2503, third capacitor 2578 reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on Q output signal 2503, in a similar fashion to that of capacitor 9126 shown in
Q output signal 2503 is received by optional third filter 2512. When present, third filter 2512 is a high pass filter to at least filter Q output signal 2503 to remove any carrier signal “bleed through”. In a preferred embodiment, when present, third filter 2512 comprises a third resistor 2554, a third filter capacitor 2558, and a third filter voltage reference 2558. Preferably, third resistor 2554 is coupled between Q output signal 2503 and a filtered Q output signal 2511, and third filter capacitor 2556 is coupled between filtered Q output signal 2511 and third filter voltage reference 2558. Alternately, third filter 2512 may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). Third filter 2512 outputs filtered Q output signal 2511.
Fourth UFD module 2514 receives amplified I/Q signal 2588. Fourth UFD module 2514 down-converts the inverted Q-phase signal portion of amplified input I/Q signal 2588 according to an inverted Q control signal 2596. Fourth UFD module 2514 outputs an inverted Q output signal 2505.
In an embodiment, fourth UFD module 2514 comprises a fourth storage module 2560, a fourth UFT module 2562, and a fourth voltage reference 2564. In an embodiment, a switch contained within fourth UFT module 2562 opens and closes as a function of inverted Q control signal 2596. As a result of the opening and closing of this switch, which respectively couples and de-couples fourth storage module 2560 to and from fourth voltage reference 2564, a down-converted signal, referred to as inverted Q output signal 2505, results. Fourth voltage reference 2564 may be any reference voltage, and is preferably ground. Inverted Q output signal 2505 is stored by fourth storage module 2560.
In a preferred embodiment, fourth storage module 2560 comprises a fourth capacitor 2580. In addition to storing inverted Q output signal 2505, fourth capacitor 2580 reduces or prevents a DC offset voltage resulting from above described charge injection from appearing on inverted Q output signal 2505, in a similar fashion to that of capacitor 9126 shown in
Inverted Q output signal 2505 is received by optional fourth filter 2516. When present, fourth filter 2516 is a high pass filter to at least filter inverted Q output signal 2505 to remove any carrier signal “bleed through”. In a preferred embodiment, when present, fourth filter 2516 comprises a fourth resistor 2566, a fourth filter capacitor 2568, and a fourth filter voltage reference 2570. Preferably, fourth resistor 2566 is coupled between inverted Q output signal 2505 and a filtered inverted Q output signal 2513, and fourth filter capacitor 2568 is coupled between filtered inverted Q output signal 2513 and fourth filter voltage reference 2570. Alternately, fourth filter 2516 may comprise any other applicable filter configuration as would be understood by persons skilled in the relevant art(s). Fourth filter 2516 outputs filtered inverted Q output signal 2513.
Second differential amplifier 2522 receives filtered Q output signal 2511 at its non-inverting input and receives filtered inverted Q output signal 2513 at its inverting input. Second differential amplifier 2522 subtracts filtered inverted Q output signal 2513 from filtered Q output signal 2511, amplifies the result, and outputs Q baseband output signal 2586. Because filtered inverted Q output signal 2513 is substantially equal to an inverted version of filtered Q output signal 2511, Q baseband output signal 2586 is substantially equal to filtered Q output signal 2513, with its amplitude doubled. Furthermore, filtered Q output signal 2511 and filtered inverted Q output signal 2513 may comprise substantially equal noise and DC offset contributions of the same polarity from prior down-conversion circuitry, including third UFD module 2510 and fourth UFD module 2514, respectively. When second differential amplifier 2522 subtracts filtered inverted Q output signal 2513 from filtered Q output signal 2511, these noise and DC offset contributions substantially cancel each other.
In step 12002, an input signal is received, wherein the input signal comprises an RF I/Q modulated signal.
In step 12004, the input signal is frequency down-converted with a first universal frequency down-conversion module to a first down-converted signal, according to a first control signal. In an embodiment, the input signal is frequency down-converted to a non-inverted I-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a first phase of the in-phase signal portion of the RF I/Q modulated signal is under-sampled. In an embodiment, the RF I/Q modulated signal may be under-sampled every 3.0 cycles of a frequency of the RF I/Q modulated signal by the first control signal. Furthermore, in embodiments, a first DC offset voltage in the first down-converted signal is reduced by a capacitor of the first universal frequency down-conversion module.
In step 12006, the input signal is frequency down-converted with a second universal frequency down-conversion module to a second down-converted signal, according to a second control signal. In an embodiment, the input signal is frequency down-converted to an inverted I-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a second phase of the in-phase signal portion of the RF I/Q modulated signal is under-sampled, wherein the second phase of the in-phase signal portion is of an opposite phase to the first phase under-sampled of the in-phase signal portion. The RF I/Q modulated signal may be sampled 1.5 cycles of a frequency of the RF I/Q modulated signal after under-sampling the RF I/Q modulated signal in step 12004, for example. Furthermore, in embodiments, a second DC offset voltage in the second down-converted signal is reduced by a capacitor of the second universal frequency down-conversion module.
In step 12008, the second down-converted signal is subtracted from the first down-converted signal to form a first output signal. In embodiments, a first DC offset voltage in the first down-converted signal and a second DC offset voltage in the second down-converted signal cancel one another.
In step 12010, the input signal is frequency down-converted with a third universal frequency down-conversion module to a third down-converted signal, according to a third control signal. In an embodiment, the input signal is frequency down-converted to a non-inverted Q-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a third phase of the quadrature-phase signal portion of the RF I/Q modulated signal is under-sampled. The RF I/Q modulated signal may be under-sampled 0.75 cycles of the frequency of the RF I/Q modulated signal after under-sampling of the RF I/Q modulated signal occurs in step 12004, for example. Furthermore, in embodiments, a third DC offset voltage in the third down-converted signal is reduced by a capacitor of the third universal frequency down-conversion module.
In step 12012, the input signal is frequency down-converted with a fourth universal frequency down-conversion module to a fourth down-converted signal, according to a fourth control signal. In an embodiment, the input signal is frequency down-converted to an inverted Q-phase signal portion of the RF I/Q modulated signal. For instance, in an embodiment, a fourth phase of the quadrature-phase signal portion of the RF I/Q modulated signal is under-sampled, wherein the fourth phase of the quadrature-phase signal portion is of an opposite phase to the third phase under-sampled of the quadrature-phase signal portion. In an embodiment, the RF I/Q modulated signal may be sampled 1.5 cycles of the frequency of the RF I/Q modulated signal after under-sampling of the RF I/Q modulated signal occurs in step 12010, for example. Furthermore, in embodiments, a fourth DC offset voltage in the fourth down-converted signal is reduced by a capacitor of fourth universal frequency down-conversion module.
In step 12014, the fourth down-converted signal is subtracted from the third down-converted signal to form a second output signal. In embodiments, a third DC offset voltage in the third down-converted signal and a fourth DC offset voltage in the fourth down-converted signal cancel one another.
In step 12016, a signal is re-radiated that comprises attenuated components of first, second, third, and fourth control signal pulses, wherein the attenuated components of the first, second, third, and fourth control signal pulses form a cumulative frequency, as discussed above.
In step 12018, the first, second, third, and fourth control signal pulses are configured such that the cumulative frequency is greater than a frequency of the input signal, as discussed above.
7.4.1.1 Example I/Q Modulation Control Signal Generator Embodiments
I/Q modulation control signal generator 2600 comprises a local oscillator 2602, a first divide-by-two module 2604, a 180 degree phase shifter 2606, a second divide-by-two module 2608, a first pulse generator 2610, a second pulse generator 2612, a third pulse generator 2614, and a fourth pulse generator 2616.
Local oscillator 2602 outputs an oscillating signal 2618.
First divide-by-two module 2604 receives oscillating signal 2618, divides oscillating signal 2618 by two, and outputs a half frequency LO signal 2620 and a half frequency inverted LO signal 2626.
180 degree phase shifter 2606 receives oscillating signal 2618, shifts the phase of oscillating signal 2618 by 180 degrees, and outputs phase-shifted LO signal 2622. 180 degree phase shifter 2606 may be implemented in circuit logic, hardware, software, or any combination thereof, as would be known by persons skilled in the relevant art(s). In alternative embodiments, other amounts of phase shift may be used.
Second divide-by two module 2608 receives phase-shifted LO signal 2622, divides phase-shifted LO signal 2622 by two, and outputs a half frequency phase-shifted LO signal 2624 and a half frequency inverted phase-shifted LO signal 2628.
First pulse generator 2610 receives half frequency LO signal 2620, generates an output pulse whenever a rising edge is received on half frequency LO signal 2620, and outputs I control signal 2590.
Second pulse generator 2612 receives half frequency inverted LO signal 2626, generates an output pulse whenever a rising edge is received on half frequency inverted LO signal 2626, and outputs inverted I control signal 2592.
Third pulse generator 2614 receives half frequency phase-shifted LO signal 2624, generates an output pulse whenever a rising edge is received on half frequency phase-shifted LO signal 2624, and outputs Q control signal 2594.
Fourth pulse generator 2616 receives half frequency inverted phase-shifted LO signal 2628, generates an output pulse whenever a rising edge is received on half frequency inverted phase-shifted LO signal 2628, and outputs inverted Q control signal 2596.
In a preferred embodiment, control signals 2590, 2592, 2594 and 2596 output pulses having a width equal to one-half of a period of I/Q modulated RF input signal 2582. The invention, however, is not limited to these pulse widths, and control signals 2590, 2592, 2594, and 2596 may comprise pulse widths of any fraction of, or multiple and fraction of, a period of I/Q modulated RF input signal 2582.
First, second, third, and fourth pulse generators 2610, 2612, 2614, and 2616 may be implemented in circuit logic, hardware, software, or any combination thereof, as would be known by persons skilled in the relevant art(s).
As shown in
For example,
As
It should be understood that the above control signal generator circuit example is provided for illustrative purposes only. The invention is not limited to these embodiments. Alternative embodiments (including equivalents, extensions, variations, deviations, etc., of the embodiments described herein) for I/Q modulation control signal generator 2600 will be apparent to persons skilled in the relevant art(s) from the teachings herein, and are within the scope of the present invention.
7.4.1.2 Detailed Example I/Q Modulation Receiver Embodiment with Exemplary Waveforms
7.4.1.3 Example Single Channel Receiver Embodiment
7.4.1.4 Alternative Example I/Q Modulation Receiver Embodiment
7.4.1.5 Example Transmitter Embodiment
I/Q modulation transmitter 4300 comprises an optional first filter 4302, a second optional filter 4306, and a third optional filter 4310. When present, second and third optional filters 4306 and 4310 may comprise first and second resistors 4334 and 4336, respectively. In alternative embodiments, second and third optional filters 4306 and 4310 may comprise inductors, capacitors, and/or other filtering elements, alone or in combination.
8. Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
This application is a continuation of U.S. patent application Ser. No. 12/419,465, filed Apr. 7, 2009, now allowed, which is a continuation of U.S. application Ser. No. 11/059,536, filed Feb. 17, 2005, now U.S. Pat. No. 7,539,474, which is a continuation of U.S. application Ser. No. 09/526,041, filed Mar. 14, 2000, now U.S. Pat. No. 6,879,817, which claims the benefit of U.S. Provisional Application No. 60/171,502, filed Dec. 22, 1999; U.S. Provisional Application No. 60/177,705, filed on Jan. 24, 2000; U.S. Provisional Application No. 60/129,839, filed on Apr. 16, 1999; U.S. Provisional Application No. 60/158,047, filed on Oct. 7, 1999; U.S. Provisional Application No. 60/171,349, filed on Dec. 21, 1999; U.S. Provisional Application No. 60/177,702, filed on Jan. 24, 2000; U.S. Provisional Application No. 60/180,667, filed on Feb. 7, 2000; and U.S. Provisional Application No. 60/171,496, filed on Dec. 22, 1999, all of which are incorporated by reference herein in their entireties. The following applications of common assignee are related to the present application, and are herein incorporated by reference in their entireties: “Method and System for Down-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filed Oct. 21, 1998. “Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998. “Method and System for Ensuring Reception of a Communications Signal,” Ser. No. 09/176,415, filed Oct. 21, 1998. “Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998. “Applications of Universal Frequency Translation,” Ser. No. 09/261,129, filed Mar. 3, 1999. “Method and System for Down-Converting Electromagnetic Signals Having Optimized Switch Structures,” Ser. No. 09/293,095, filed Apr. 16, 1999. “Method and System for Down-Converting Electromagnetic Signals Including Resonant Structures for Enhanced Energy Transfer,” Ser. No. 09/293,342, filed Apr. 16, 1999. “Method and System for Frequency Up-Conversion with a Variety of Transmitter Configurations,” Ser. No. 09/293,580, filed Apr. 16, 1999. “Integrated Frequency Translation and Selectivity with a Variety of Filter Embodiments,” Ser. No. 09/293,283, filed Apr. 16, 1999. “Matched Filter Characterization and Implementation of Universal Frequency Translation Method and Apparatus,” Ser. No. 09/521,878, filed Mar. 9, 2000.
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| Number | Date | Country | |
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