Claims
- 1. A memory device comprising:
- an array of individual, randomly accessed memory cells operatively arranged in rows and columns, said columns operationally divided into a multiplicity of data blocks,
- a static column buffer operationally divided into a multiplicity of buffer blocks, one each of said multiplicity of data blocks associated with one each of said multiplicity of buffer blocks wherein during a data transfer cycle each of said multiplicity of data blocks is coupled to said corresponding buffer block but only one of said multiplicity of data blocks is latched into said corresponding buffer block; and
- means for exclusively outputting said one latched buffer block of said static column buffer.
- 2. The memory device of claim 1 wherein:
- the memory device is a static column decode dynamic random access memory.
- 3. The memory device of claim 1 wherein:
- the static buffer comprises a row of static random access memory cells.
- 4. The memory device of claim 1 wherein:
- the buffer further comprises a single operative line of n memory cells, n equals the number of columns of the array, and divided into s sections, s is greater than 1.
- 5. The memory array of claim 5 wherein:
- s equals four and each section contains n/4 memory cells.
- 6. The memory array of claim 5 wherein:
- s equals eight and each section contains n/8 memory cells.
- 7. A memory device comprising:
- an array of individual memory cells operatively arranged in (n) rows and (m) columns, each of said columns operationally divided into a multiplicity of data blocks;
- a static column buffer having at least (m) locations coupled to said array for receiving (m) data signals from a row of memory cells of said array, said buffer being operationally divided into a multiplicity of buffer blocks each associated with one of said data blocks;
- a demultiplexer control circuit for decoding a block address and exclusively gating said data from said memory cells into one said buffer block; and
- means for outputting the data from said exclusively gated block.
Parent Case Info
This application is a continuation of application Ser. No. 07/639,309, filed Jan. 7, 1991 now abandonded which is a continuation of application Ser. No. 07/175,875 filed Mar. 31, 1988 now abandoned.
US Referenced Citations (11)
Non-Patent Literature Citations (2)
Entry |
Smith, "Cache Memory Design: An Evolving Art," Spectrum vol. 24, No. 12 (IEEE, 1987), pp. 40-44. |
Ward, S. and Zak, R., "Static-column RAM as Virtual Cache", Laboratory for Computer Science, MIT, Cambridge, Mass. |
Continuations (2)
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Number |
Date |
Country |
Parent |
639309 |
Jan 1991 |
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Parent |
175875 |
Mar 1988 |
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