Data input circuits

Industry

CPC
G11C7/1078

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1078Data input circuits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sense amplifier with read circuit for compute-in-memory
- Patent number 12,322,435
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chieh Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock mode determination in a memory system
- Patent number 12,321,600
- Issue date Jun 3, 2025
- Mosaid Technologies Incorporated
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conflict detection and address arbitration for routing scatter and...
- Patent number 12,314,572
- Issue date May 27, 2025
- Synopsys, Inc.
- Karthik Thucanakkenpalayam Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller operable in data loop-back mode
- Patent number 12,314,113
- Issue date May 27, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit, signal transmission system and signal transmission...
- Patent number 12,283,302
- Issue date Apr 22, 2025
- NANYA TECHNOLOGY CORPORATION
- Shun-Ke Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and ZQ calibration method
- Patent number 12,277,992
- Issue date Apr 15, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kai Tian
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die termination configuration for integrated circuit
- Patent number 12,254,954
- Issue date Mar 18, 2025
- Yangtze Memory Technologies Co., Ltd.
- Debo Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiving circuit, data receiving system and memory device
- Patent number 12,237,042
- Issue date Feb 25, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for receiving strobe signal
- Patent number 12,231,100
- Issue date Feb 18, 2025
- Electronics and Telecommunications Research Institute
- Yi-Gyeong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods employing asynchronous FIFO buffer with read...
- Patent number 12,176,064
- Issue date Dec 24, 2024
- Advanced Micro Devices, Inc.
- Richard Martin Born
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory computing method and in-memory computing apparatus
- Patent number 12,169,702
- Issue date Dec 17, 2024
- Macronix International Co., Ltd.
- Bo-Rong Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory system using standard controller component
- Patent number 12,148,462
- Issue date Nov 19, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calibrating write timing in a memory system
- Patent number 12,136,452
- Issue date Nov 5, 2024
- RAMBUS INC.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power source-synchronous signaling
- Patent number 12,119,042
- Issue date Oct 15, 2024
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock synchronizing method of a multiple clock domain memory device
- Patent number 12,057,193
- Issue date Aug 6, 2024
- Samsung Electronics Co., Ltd.
- Hye-Ran Kim
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CIRCUIT, SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION...
- Publication number 20250218484
- Publication date Jul 3, 2025
- NANYA TECHNOLOGY CORPORATION
- Shun-Ke WU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATION METHOD THEREOF
- Publication number 20250191624
- Publication date Jun 12, 2025
- Yangtze Memory Technologies Co., Ltd.
- Debo Wei
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
- Publication number 20250111873
- Publication date Apr 3, 2025
- Rambus Inc.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT
- Publication number 20250087261
- Publication date Mar 13, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20250069644
- Publication date Feb 27, 2025
- Rambus Inc.
- Jared L. ZERBE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS
- Publication number 20240355378
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Akira Yamashita
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD FOR PERFORMING MATRIX OPERATION
- Publication number 20240304230
- Publication date Sep 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Lien Linus LU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR STORING PLURALITY OF DATA BITS AND METHOD OF OPER...
- Publication number 20240304225
- Publication date Sep 12, 2024
- SK HYNIX INC.
- Tae Hun PARK
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ/WRITE SWITCHING CIRCUIT AND MEMORY
- Publication number 20240256174
- Publication date Aug 1, 2024
- Changxin Memory Technologies, Inc.
- WeiBing SHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND OPERATION METHOD THEREOF
- Publication number 20240232012
- Publication date Jul 11, 2024
- Samsung Electronics Co., Ltd.
- Seongmuk KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DI...
- Publication number 20240203464
- Publication date Jun 20, 2024
- Lodestar Licensing Group LLC
- Matthew A. Prather
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ADVERTISEMENT TRANSMISSION AND DISPLAY
- Publication number 20240169395
- Publication date May 23, 2024
- STRATOSAUDIO, INC.
- Kelly M. Christensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
- Publication number 20240168636
- Publication date May 23, 2024
- MOSAID TECHNOLOGIES INCORPORATED
- Peter B. GILLINGHAM
- G06 - COMPUTING CALCULATING COUNTING

Data input circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus to facilitate atomic operations in victim cache

Sense amplifier with read circuit for compute-in-memory

Clock mode determination in a memory system

Victim cache with write miss merging

Conflict detection and address arbitration for routing scatter and...

Memory controller operable in data loop-back mode

Write merging on stores with different privilege levels

Memory circuit, signal transmission system and signal transmission...

Memory device and ZQ calibration method

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

On-die termination configuration for integrated circuit

Data receiving circuit, data receiving system and memory device

Apparatus and method for receiving strobe signal

Atomic compare and swap in a coherent cache system

Aggressive write flush scheme for a victim cache

Methods and apparatus to reduce bank pressure using aggressive writ...

Fully pipelined read-modify-write support

Methods and apparatus for allocation in a victim cache system

Apparatus and methods employing asynchronous FIFO buffer with read...

In-memory computing method and in-memory computing apparatus

Methods and apparatus for read-modify-write support in multi-banked...

High capacity memory system using standard controller component

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Method and apparatus for calibrating write timing in a memory system

Low-power source-synchronous signaling

Methods and apparatus for eviction in dual datapath victim cache sy...

Methods and apparatus to facilitate read-modify-write support in a...

Clock synchronizing method of a multiple clock domain memory device

Patents Applicationslast 30 patents

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

MEMORY CIRCUIT, SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION...

MEMORY DEVICE AND OPERATION METHOD THEREOF

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS

DEVICE AND METHOD FOR PERFORMING MATRIX OPERATION

MEMORY DEVICE FOR STORING PLURALITY OF DATA BITS AND METHOD OF OPER...

VICTIM CACHE WITH WRITE MISS MERGING

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

READ/WRITE SWITCHING CIRCUIT AND MEMORY

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

MEMORY DEVICE AND OPERATION METHOD THEREOF

METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DI...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

SYSTEM AND METHOD FOR ADVERTISEMENT TRANSMISSION AND DISPLAY

CLOCK MODE DETERMINATION IN A MEMORY SYSTEM