Claims
- 1. A semiconductor device including a memory cell region having a plurality of memory cells and a peripheral circuit for writing/reading prescribed memory information to and from the memory cell region, on a main surface of a semiconductor substrate having a bottom surface comprising:
- a transistor for each memory cell including a pair of first impurity regions formed in said semiconductor substrate and a first gate electrode formed on the semiconductor substrate between said pair of first impurity regions;
- a transistor for the peripheral circuit including a pair of second impurity regions formed in said semiconductor substrate and a second gate electrode formed on said semiconductor substrate between said pair of second impurity regions;
- a first conductive layer connected to one of said first impurity regions of said transistor for the memory cell;
- a second conductive layer separate and distinct from said first conductive layer connected to the other one of said first impurity regions of said transistor for the memory cell;
- a first contact pad layer connected to one of said second impurity regions of said transistor for the peripheral circuit; and
- a second contact pad layer separate and distinct from said first contact pad layer connected to the other one of said second impurity regions of said transistor for the peripheral circuit, wherein a portion of said second contact pad layer extends in a direction substantially parallel to said bottom surface of said semiconductor substrate at a level higher than said entire first contact pad layer.
- 2. A semiconductor device comprising:
- a semiconductor substrate having a main surface and a bottom surface,
- a memory cell region on the main surface of a semiconductor substrate including a plurality of memory cells,
- a peripheral circuit region on the main surface of said semiconductor substrate adjacent to said memory cell region, including a peripheral circuit for reading and writing memory information to and from memory cells in the memory cell region,
- an interlayer insulating layer having a relatively flat upper surface formed on both said peripheral circuit region and said memory cell region, wherein the height of said entire interlayer insulating layer with respect to the bottom of the substrate above said memory cell region is essentially the same as the height above said peripheral circuit region, wherein the surfaces of the semiconductor substrate having the memory cell region and the peripheral circuit region are substantially in the same plane.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-115642 |
May 1990 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 08/456,331 filed Jun. 1, 1995, now U.S. Pat. No. 5,659,191 which is a continuation of application Ser. No. 08/232,315 filed Apr. 25, 1994, now U.S. Pat. No. 5,486,712 which is a continuation of application Ser. No. 07/690,843 filed Apr. 24, 1991 abandoned.
US Referenced Citations (11)
Foreign Referenced Citations (9)
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Country |
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EPX |
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Oct 1991 |
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Oct 1991 |
DEX |
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JPX |
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JPX |
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Mar 1990 |
JPX |
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Non-Patent Literature Citations (2)
Entry |
Kaga et al., "A Crown Type Stacked Capacitor Cell for a 1.5V Operation 64 DRAM", Proceedings of 37th Applied Physics Association Conference, 2nd Vol., p. 582, no date. |
Wakamiya et al., "Novel Stacked Capacitor Cell for 64Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70, no month. |
Divisions (1)
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Number |
Date |
Country |
Parent |
456331 |
Jun 1995 |
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Continuations (2)
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Number |
Date |
Country |
Parent |
232315 |
Apr 1994 |
|
Parent |
690843 |
Apr 1991 |
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