Patent Application
20090224139
The demodulation of modulated light signals at the pixel level requires the switching of a photo-generated charge. While it is possible to use either photo-generated electrons or holes, typical solutions use photo-generated electrons because of their higher mobility in the semiconductor material. Some pixel architectures do the necessary signal processing based on the photo-current whereas other architectures work in the charge domain directly.
Common to all pixels is the necessity to transfer charges through the photo-sensitive detection region to a subsequent storage area and/or to a subsequent processing unit. In the case of charge-domain based pixel architectures, the photo-charges are generally transferred to a storage or integration node. In order to demodulate an optical signal, the pixel has to have at least one integration node that can be controlled to accumulate the photo-generated charges during certain time intervals, typically synchronously with a modulated illumination signal.
Different pixel concepts have been realized in the last few decades. Many use a demodulation pixel, which transfers the photo-generated charge below a certain number of adjacent poly-silicon gates to discrete accumulation capacitances. Spirig, “Apparatus and method for detection of an intensity-modulated radiation field”, Jan. 5, 1999, U.S. Pat. No. 5,856,667 disclosed a charge coupled device (CCD) lock-in concept that allows the in-pixel sampling of the impinging light signal with theoretically an arbitrary number of samples. Another very similar pixel concept has been demonstrated by T. Ushinaga et al., “A QVGA-size CMOS time-of-flight range image sensor with background light charge draining structure”, Three-dimensional image capture and applications VII, Proceedings of SPIE, Vol. 6056, pp. 34-41, 2006, where a thick field-oxide layer is used to smear the potential distribution below the demodulation gates.
A common problem of the afore-mentioned pixel approaches is the slowness of the charge transport through the semiconductor material, which undermines significantly the quality of the in-pixel demodulation process. In all pixel structures, the limiting transport speed is the step-shaped potential distribution in the semiconductor substrate. Ideally, the potential distribution decreases linearly in lateral direction giving rise to the lateral electric fields that are preferably used to transport the charges through the semiconductor in direction to the different storage sites. Step-shaped potential distributions created by gate structures have regions with flat lateral potential distribution, where slow thermal diffusion processes dominate the transport speed instead of the lateral electric drift fields.
New pixel designs have been explored in recent years that are intended to accelerate the in-pixel transport of the charges by exploiting lateral electric drift fields. Seitz, “Four-tap demodulation pixel”, filed on Jun. 20, 2002, GB 2 389 960 A, invented the first drift field demodulation device for photo detection purposes. It is based on a very high-resistive photo-transparent poly-silicon gate electrode. It even allows the design of pixels having an arbitrary number of n samples. The static drift field pixel disclosed by Büttgen, “Device and method for the demodulation of modulated electromagnetic wave fields”, European Patent Application, Publication date: Feb. 8, 2006, EP1777747A1—in contrast to the architectures mentioned before—clearly separates the detection and the demodulation regions within the pixel. It shows lower power consumption compared to the drift field demodulation approach of Seitz and, at the same time, supports fast in-pixel lateral charge transport. Another pixel concept was proven by D. van Nieuwenhove et al., Novel Standard CMOS Detector using Majority Current for guiding Photo-Generated Electrons towards Detecting Junctions”, Proceedings Symposium IEEE/LEOS Benelux Chapter, 2005. In this pixel architecture the lateral electric drift field is generated by the current of majority carriers within the semiconductor substrate. Minority carriers are generated by the photons and transported to the particular side of the pixel just depending on the applied drift field.
One major application of demodulation pixels is found in real-time 3-D imaging. By demodulating the optical signal and applying the discrete Fourier analysis on the acquired samples, parameters such as amplitude and phase can be extracted for the frequencies of interest. If the optical signal is sinusoidally modulated, capturing at least three discrete samples enables the extraction of the offset, amplitude and phase information. In a time-of-flight 3D imaging system, the phase value corresponds proportionally to the sought distance value. Such a harmonic modulation scheme is often used in real-time 3-D imaging systems incorporating the demodulation pixels.
The precision of the pixel-wise distance measurement is determined by the in-pixel transfer time needed for the electrons to pass from the photosensitive region in which they are generated to the area where they are accumulated or post-processed The ability of the pixel to sample at high modulation frequencies is determined by the transit time and is of high importance to perform distance measurements with high accuracy. The achievable measurement accuracy is directly inversely proportional to the modulation frequency.
Each of the three major concepts of drift field pixels has its particular drawbacks restricting the 3-D imaging applications.
The drift field demodulation pixel generates the lateral drift field by a constant electronic current through the poly-silicon gate. In order to reduce the power consumption, the gate is suggested to be as resistive as possible. However, the creation of sensors with large pixel counts is not possible without increasing the sensor's power consumption. The high in-pixel power consumption has also a negative impact on the thermal heating of the sensor and hence, on its dark current noise.
The drift field pixel of Nieuwenhoven generates the drift field in the substrate by the current flow of majority carriers. One major problem of this pixel concept is the self-heating of the pixel and the associated dark current noise. Furthermore, the quantum efficiency suffers from the fact that the same semiconductor region is used to create the drift field by a current of majority carriers and to separate the minority carriers. High recombination rates are the result, which reduces the optical sensitivity.
The static drift field pixel requires the creation of a large region having a lateral electric drift field that moves the charges in the direction of the demodulation region. The drift region is currently implemented as a successive, overlapping CCD gate structures. Each gate has a minimum width and the gate voltages are linearly increasing in the direction of the demodulation region. The voltages applied to the gates are all constant meaning that the lateral electric drift field is also constant. The main drawback is the complex layout, in particular the connection of the large number of gates to the constant voltages. Even more dramatically, if a pure CCD process is used, the routing rules are more restricting than in a complimentary metal oxide semiconductor (CMOS) process with CCD option generally making such a design more impractical.
Another drawback of the static drift field pixel layout is the high number of overlaps between poly-silicon gates leading to optical interference and, hence, to a reduced quantum efficiency strongly depending on the wavelength. Furthermore, the gate structure is not perfectly suited to create perfectly linear potential distributions, which undermines the charge transport speed in the lateral direction.
In order to overcome the complex pixel design, to reduce the necessary number of gates in the detection region, to reduce the power consumption and to increase the optical sensitivity, the following pixel implementation with a pinned-photo diode architecture is proposed for high-speed charge transfer and 3-D imaging applications. The pinned photodiode architecture means the possibility to implant p on n on p. Thus, standard CMOS processes that provide such an implantation set-up are preferably used. In general, CCD processes do not offer this feature of pinned photodiodes.
In general, according to one aspect, the invention features a pixel for an optical sensor, comprising: at least one sense node for receiving photo-generated charges and a pinned photodiode structure for creating a lateral drift field for transferring the photo-generated charges created in a photosensitive region to the at least two sense nodes.
In general, according to another aspect, the invention features a 3-D imaging system comprising a modulated light source of illuminating a scene with modulated light and an imaging sensor for detecting the modulated light from the scene. The imaging sensor comprises a two-dimensional array of pixels, the pixels each including at least one sense node for receiving photo-generated charges generated by the detected modulated light and a pinned photodiode structure for creating a lateral drift field for transferring the photo-generated charges created in a photosensitive region to the at least two sense nodes synchronously with a modulation of the modulated light.
The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.
In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:
In the following descriptions, we use just p doped substrates in order to keep the descriptions clear and well-structured. However, the devices are not limited to p-doped substrates. In the case that n-doped material is used as substrate, all doping concentrations and considerations of the potential distributions are reversed, which, however, does not mean that any functioning of the device would be restricted.
In the case that two different voltages are applied to the left (low potential) contact 118 and right (high potential) contact 120 to the n-well layer of the PPD structure 110, a constantly increasing potential is created moving from left to right, in the figure. This lateral electric field is used to transport photo-generated charges created in a photosensitive region 122 to the right side or in the direction of the high potential contact 120. These charges are generated by incoming light 50 in the PPD structure 110.
In order to avoid direct charge drain by the high-voltage contact 120, this contact needs to be replaced by an insulated gate, such as a poly-silicon gate.
Specifically, an insulating layer 124 is deposited over the substrate 114. In the preferred embodiment, the insulating layer is silicon dioxide. The insulating layer separates the low potential contact 118 and the high potential contact 120 from the substrate so they are electrically insulated from the substrate 114 to create the insulated gate structures.
The use of the poly-silicon gate structures means that the voltage at the silicon-insulator interface is created by the capacitive coupling between the contacts/gates 118, 120 and the substrate 114, similar to the principle in charge coupled devices (CCDs).
Three advantages of this drift field region are highlighted below, all due to the fact that no gates are needed in the photosensitive region 122:
1. The layout is less complicated. The number of necessary contacts is smaller and the routing does not have to be accomplished for a few tens of gate signals.
2. The quantum efficiency is higher than it is for a CCD-gate based structure. The quantum efficiency curve exhibits less fluctuations because there are less interferences between overlapping gates.
3. The structure is suited to generate perfect linearized potential distributions in the semiconductor material without increasing the in-pixel routing effort.
Demodulation Pixel DP Designs
Below, examples of two different demodulation devices are described based on the PPD. The first one is based on modulated drift fields and the second one on static drift fields.
Modulated Drift Field
On both sides of the pixel DP, the photo-generated charge are first stored or integrated below the respective integration gates 134/136. Each integration gate 134/136 is decoupled from a corresponding diffusion sense node 140/142 by an additional out gate 135/137. The integration gates 134/136 and out gates 135/137 structure, however, is optional meaning that the charge can be directly stored in the diffusion nodes 140/142 in some implementations.
Preferably, an n-implant 144/146 is formed below each of the integration gates 134/136 and out gates 135/137.
Also, in a preferred embodiment, a charge transfer channel 152 is provided that is shifted from the substrate-insulator interface 150 downwards into the substrate 114 to form a so-called buried channel. The buried channel provides higher charge transfer efficiency and less trapping noise.
Typically, amplifiers 155/156 inside the pixel DP are used to read out of the photo-generated charge. Usually, standard source followers are used in imaging devices in order to save space for the photo-sensitive region.
Static Drift Field with Subsequent Demodulation Region
The static drift field demodulation pixel DP includes two parts, the drift field section 210 and a demodulation section 220 for post-processing, memory and/or readout.
In the preferred embodiment of
The demodulation section 220 comprises a middle gate 222, two toggle gates 224/226 to the left and right side of the middle gate 222. By applying changing voltages to the two toggle gates 224/226, charges are can alternately be moved either to a left side integration gate 230 or a right side integration gate 234. Each of the left side integration gate 230 or right side integration gate 234 has a corresponding out gate, out gate 228 and out gate 236, respectively, that control the movement of the photo-generated charges from the left side integration gate 230 or the right side integration gate 234 to the left side diffusion sense node 240 or right side diffusion sense node 242, respectively
A new drift field pixel is disclosed, which is based on the fundamental structure of a pinned-photodiode. With regard to functionally comparable CCD or CMOS devices, the main advantages are:
High photo-sensitivity
Independence of the photo-sensitivity on wide ranges of the optical wavelength
Simplified layout
Perfect linear lateral drift fields
The device is suited to be manufactured in standard CMOS processes of even smallest feature sizes. In particular, 3-D imaging applications, described below, can be realized with that device because the perfect linearity of the drift fields leads to best-achievable demodulation performances.
3D-Measurement Camera System Using the Pixels
Modulated illumination light ML1 from an illumination module or light source IM is sent to the object OB of a scene. A fraction of the total optical power sent out is reflected to the camera 10 and detected by the 3D imaging sensor SN. The sensor SN comprises a two dimensional pixel matrix of the demodulation pixels DP. Each pixel DP is capable of demodulating the impinging light signal as described above. A control board CB regulates the timing of the camera 10. The phase values of all pixels correspond to the particular distance information of the corresponding point in the scene. The two-dimension gray scale image with the distance information is converted into a three-dimensional image by image processor IP. This can be displayed to a user via display D or used as a machine vision input.
The distance R for each pixel is calculated by
R=(c*TOF)/2,
with c as light velocity and TOF corresponding to the time-of-flight. Either pulse intensity-modulated or continuously intensity-modulated light is sent out by the illumination module or light source IM, reflected by the object and detected by the sensor. With each pixel of the sensor being capable of demodulating the optical signal at the same time, the sensor is able to deliver 3D images in real-time, i.e., frame rates of up to 30 Hertz (Hz), or even more, are possible. In pulse operation the demodulation would deliver the time-of-flight directly. However, continuous sine modulation delivers the phase delay (P) between the emitted signal and the received signal, also corresponding directly to the distance R:
R=(P*c)/(4*pi*fmod),
where fmod is the modulation frequency of the optical signal.
In
By activating the PPD structures and demodulation sections, alternately the photogenerated charge injected into the demodulation section is transferred to the specific storage site or integration gate. The alternation of the PPD structures as described with respect to
The electronic timing circuit, employing for example a field programmable gate array (FPGA), generates the signals for the synchronous channel activation in the demodulation stage. During the activation of one conduction channel, injected charge carriers are moved to the corresponding integration gate. As example, only two conduction channels are implemented in the demodulation region. Assuming there is no background light BG (i.e., A=BG), then two samples A0 and A1 of the modulation signal sampled at times that differ by half of the modulation period, allow the calculation of the phase P and the amplitude A of a sinusoidal intensity modulated current injected into the sampling stage. The equations look as follows:
A=(A0+A1)/2
P=arcsin [(A0−A1)/(A0+A1)].
Extending the example to four conduction channels and sample values requires in practice a different gate structure of the demodulation region with four contacts and four integration regions and an appropriate clocking scheme for the electrode voltages in order to obtain four sample values A0, A1, A2 and A3 of the injected current. Generally the samples are the result of the integration of injected charge carriers over many quarters of the modulation period, whereby finally each sample corresponds to a multiple of one quarter of the modulation period. The phase shift between two subsequent samples is 90 degree.
Instead of implementing the four channels, one can also use two channels only, but adding a second measurement with the light source delayed by 90 degrees in order to get again the four samples.
Using these four samples, the three decisive modulation parameters amplitude A, offset B and phase shift P of the modulation signal can be extracted by the equations
A=sqrt[(A3−A1)̂2+(A2−A1)̂2]/2
B=[A0+A1+A2+A3]/4
P=arctan [(A3−A1)/(A0−A2)]
While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.
This application claims the benefit under 35 USC 119(e) of U.S. Provisional Application No. 61/033,501, filed on Mar. 4, 2008, which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61033501 | Mar 2008 | US |
