Drive method for plasma display panel and plasma display device

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a drive method for a plasma display panel, and a plasma display device used for a flat type television set and an information display, and specifically relates to a drive method for a plasma display panel, and a plasma display device for preventing a reversal of luminance when a total sustain cycle number decreases.

[0003] 2. Description of the Related Art

[0004] A plasma display panel (PDP) is provided with a plurality of scan electrodes, and sustain electrodes extending in the horizontal direction, and a plurality of data electrodes extending in the vertical direction. Display cells are provided at individual intersections between the scan and sustain electrodes, and the data electrodes. In this specification, the vertical direction and the horizontal direction mean a vertical direction and a horizontal direction when the plasma display device is used while it is hanged on a wall, and respectively correspond to a column direction and a row direction in a drawing. FIG. 1 shows a schematic drawing showing a relationship among electrodes for the plasma display panel.

[0005] A number (a) of scan electrodes Sc1 to Sca, and a number (a) of sustain electrodes Su1 to Sua extending in the horizontal direction are provided alternately, and data electrodes D1 to Db extending in the vertical direction are provided in orthogonal to the scan electrodes and the sustain electrodes in the plasma display panel as shown in FIG. 1. Generally, the scan electrodes and the sustain electrodes are provided on a front substrate (not shown), and the data electrodes are provided on a rear substrate (not shown). A discharge space is formed between the front substrate and the rear substrate. The sustain electrodes Su1 to Sua may be connected together. One display cell 101 is placed at each of intersections between the scan and sustain electrode, and the data electrode. Therefore, when (a) of the scan electrodes, (a) of the sustain electrodes, and (b) of the data electrodes are provided in the plasma display, there exist total of (axb) of the display cells 101. For three display cells 101 successive in the horizontal direction, any one of them emits red light (R), any one of them emits green light (G), and any one of them emits blue light (B). These three display cells constitute one pixel.

[0006] A gradation expression method called as a subfield method is generally adopted in a plasma display panel. In the subfield method, one field (one frame) is divided into a plurality of subfields having different weights, and the gradation is determined by which subfields are selected. The subfield comprises a preliminary discharge period (a priming period), a write period (an address period), a sustain period, and an erase period in many drive methods.

[0007] There is a control method called as PLE (Peak Luminance Enhancement). The PLE controls a sustain cycle number (a sustain pulse number) for the individual subfields for every frame according to an average peak level (APL), and reduces a power consumption while increasing peak luminance. For example, the average peak level is large for an image display of a snow-covered mountain, and is small for an image display of a night sky. For the image of the snow-covered mountain, there is no large effect on the human vision when background luminance is slightly large. On the other hand, for the image of the night sky, because most of the display area may have background luminance itself, when the background luminance is high, the contrast largely decreases compared with the case of the snow-covered mountain. Thus, the sustain cycle number per field is decreased when the average peak level is high, and the sustain cycle number per field is increased when the average peak level is low in the PLE control.

[0008] A drive method is disclosed for decreasing a write period to secure a long sustain period, and to increase the luminance (Japanese Patent Laid-Open Publication No. Hei. 11-24628). FIG. 2 is a timing chart for showing a drive method similar to the drive method disclosed in the publication described above.

[0009] In the drive method disclosed in the publication, for example, one field comprises eight subfields, and all scan electrodes are scanned for the four upper level subfields having larger weights. A scan similar to interlace display is conducted for the four lower level subfields having smaller weights. Namely, the scan pulses are applied only on the odd number scan electrodes (mth (m: odd number), (m+2)th, (m+4)th, . . . ) for an odd number field (nth (n: odd number) frame), and the scan pulses are applied only on the even number scan electrodes ((m+1)th, (m+3)th, (m+5)th, . . . ) for an even number field ((n+1)th frame) as shown in FIG. 2. As a result, because the even number scan electrodes are not scanned in the odd number fields, and the odd number scan electrodes are not scanned in the even number fields, the write period is reduced accordingly, and the reduced amount of the period can be assigned for the sustain period. Also, though a line flicker may be remarkable in the interlace display, because the interlace display is limited to the lower level subfields, the influence of the line flicker is small.

[0010] However, when the average peak level is high in the PLE control, the sustain cycle number may be 1 in the plurality of lower subfields, namely in the subfields with smaller weights. Table 1 shows a relationship between the gradation level and selected subfields when the average peak level is high in the PLE control where one field comprises four subfields SF1 to SF4, and 11 gradation levels are realized.

1TABLE 1SubfieldSF1SF2SF3SF4Weight1248Cycle number1124LuminanceGradation00.84level1◯2.082◯2.083◯◯3.324◯2.965◯◯4.206◯◯4.207◯◯◯5.328◯4.689◯◯5.9210 ◯◯5.92

[0011] While Table 1 shows the eleven gradation levels, 16 gradation levels can be realized when one frame comprises four subfields.

[0012] When there are a plurality of subfields whose sustain cycle number is 1, there may be a reversal of the luminance, namely a case where a higher gradation level has lower luminance than a lower gradation level in two successive gradation levels. FIG. 3 is a chart showing a relationship between the gradation level and the luminance in Table 1. Because of the reversal of the luminance, there is a problem that a sufficient gradation expression is not realized.

[0013] When the method disclosed in Japanese Patent Laid-Open Publication No. Hei. 11-24628 is applied to the PLE control, because the sustain cycle number apparently increases, it is possible to prevent the reversal of the luminance. However, the interlace scan causes a change of an existing position of a displayed object within one filed, and the screen may momentarily become darker or brighter at a moment of a switching between a case where the write period is reduced and a case where the write period is not reduced, namely a switching between a frame where the lower four subfields are selected, and a frame where lower four subfields are not selected. As a result, the image quality degrades.

SUMMARY OF THE INVENTION

[0014] It is an object of the present invention to provide a drive method for a plasma display panel, and a plasma display device for preventing a reversal of luminance without degrading image quality when the PLE control is used.

[0015] The present invention is a method for driving a plasma display panel in which one field is constituted by a plurality of subfields, having a step of impressing a data pulse on a data electrode provided on individual display cells in one or more subfields of said plurality of subfields in association with a video signal to generate a write discharge for a gradation display on the plasma display panel. The step of impressing the data pulse comprises a step of impressing the data pulses only on the data electrodes of the predetermined display cells which is a part of all display cells without generating the write discharge in the remaining display cells in at least one subfield of said plurality of subfields.

[0016] With the present invention, the data pulse in association with the video signal is impressed on the data electrode only in the predetermined display cells in at least one subfield such as the lowest level subfields with the smallest weight of the plurality of subfields. Namely, the data pulse is not impressed at all on the data electrode in the other display cells. As a result, when the number of the predetermined display cells is a half of the total number of the display cells on the plasma display panel, the luminance of that subfield is reduced by half. If the number is one fourth of the number of the total display cells, the luminance of that subfield is reduced to one fourth. Thus, even when there are two subfields where the sustain cycle number is 1 in the PLE control and the like, if the number of the predetermined display cells is reduced to a half of the total number of the display cells in one of the subfields such as the lower level subfield, the reversal of the luminance is prevented. Also, because it is not necessary to skip impressing the scan pulse, the screen does not momentarily become darker or brighter, and an excellent image quality can be provided.

[0017] It is preferred that the at least one subfield described above be assigned with a sustain cycle number equal to that for the other subfields, and has a weight lower than those for the other subfields, and it is particularly preferred that the sustain cycle number equal to that for the other subfields be 1, and the sustain cycle number become virtually 1/N (N is an integer equal to 2 or more) in the at least one subfield.

[0018] It is preferred that the predetermined display cells constitute scan lines, the scan lines constituted by the predetermined display cells are provided at a ratio of one scan line in every N scan lines, and the data pulses are not impressed on the data electrodes on the remaining (N−1) scan lines. In this case, it is preferred that error diffusion be conducted only for data in the horizontal direction for the video signal. It is possible that the predetermined display cells constitute pixels, the pixels constituted by the predetermined display cells be provided at a ratio of one pixel in every N pixels, and the data pulses be not impressed on the data electrodes for the remaining (N−1) pixels. It is also possible that the predetermined display cells constitute blocks, the blocks constituted by the predetermined display cells are provided at a ratio of one block in every N blocks, and the data pulses are not impressed on the data electrodes for the remaining (N−1) blocks. In this case, one data driver is connected with data electrodes for the individual blocks, for example.

[0019] Further, it is possible to realize PLE control for preventing the reversal of the luminance. A plurality of total sustain cycle numbers are set in advance. And one of a total sustain cycle number is selected from the plurality of the total sustain cycle numbers in association with an average peak level of the video signal before impressing the data pulses associated with the video signal only on the data electrodes of the predetermined display cells. For example, when 32 to 10 are set in advance as the total sustain cycle numbers for 16 gradation level display (gradation level: 0 to 15), the following control is available. The PLE control is conducted such that the total sustain cycle number is 10 when the average peak level is maximum, namely when the gradation level is 15, and the total sustain cycle number is 32 when the average peak level is equal to or less than the gradation level of 5. In this way, it is possible to always restrain a power consumption for the sustain discharge to a level lower than a certain value. When the total sustain cycle number becomes from 15 to 10, using the drive method of the present invention always realizes a 16-gradation level display.

[0020] It is preferred that the predetermined display cells be changed once in every M (M is an integer equal to 2 or more) fields. It is especially preferred that the value of M be equal to the value of N.

[0021] The plasma display device according to the present invention comprises a plasma display panel, and a drive device for using the method according to any one of the aforementioned methods for driving a plasma display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]
FIG. 1 is a schematic drawing showing relationship among electrodes for a plasma display panel;

[0023]
FIG. 2 is a timing chart showing a drive method similar to a drive method disclosed in Japanese Patent Laid-Open Publication No. Hei. 11-24628;

[0024]
FIG. 3 is a chart showing a relationship between gradation level and luminance in Table 1;

[0025]
FIG. 4 is a timing chart showing a drive method for a plasma display panel according to a first embodiment of the present invention;

[0026]
FIG. 5 includes drawings showing a relationship between selectable display cells and unselectable display cells in the first embodiment of the present invention,

[0027]
FIG. 5A is a schematic drawing showing the relationship in an nth frame, and

[0028]
FIG. 5B is a schematic drawing showing the relationship in an (n+1)th frame;

[0029]
FIG. 6 is a chart showing a relationship between gradation level and luminance in Table 2;

[0030]
FIG. 7 includes drawings showing a relationship between selectable display cells and unselectable display cells in a second embodiment of the present invention,

[0031]
FIG. 7A is a schematic drawing showing the relationship in an nth frame, and

[0032]
FIG. 7B is a schematic drawing showing the relationship in an (n+1)th frame;

[0033]
FIG. 8 includes drawings showing a relationship between selectable display cells and unselectable display cells in a third embodiment of the present invention,

[0034]
FIG. 8A is a schematic drawing showing the relationship in an nth frame, and

[0035]
FIG. 8B is a schematic drawing showing the relationship in an (n+1)th frame;

[0036]
FIG. 9 includes drawings showing a relationship between selectable display cells and unselectable display cells in a fourth embodiment of the present invention,

[0037]
FIG. 9A is a schematic drawing showing the relationship in an nth frame, and

[0038]
FIG. 9B is a schematic drawing showing the relationship in an (n+1)th frame;

[0039]
FIG. 10 includes drawings showing a relationship between selectable display cells and unselectable display cells in the same fourth embodiment of the present invention,

[0040]
FIG. 10A is a schematic drawing showing the relationship in an (n+2)th frame, and

[0041]
FIG. 10B is a schematic drawing showing the relationship in an (n+3)th frame; and

[0042]
FIG. 11 is a block diagram showing an example of a constitution of a plasma display device (a PDP multimedia monitor) according to the embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0043] The following section specifically describes drive methods for a plasma display panel according to embodiments of the present invention while referring to the accompanied drawings. FIG. 4 is a timing chart showing a drive method for a plasma display panel according to a first embodiment of the present invention. One field comprises four subfields SF1 to SF4 in the first embodiment. It is assumed that the PIE control is conducted for expressing 11 gradation levels. FIG. 4 shows drive waveforms in the lowest subfield when the average peak level is high. Table 2 shows a relationship between the gradation level and selected subfields in the PIE control when the average peak level is high for the first embodiment.

2TABLE 2SubfieldSF1SF2SF3SF4Weight1248Cycle number1124LuminanceGradation00.84level1◯1.462◯2.083◯◯2.704◯2.965◯◯3.586◯◯4.207◯◯◯4.828◯4.729◯◯5.3010 ◯◯5.96

[0044] When the average peak level is low, and there are no subfields with the same sustain cycle numbers, all scan electrodes are scanned, and simultaneously data pulses according to the video signals are impressed on data electrodes in the first embodiment.

[0045] On the other hand, when the average peak level is high, and the sustain cycle numbers are equal in the lowest level subfield SF1 and the second lowest level subfield SF2 while there is a difference in the weight between the lowest level subfield SF1 and the second lowest level subfield SF2 as shown in Table 1, all scan electrodes are scanned, and simultaneously data pulses according to the video signals are impressed only on the odd number data electrodes or the even number data electrodes according to whether the field has an odd number or an even number as shown in FIG. 4 in the subfield SF1. Namely, for the lowest level subfield SF1 of an odd number filed (nth (n: odd number) frame), the data pulses are impressed on the data electrodes according to the video signal only when the odd number scan electrodes (corresponding to mth (m: odd number) line, (m+2)th line, (m+4)th line, . . . ) are scanned while a scan pulse is sequentially impressed on the all scan electrodes as shown in FIG. 4. For an even number filed ((n+1)th frame), the data pulses are impressed on the data electrodes according to the video signal only when the even number scan electrodes (corresponding to (m+1)th line, (m+3)th line, (m+5)th line, . . . ) are scanned while the scan pulse is sequentially impressed on the all scan electrodes.

[0046] Namely, one pixel comprises the display cells in three colors of R (red), G (green), and B (blue). The plurality of pixels arranged in the horizontal direction share a scan line. In a certain frame, for two scan lines next to each other in the vertical direction, one scan line is selectable, and receives the data pulses according to the video signals, and the other scan line is unselectable, and does not receive the data pulses at all. Then, in the following frame, the selectable scan lines and the unselectable scan lines are switched, and this switching is repeated for every frame.

[0047] To disable impressing the data pulses on the predetermined data electrodes regardless of the video signal, a data blank signal is activated in synch with the impressing timing as shown in FIG. 4, for example. When the data blank signal is activated, even if a data latch signal is activated in synch with the impressing timing of the scan pulse, the data pulse is not impressed on the corresponding data electrode.

[0048]
FIG. 5 includes drawings showing a relationship between selectable display cells and unselectable display cells in the first embodiment of the present invention. FIG. 5A is a schematic drawing showing the relationship in an nth (odd number) frame, and FIG. 5B is a schematic drawing showing the relationship in an (n+1)th (even number) frame. The symbol “x” is added to show the unselectable display cells in FIG. 5A and FIG. 5B.

[0049] The data pulses according to the video signals are impressed only on the odd data electrodes or only on the even data electrodes according to whether the field has an odd number or an even number in the present embodiment as described above. Even when the average peak level is high, and the subfield SF1 and the subfield SF2 have the same sustain cycle number, a write discharge does not occur for an odd number field when the scan pulse is impressed in the display cell 1 where the even number scan electrode is provided, and a write discharge does not occur for an even number field when the scan pulse is impressed in the display cell 1 where the odd number scan electrode is provided in the lowest level subfield SF1. As a result, the sustain cycle number for the lowest level subfield SF1 virtually becomes 0.5, which is a half of 1, and is a half of the sustain cycle number of the subfield SF2, which is on one upper level. Consequently, because the luminance increases as the gradation level increases, the reversal of the luminance which occurs in the conventional case does not occur as shown in Table 2. FIG. 6 is a chart for showing a relationship between the gradation level and the luminance in Table 2. A solid line in FIG. 6 shows the relationship in the first embodiment, and a broken line shows the relationship in the conventional case as a reference. While the reversal of the luminance occurs in the conventional drive method (the broken line), no reversal of the luminance occurs in the first embodiment (the solid line) as shown in FIG. 6.

[0050] Also, because all the scan electrodes are scanned in every frame, the screen does not momentarily become darker or brighter as in the conventional drive method which combines the interlace display for the lower level subfields. As a result, an excellent image quality is provided.

[0051] The following section describes the second embodiment of the present invention. FIG. 7 includes drawings showing a relationship between selectable display cells and unselectable display cells in a second embodiment of the present invention. FIG. 7A is a schematic drawing showing the relationship in an nth frame, and FIG. 7B is a schematic drawing showing the relationship in an (n+1)th frame. The symbol “x” is added to show the unselectable display cells in FIG. 7A and FIG. 7B as in FIG. 5A and FIG. 5B.

[0052] In the second embodiment, the display method in the lowest subfield is different from that in the first embodiment when the average peak level is high. One pixel comprises the display cells 1 in three colors of R (red), G (green), and B (blue) as well in the second embodiment. For the two pixels next to each other in the horizontal direction in a certain frame, one pixel is selectable, and receives the data pulses according to the video signals on its data electrodes, and the other pixel is unselectable, and does not receive the data pulses at all. Simultaneously, for the two pixels next to each other in the vertical direction, one pixel is selectable, and receives the data pulses according to the video signals on its data electrodes, and the other pixel is unselectable, and does not receive the data pulses at all. Then, in the following frame, the selectable pixels and the unselectable pixels are switched, and this switching is repeated for every frame.

[0053] With the second embodiment, in the lowest subfield SF1, the selectable pixels receiving the data pulses are arranged in a checkerboard pattern, and the selectable state and the unselectable state are switched for all the pixels for every frame as shown in FIG. 7A and FIG. 7B. As a result, the sustain cycle number for the lowest level subfield SF1 virtually becomes 0.5, which is a half of 1, and is a half of the sustain cycle number of the subfield SF2, which is on one upper level. Consequently, because the luminance increases as the gradation level increases, the reversal of the luminance is prevented.

[0054] Because the selectable pixels are arranged as lines in the first embodiment, more or less flickers may occur. On the other hand, because the selectable pixels are arranged in a checkerboard pattern, no flickers occur in the second embodiment.

[0055] The following section describes a third embodiment. FIG. 8 includes drawings showing a relationship between selectable display cells and unselectable display cells in the third embodiment of the present invention. FIG. 8A is a schematic drawing showing the relationship in an nth frame, and FIG. 8B is a schematic drawing showing the relationship in an (n+1)th frame. The symbol “x” is added to show the unselectable display cells in FIG. 8A and FIG. 8B as in FIG. 5A and FIG. 5B.

[0056] In the third embodiment, the display method is different from that in the first and second embodiments in the lowest level subfield when the average peak level is high. One pixel comprises the display cells 1 in three colors of R (red), G (green), and B (blue) as well in the third embodiment. For the two display cells 1 next to each other in the horizontal direction in a certain frame, one display cell 1 is selectable, and receives the data pulse according to the video signals on its data electrode, and the other display cell 1 is unselectable, and does not receive the data pulse at all. Simultaneously, for the two display cells 1 next to each other in the vertical direction, one display cell 1 is selectable, and receives the data pulse according to the video signals on its data electrode, and the other display cell 1 is unselectable, and does not receive the data pulse at all. Then, in the following frame, the selectable display cells 1 and the unselectable display cells 1 are switched, and this switching is repeated for every frame.

[0057] With the third embodiment, in the lowest level subfield SF1, the selectable display cells 1 for receiving the data pulses are arranged in a checkerboard pattern, the selectable state and the unselectable state for the all display cells 1 are switched for every frame as shown in FIG. 8A and FIG. 8B. As a result, the sustain cycle number for the lowest level subfield SF1 virtually becomes 0.5, which is a half of 1, and is a half of the sustain cycle number of the subfield SF2, which is on one upper level as in the first and second embodiments. Consequently, because the luminance increases as the gradation level increases, the reversal of the luminance is prevented.

[0058] The following section describes a fourth embodiment of the present invention. FIG. 9 and FIG. 10 includes drawings showing a relationship between selectable display cells and unselectable display cells in the fourth embodiment of the present invention. FIG. 9A is a schematic drawing showing the relationship in an nth frame, and FIG. 9B is a schematic drawing showing the relationship in an (n+1)th frame. FIG. 10A is a schematic drawing showing the relationship in an (n+2)th frame, and FIG. 10B is a schematic drawing showing the relationship in an (n+3)th frame. The symbol “x” is added to show the unselectable display cells in FIG. 9A, FIG. 9B, FIG. 10A, and FIG. 10B as in FIG. 5A and FIG. 5B.

[0059] In the fourth embodiment, the display method is different from that in the first to third embodiments in the lowest level subfield when the average peak level is high. One pixel comprises the display cells 1 in three colors of R (red), G (green), and B (blue) as well in the fourth embodiment. Only one fourth of the total pixels included in one screen are selectable for one frame. The individual pixels are selectable once in every four frames.

[0060] Specifically, the data pulses are not impressed on the data electrodes when the even number scan electrodes (corresponding to (m+1)th line, (m+3)th line, (m+5)th line, . . . ) are scanned in the nth frame as shown in FIG. 9A. When the odd number scan electrodes (corresponding to (m)th line, (m+2)th line, (m+4)th line, . . . ) are scanned, for the two display pixels next to each other in the horizontal direction, one pixel is selectable, and receives the data pulses according to the video signals on its data electrodes, and the other pixel is unselectable, and does not receive the data pulses at all. A pixel column comprises the pixels as many as the number of the scan lines included in that pixel column. For the two pixel columns next to each other, one pixel column has no selectable pixels. For the other pixel column, the pixels on the odd number scan lines are entirely selectable.

[0061] The data pulses are not impressed on the data electrodes when the odd number scan electrodes are scanned in the (n+1)th frame as shown in FIG. 9B. When the even number scan electrodes are scanned, the pixels between the pixels which are unselectable and are on the odd number lines in the vertical direction in the nth frame are selectable and receive data pulses according to the video signals on their data electrode. Simultaneously, the pixels between the pixels which are selectable, and are on the odd number lines in the vertical direction in the nth frame are unselectable, and do not receive the data pulses at all.

[0062] The data pulses are not impressed on the data electrodes when the odd number scan electrodes are scanned in the next (n+2)th frame as shown in FIG. 10A. When the even number scan electrodes are scanned, the pixels which are unselectable in the (n+1)th frame are selectable and receive data pulses according to the video signals on their data electrodes. Simultaneously, the pixels which are selectable in the (n+1)th frame are unselectable, and do not receive the data pulses at all.

[0063] The data pulses are not impressed on the data electrodes when the even number scan electrodes are scanned in the next (n+3)th frame as shown in FIG. 10B. When the odd number scan electrodes are scanned, the pixels which are unselectable in the nth frame are selectable and receive data pulses according to the video signals on their data electrode. Simultaneously, the pixels which are selectable in the nth frame are unselectable, and do not receive the data pulses at all.

[0064] Then, this switching between the selectable pixels and unselectable pixels is repeated for every four frames as a unit.

[0065] With the fourth embodiment, the sustain cycle number for the lowest level subfield SF1 virtually becomes 0.25, which is one fourth of 1, and is one fourth of the sustain cycle number of the subfield SF2, which is on one upper level. When the lowest level subfield SF1, the second lowest level subfield SF2, and the third lowest level subfield SF3 have the same sustain cycle number of 1, the following constitution provides a sufficient gradation display without a reversal of the luminance. For the subfield SF3, the sustain cycle number is maintained as 1. For the subfield SF2, any one of the embodiments 1 to 3 is used for virtually reducing the sustain cycle number by half to 0.5. For the subfield SF1, the embodiments 4 is used for virtually reducing the sustain cycle number to 0.25.

[0066] The unit for switching between the selectable state and the unselectable state is not limited to the display cell or the pixel. For example, a block is set per data driver with which the plurality of data electrodes are connected, and the selectable state and the unselectable state may be switched for this block as a unit. For the fourth embodiment, the states may be switched for the display cell as a unit as in the third embodiment instead of the pixel.

[0067] It is preferable not to apply error diffusion to the video signal in the column direction, and to apply the error diffusion only to the video signal in the row direction when the selectable state and the unselectable state is switched for every scan line as in the first embodiment. This corresponds to a case where an analog interface circuit 91 conducts signal processing such as the error diffusion and dithering independently to halftone processing conducted by parts on a PDP side after a digital processing circuit 92 in a plasma display device shown in FIG. 11 described later. This constitution prevents a generation of a moire pattern and the like as a result of an interaction between the signal processing and the drive method of the present invention.

[0068] The plasma display device according to these embodiments can be used as a display device such as a television receiver and a computer monitor. FIG. 11 shows an example of a constitution of a plasma display device (a PDP multimedia monitor) according to the embodiments of the present invention. In this plasma display device, a sustain driver 125 connected with the sustain electrodes, a scan pulse driver 124 connected with the scan electrodes, a scan driver 123 connected on a prior stage of the scan pulse driver 124, and a data driver 126 connected with the data electrodes as drive circuits for a PDP 130, a driver power supply 121 for supplying the drive circuits with a power supply voltage, and a controller 122 for controlling the operation of the drive circuits are provided. Further, an analog interface circuit 91 and the digital signal processing circuit 92 are provided on a stage before the constitution elements described above. A power supply circuit 93 is provided for supplying individual parts of the device with DC voltages from AC 100 V. A Y/C separation circuit and a chroma decoder 94, an analog/digital converter (ADC) 95, an image format conversion circuit 96, an inverse gamma conversion circuit 97, and a synchronization signal control circuit 98 constitute an analog interface circuit 91.

[0069] The Y/C separation circuit and the chroma decoder 94 are circuits which separate an analog video signal Av into a red (R) luminance signal, a green (G) luminance signal, and a blue (B) luminance signal respectively when this display is used as a display for a television receiver. The ADC 95 converts analog RGB signals ARGB into digital RGB signals when this display device is used as a monitor for a computer and the like. The ADC 95 converts the individual luminance signals in R, G, and B supplied from the Y/C separation circuit and the chroma decoder 94 into the individual digital luminance signals in R, G, and B when this display is used as a display for a television receiver. The image format conversion circuit 96 converts a pixel constitution of the individual digital luminance signals in R, G, and B so as to match a pixel constitution of the PDP 130 when there is a difference in the pixel constitution between the individual digital luminance signals in R, G, and B supplied from the ADC 95, and the PDP 130. The inverse gamma conversion circuit 97 applies inverse gamma correction such that the property of the digital RGB signals after gamma correction for matching a gamma characteristic of a CRT display matches a linear gamma characteristic of the PDP 130, or the characteristic of the individual digital luminance signals in R, G, and B from the image format conversion circuit 96 matches the linear gamma characteristic of the PDP 130. The synchronization signal control circuit 98 is a circuit for generating a sampling clock signal for the ADC 95, and a data clock signal based on a horizontal synchronization signal supplied along with the analog video signal Av. The digital signal processing circuit 92 provides the controller 122 with a video signal Sv.

[0070] The power supply circuit 93 generates a logic voltage Vdd, a data voltage Vd, and a sustain voltage Vs from AC 100 V. The driver power supply 121 generates a priming voltage Vp, a scan base voltage Vbw, and a bias voltage Vsw based on the sustain voltage Vs supplied from the power supply circuit 93. The PDP 130, the controller 122, the driver power supply 121, the scan driver 123, the scan pulse driver 124, the sustain driver 125, the data driver 126, and the digital signal processing circuit 92 are modularized. This plasma display device can be applied to any one of the embodiments described above.

[0071] As detailed above, with the present invention, when the predetermined number of the display cells in a subfield is a half of the number of the total display cells of the plasma display, the luminance is reduced by half in that subfield. When the predetermined number of the display cells in the subfield is one fourth of the number of the total display cells, the luminance is reduced to one fourth in that subfield. Thus, even when there are two subfields whose sustain cycle number is 1 as a result of the PLE control, if the number of the predetermined display cells is a half of the total number of the display cells in one of the subfields such as a lower level subfield, the reversal of the luminance is prevented. Simultaneously, because it is not necessary to skip the scan pulse, the screen does not momentarily become darker or brighter, and an excellent image quality is provided.

Drive method for plasma display panel and plasma display device

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CPC

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Priority Claims (1)