Claims
- 1. A driver circuit for a semiconductor test system for generating test signals having predetermined voltage levels for testing a semiconductor device, comprising:
- an output driver for supplying test signals having predetermined voltage levels to said semiconductor device under test, said output driver being formed of first and second pairs of transistors each pair of transistors being connected in a current Miller form;
- a first diode bridge connected to a first reference voltage for providing a first voltage level to a first input of said output driver through a connection point which is shifted by one diode from a center of said first diode bridge;
- a second diode bridge connected to a second reference voltage for providing a second voltage level to a second input of said output driver through a connection point which is shifted by one diode of said second diode bridge;
- a first pair of transistors for supplying bridge current to said first diode bridge to ON/OFF control said first diode bridge;
- a second pair of transistors for supplying bridge current to said second diode bridge to ON/OFF control said second diode bridge; and
- a third pair of transistors for supplying current to said output driver.
- 2. A driver circuit as defined in claim 1, wherein said first pair of transistors in the output driver are NPN transistors and said second pair of transistors in the output driver are PNP transistors, said first voltage level from said connection point of Said first diode bridge is higher than said first reference voltage by a diode threshold voltage, and said second voltage level from said connection point of said second diode bridge is lower than said second reference voltage by a diode threshold voltage.
- 3. A driver circuit as defined in claim 1, further comprising:
- a pair of power sources connected to said output driver for supplying electric power to said output driver; and
- means for supplying current to said first and second diode bridges when said diode bridges are OFF, an amount of said current being sufficiently small when said diode bridges are OFF.
- 4. A driver circuit as defined in claim 1, wherein said first input of said output driver is connected to bases of said first pair of transistors in said output driver and said second input of said output driver is connected to bases of said second pair of transistors in said output driver.
- 5. A driver circuit as defined in claim 1, further comprising:
- a level shift circuit for generating switching signals to drive said first and second pair of transistors which supply bridge current to said first and second diode bridges for switching said first and second diode bridges.
- 6. A driver circuit as defined in claim 1, wherein each of said first and second diode bridges is formed of eight diodes of identical characters.
- 7. A driver circuit as defined in claim 1, wherein said first reference voltage is higher than said second reference voltage.
- 8. A driver circuit as defined in claim 3, further comprising a current limiter circuit for preventing excessive current from flowing in said pair of power supplies.
- 9. A driver circuit as defined in claim 4, further comprising a diode connected between said first and second inputs of said output driver.
- 10. A low power consumption driver circuit for a semiconductor test system for providing a test signal having predetermined voltage levels to a semiconductor device to be tested, comprising:
- first and second analog-voltage signals (VH, VL) which determine high and low voltage levels of said test signal;
- a positive-voltage switching section (511) which supplies current (i6) to a first diode bridge (DB71) by receiving positive differential switching signals (Henb1, Lenb1) when the potential of one positive switching signal (Henb1) is smaller than the other positive switching signal (Lenb1), and supplies current (i2) to a second diode bridge (DB72) and current (i3) to an output driver section (520) when the potential of said one positive switching signal (Henb1) is larger than said other positive switching signal (Lenb1);
- a negative voltage switching section (512) which sinks current (i2) from said second diode bridge (DB72) by receiving negative differential switching signals (Henb2, Lenb2) when the potential of one negative switching signal (Henb2) is smaller than the other negative switching signal (Lenb2), and sinks current (i7) from said first diode bridge (DB71) and current (i8) from said output driver section (520) when the potential of said one negative switching signal (Henb2) is larger than said other negative switching signal (Lenb2);
- said first diode bridge (DB71) consisting of at least six diodes and providing a high level voltage to said semiconductor device to be tested based on said first analog-voltage signal (VH) through a tap position shifted by one diode (D16) in said first diode bridge (DB71) and a first NPN transistor (Q112) of said output driver section (520) when driven by said positive-voltage switching section (511) and said negative-voltage switching section (512);
- said second diode bridge (DB72) consisting of at least six diodes and providing a low level voltage to said semiconductor device to be tested based on said second analog-voltage signal (VL) through a tap position shifted by one diode (D27) in said second diode bridge (DB72) and a first PNP transistor (Q113) of said output driver section (520) when driven by said positive-voltage switching section (511) and said negative-voltage switching section (512);
- said output driver section (520) outputting either one of said first or second analog voltage signals (VH, VL) to the semiconductor device to be tested through an output terminal (out1), said output driver section having one input terminal which receives current from said tap position of said first diode bridge (DB71) and current (i3) from said positive-voltage switching section (511) and other input terminal which receives current from said tap position of said second diode bridge (DB72) and current (i8) from said negative-voltage switching section (512), said output driver section (520) generating a bias potential based on a potential difference (2.times.Vbe) between a second NPN transistor (Q107) and a second PNP transistor (Q108) by said currents (i3.apprxeq.i8) provided to both said input terminals thereby establishing an A-class bias to a complementary structure formed of said first NPN transistor (Q112) and said first PNP transistor (Q113).
- 11. A driver circuit for a semiconductor test system as defined in claim 10, wherein:
- said first and second NPN transistors (Q107) (Q112) are connected in a current Miller form and are integrated in a semiconductor chip, wherein a collector-current ratio therebetween is about 1:6; and
- said first and second PNP transistors (Q108 and Q113) are connected in a current Miller form and are integrated in a semiconductor chip, wherein a collector-current ratio therebetween is about 1:6.
- 12. A driver circuit for a semiconductor test system as defined in claim 10, wherein constant current sections (501 and 502) provide a small amount of current for the side of said output driver section (520) where said first or second diode bridge (DB71, DB72) is OFF.
- 13. A driver circuit for a semiconductor test system as defined in claim 10, further comprising:
- a first current limiter (50) which prevents excessive current flowing through said first NPN transistor (Q112) in said output driver section (520); and
- a second current limiter (51) which prevents excessive current flowing through said first PNP transistor (Q113) in said output driver section (520).
- 14. A driver circuit for a semiconductor test system as defined in claim 10, further includes a level-shift circuit (400) that outputs said differential switching signals (Henb1, Lenb1) shifted to a positive-voltage level and said differential-switching signals (Henb2, Lenb2) shifted to a negative-voltage level by receiving an input pattern signal.
Priority Claims (2)
Number |
Date |
Country |
Kind |
6-138089 |
May 1994 |
JPX |
|
6-333363 |
Dec 1994 |
JPX |
|
Parent Case Info
This application is a divisional of a U.S. patent application Ser. No. 08/451,430 filed May 26, 1995.
US Referenced Citations (4)
Divisions (1)
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Number |
Date |
Country |
Parent |
451430 |
May 1995 |
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