Driving chip package, display device including the same, and method of testing driving chip package

Abstract

A driving chip package, a display device including the same, and a method of testing the driving chip package are disclosed. Any contact failure between the driving chip package and the display substrate can be easily detected, thus reducing the quality management cost and preventing additional failures and increasing the manufacturing yield. The driving chip package includes a base film made of an insulating material, a plurality of interconnection lines formed (e.g., patterned) on the base film (that conduct externally processed driving signals to driving chip and that conduct the driving signals processed in and output by the driving chip), and at least one test interconnection line (e.g., a test signal input interconnection line or a test signal output interconnection line) formed parallel to the interconnection lines on the base film. A test signal input interconnection line and a corresponding test signal output interconnection line are electrically connected through a link on the display substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present invention will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a perspective view of a data driving chip package according to a first embodiment of the present invention;

FIG. 2 is a perspective view of a data driving chip package according to a second embodiment of the present invention;

FIG. 3 is a perspective view of portions of display panel assembly using the data driving chip package of FIG. 1;

FIG. 4 is a perspective view of portions of display panel assembly using the data driving chip package of FIG. 2;

FIG. 5A is a block diagram of a testing unit 420 on a PCB and of a test circuit configuration for testing a driving chip package according to an embodiment of the present invention.

FIG. 5B a block diagram of a testing unit 420 on a PCB and of a test circuit configuration for testing a driving chip package according to another embodiment of the present invention;

FIG. 6 is a circuit diagram of a circuit used in a control unit 460 of the testing unit 400 (or 400′) shown in FIGS. 5A and 5B; and

FIG. 7 is an exploded perspective view of a display device including the display panel assembly as shown in FIG. 3 or 4.

Claims

1. A driving chip package comprising: a base film made of an insulating material;a plurality of interconnection lines formed on the base film, the interconnection line including input interconnection lines that conduct externally processed driving signals to a driving chip and output interconnection lines that output the driving signals processed in the driving chip; andat least one test signal interconnection lines formed on the base film parallel to the plurality of interconnection lines,the test signal interconnection lines are not connected to the driving chip and having a test signal input interconnection line and a test signal output interconnection line.

2. The driving chip package of claim 1, wherein the driving chip is configured to receive the driving signals from the input interconnection lines and processes the received driving signals to output the processed signals to the output interconnection lines, the driving chip is mounted on inner leads formed on a chip mounting area of the base film, each of the inner leads is connected to a corresponding one of the outer leads formed at a terminal portion of the base film through one of the input or output interconnection lines, and each of the at least one test interconnection lines are formed between a pair of outer leads.

3. The driving chip package of claim 1, wherein the test interconnection lines are formed adjacent to and along the interconnection lines.

4. The driving chip package of claim 1 wherein the test interconnection lines are formed on one first side of the base film.

5. The driving chip package of claim 1, wherein two of the test interconnection lines are formed on opposite sides of the base film.

6. The driving chip package of claim 1, wherein the test signal interconnection lines are formed on the same layer as the plurality of interconnection lines and of the same material.

7. The driving chip package of claim 1, wherein the driving chip is a data driving chip.

8. A display device comprising: a display panel including a substrate and a pixel array for displaying an image;a printed circuit board (PCB) configured to generate driving signals and control signals that drive and control the display panel; anda plurality of driving chip packages electrically connected to the display panel and to the PCB, wherein each of the plurality of driving chip packages includes: a base film made of an insulating material;a plurality of interconnection lines formed on the base film, the interconnection lines including input interconnection lines that conduct externally processed driving signals to a driving chip and output interconnection lines that output the driving signals processed in the driving chip; andat least one test signal interconnection lines formed on the base film parallel to the plurality of interconnection lines,the test signal interconnection lines are not connected to the driving chip and having a test signal input interconnection line and a test signal output interconnection line.

9. The display device of claim 8, wherein the test signal interconnection lines are bonded to a test signal input pad formed on the display panel, or to a test signal output pad formed on the display panel, and the test signal input pad and the test signal output pad are electrically connected through a short-circuited interconnection line.

10. The display device of claim 9, wherein the test signal interconnection lines includes a test signal input interconnection line configured to receive a predetermined test signal from the PCB, and a test signal output interconnection line configured to output to the PCB the predetermined test signal conducted through the short-circuited interconnection line from the test signal input interconnection line.

11. The display device of claim 8, wherein the PCB includes: a driving power generating unit configured to generate a driving power of the display panel; anda testing unit electrically connected to the test signal interconnection lines formed on the base film of each driving chip package and configured detect a contact failure at a contact portion between the display panel and the driving chip package.

12. The display device of claim 11, wherein the testing unit includes: a test signal generating unit configured to generate the predetermined test signal and to output the generated test signal to a test signal input interconnection line among the test signal interconnection lines;a detecting unit configured to detect the predetermined test signal output from the test signal output interconnection line and to generate a control signal; anda control unit receiving the predetermined control signal from the detecting unit and generating a power OFF signal.

13. The display device of claim 12, wherein if the predetermined test signal output from the test signal output interconnection line is not detected, the detecting unit generates the active control signal, and if the predetermined test signal is detected, the detecting unit does not generate the control signal.

14. The display device of claim 12, wherein the power OFF signal controls the operation of the driving power generating unit.

15. The display device of claim 12, wherein the display device comprises at least two driving chip packages each having at least two test signal interconnection lines, and the testing unit further includes a logic operation unit configured to generate a single test signal based upon a logical combination of test signals received from a plurality of the test signal interconnection lines and provides the test signal to the detecting unit.

16. The display device of claim 15, wherein the logic operation unit is an AND-gate.

17. The display device of claim 8, wherein the driving chip is configured to receive the driving signals from the input interconnection lines and processes the received driving signals to output the processed signals to the output interconnection lines, the driving chip is mounted on inner leads formed on a chip mounting area of the base film, each of the inner leads is connected to a corresponding one of the outer leads formed at a terminal portion of the base film through one of the input or output interconnection lines, and each of the at least one test interconnection lines are formed between a pair of outer leads.

18. The display device of claim 8, wherein the test interconnection lines are formed adjacent to and along the interconnection lines.

19. The display device of claim 8, wherein the test interconnection lines are formed on one first side of the base film.

20. The display device of claim 8, wherein two of the test interconnection lines are formed on opposite sides of the base film.

21. The display device of claim 8, wherein the test signal interconnection lines are formed on the same layer as the plurality of interconnection lines and of the same material.

22. The display device of claim 8, wherein the driving chip is a data driving chip.

23. A method of testing a driving chip package, comprising: providing a display panel, a printed circuit board (PCB) configured to generate driving signals and control signals that drive and control the display panel, and at least one driving chip package that electrically connects the display panel to the PCB and has at least one test signal interconnection line.transmitting a predetermined test signal to a first test signal interconnection line of the at least one driving chip packages;conducting the predetermined test signal through a second test signal interconnection line electrically connected to the first test signal interconnection line through a short-circuited interconnection line formed on the display panel; anddetermining whether the test signal is detected through a second test signal interconnection line.

24. The method of claim 23, wherein the first test signal interconnection line is one of the at least one test signal interconnection lines of a particular driving chip package, and the second test signal interconnection line is another one of the at least one test signal interconnection lines of the same particular driving chip package, and the pair of corresponding first and second test signal interconnection lines of the same driving chip package are electrically connected to each other through a short-circuited interconnection line formed on the display panel.

25. The method of claim 23, wherein the first test signal interconnection line is one of the at least one test signal interconnection lines of a first driving chip package, and the second test signal interconnection line is one of the at least one test signal interconnection lines of a second driving chip package, and the pair of corresponding first and second test signal interconnection lines of different driving chip packages are electrically connected to each other through a short-circuited interconnection line formed on the display panel.

26. The method of claim 25, wherein the first driving chip package is adjacent to the second driving chip package.

27. The method of claim 25, wherein the first driving chip package is not adjacent to the second driving chip package.

28. The method of claim 23, wherein providing at least one driving chip package includes providing at least two driving chip packages, and the method further comprises outputting a single test signal based on a logical combination of at least two test signals received through the plurality of second test signal interconnection lines.

29. The method of claim 28, wherein the outputting of the single test signal includes combining at least two test signals received through the plurality of second test signal interconnection lines as inputs of an AND-gate that outputs the single test result signal.

30. The method of claim 23, further comprising generating a power OFF signal if a test signal is not detected through a second test signal interconnection line, and otherwise not generating the power OFF signal if the test signal is detected.

31. The method of claim 23, wherein the test signal is any one among driving signals provided by an external device to the PCB.