Claims
- 1. A dual damascene arrangement comprising:a conductive layer; a first dielectric layer over the conductive layer, the first dielectric layer comprising a first low k dielectric material having a dielectric constant less than 4.0; a second dielectric layer on the first dielectric layer, the second dielectric layer comprising a second low k dielectric material having different etch sensitivity than the first low k dielectric material to at least one etchant chemistry; a first opening extending through the first dielectric layer to the conductive layer; a second opening extending through the second dielectric layer to the first dielectric layer; and conductive material filling the first and second openings.
- 2. The arrangement of claim 1, wherein the conductive layer comprises copper or a copper alloy.
- 3. The arrangement of claim 2, wherein the first low k dielectric material is an oxide based dielectric material and the second low k dielectric material is a polymer based material.
- 4. The arrangement of claim 3, wherein the first low k dielectric material is selected from one of hydrogen silsesquioxane (HSQ) and SiOF and the second low k dielectric material is selected from one of BCB and FLARE.
- 5. The arrangement of claim 3, wherein the first low k dielectric material is a polymer based material and the second low k dielectric material is an oxide based material.
- 6. The arrangement of claim 5, wherein the first low k dielectric material is selected from one of benzocyclobutene (BCB) and FLARE and the second low k dielectric material is selected from one of HSQ and SiOF.
- 7. The arrangement of claim 1, wherein the conductive material filling the first and second openings comprises copper or a copper alloy.
RELATED APPLICATIONS
The present application contains subject matter related to subject matter disclosed in U.S. patent applications Ser. No. 09/225,220, filed on Jan. 4, 1999, and Ser. No. 09/225,215, filed on Jan. 4, 1999, now U.S. Pat. No. 6,153,514.
US Referenced Citations (18)
Non-Patent Literature Citations (1)
Entry |
Stanley Wolf and Richard Tauber, Silicon processing the VLSI era, vol. 1, pp. 555. |