The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to a damascene process utilized in semiconductor manufacturing.
With increased device density, the available area for circuit wiring becomes a potential limiting factor in device performance. Such a limitation has led to the development of multi-layer wiring and the adoption of damascene and dual-damascene structures. During a damascene process, interconnect metal lines are delineated in dielectric and isolated from each other by planarization. First, an interconnect pattern is lithographically defined in the layer of dielectric. Then, metal is deposited to fill resulting trenches, and excessive metal is removed by chemical mechanical polishing planarization.
A dual-damascene process is a modified version of the damascene process. It is used to form metal interconnect geometry using planarization such as chemical mechanical polishing. During the process, two interlayer dielectric patterning steps and one chemical mechanical polishing step are generally employed to create a required pattern. During a dual-damascene process, a metal via plug is first formed in a surface, which may be the surface of a semiconductor substrate. A layer of dielectric is deposited over the surface, and trenches (for metal lines) are formed in the dielectric. Metal is then deposited to fill the trenches, and excessive metal over the surface is removed. As a result, a planar structure of interconnect lines with metal inlays in the dielectric is achieved.
It is desired to provide a damascene or dual-damascene process with reduced defects. Typical defects include fencing, damaged etch-stop layers, residue, and so forth.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
Referring now to
The method 10 begins at step 12 in which a patterned insulative layer is filled with a first plug fill material. Referring also to
The semiconductor device 100 also includes an insulative layer 104. The insulative layer 104 (also referred to as a dielectric layer) may be formed by CVD, PECVD, ALD, PVD, spin-on coating and/or other processes. The insulative layer 104 may be an inter-metal dielectric (IMD), and may include low-k materials, silicon dioxide, polyimide, spin-on-glass (SOG), fluoride-doped silicate glass (FSG), Black Diamond® (a product of Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, and/or other materials.
The insulative layer 104 is patterned, such as by photolithography, etching, and/or other means, to form one or more openings 106, thereby exposing a portion of the underlying substrate 102. For the sake of example, the openings 106 will be hereinafter referred to as via holes (also called contact holes).
In some embodiments, one or more barrier layers and/or etch-stop layers may be provided above the substrate 102 and/or in the openings 106, such as by self-ionized plasma (SIP) PVD and/or ionized metal plasma (IMP) PVD. The barrier layer may include Ta, TaN, Ti, TiN, and/or other barrier materials. In furtherance of the example, the bottom portion of a barrier layer proximate the substrate 102, whether formed prior to or after removing a portion of the insulative layer 104, may be removed by in-situ sputtering utilizing SIP or IMP. Consequently, at least a portion of the substrate 102 may be exposed.
The openings 106 may be at least partially filled with a first plug filler material 110 by a damascene process or other methods. In one embodiment, one or more seed layers comprising copper, copper alloys, and/or other seed materials may be deposited initially, thereby lining the opening 106 by PVD, IMP, SIP, and/or other processes. The openings 106 may then be filled with the first plug filler material 110 that may include materials substantially similar to that of the substrate 102. In one example, the first plug filler material 110 may include one ore more low etching rate materials (relative to a second conductive plug described below), such as para-hydroxy styrene (PHS), Novolake, and/or other suitable materials. The conductive material employed to form the first plug filler material 110 may be formed in the opening 106 by spin coating and/or other deposition processes.
At step 14 of method 10 (
At step 16 of method 10, a second plug fill material is deposited into the previously formed openings. Referring also to
At step 18 of method 10 (
At step 20 of method 10, a liner layer may be formed over the insulative layer. With continued reference to
At steps 22 and 24 of method 10 (
At step 26 of method 10 (
At step 28 of the method 10, trench etching is performed. Trench etching may be a continuation of the process used to etch the BARC layer 120, or may be some other type of removal process, such as dry etching, wet etching, or chemical etching. The trench etching removes the second plug material filler 112 to form trench openings 136. After completion of the trench etching, or in continuation thereof, the first plug filler material 110 (and any portions of the second plug material filler 112) in the via holes 106 is etched away, leaving a portion of residue 140 (e.g., a resist residue and/or a portion of the first plug filler material 110). It is contemplated that the trench openings 136 may be formed prior to or following the formation of the etched via holes. The patterned trench mask layer 122 is used as a mask for removing a portion of the exposed insulator layer 104.
Since the residue 140 remains, the substrate 102 is protected from damage that may occur during the etch process. This avoids, for example, via hole punch-through into the substrate 102. The trench opening 136 and the etched via opening together form a dual-damascene opening.
At step 30 of method 10 (
Referring now to
The method 40 begins at step 12 in which a patterned insulative layer is filled with a first plug fill material. Execution then proceeds through steps 14-18 which are similar to the like-numbered steps of method 10 and the examples of
At step 42 of method 40, an under-layer is provided. Referring to
Execution then proceeds to steps 22 and 24 of method 40 (
Execution then proceeds to steps 28 and 30 where trench etching and residue removal are performed. Trench etching and residue removal may be similar to the method discussed above with reference to method 10 of
Referring now to
The method 50 begins at step 12 in which a patterned insulative layer is filled with a first plug fill material. Execution then proceeds through steps 14 and 16 which are similar to the like-numbered steps of method 10 and the examples of
Instead of providing a separate under-layer as discussed above with respect to step 42 of method 40, the second plug filler material 112 serves as the under-layer, which may include materials such as Si, Ti, a polymer with metal, and/or other materials.
Execution then proceeds to steps 22 and 24 of method 50 (
Execution then proceeds to steps 28 and 30 where trench etching and residue removal may be performed. Trench etching and residue removal may be similar to the method discussed above with reference to the like-numbered steps discussed above.
Although only a few exemplary embodiments of this disclosure have been described in details above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Also, features illustrated and discussed above with respect to some embodiments can be combined with features illustrated and discussed above with respect to other embodiments. Accordingly, all such modifications are intended to be included within the scope of this disclosure.
The present application is related to U.S. Pat. No. 6,488,509, U.S. patent application Ser. No. 10/789,083, and U.S. patent application (Attorney Docket No. N1085-00255/TSMC 2003-0509 filed on Jan. 31, 2004 and entitled “Method for Forming Dual Damascene Interconnect Structure”), each of which is hereby incorporated by reference in its entirety.