Patent Application
20060124975
The present invention generally relates to integrated circuit fabrication, and more particularly to an integrated circuit device having a dual work function gate.
In a conventional metal oxide semiconductor (MOS) transistor 10 shown in
The breakdown voltage of the transistor 10 depends upon the doping of the source region 14 and the drain region 16. The thickness of the gate oxide 20 is also used to control the breakdown voltage of the transistor 10 such that the thickness of the gate oxide 20 is increased in order to increase the breakdown voltage of the transistor 10. The breakdown voltage of the transistor can be increased by alternatively using the double-diffused metal oxide semiconductor (DMOS) transistor shown in
Furthermore, the transistor 40 has only a single threshold voltage and, therefore, cannot be easily used in applications requiring selective multiple turn on and turn off voltages.
The present invention overcomes one or more of these disadvantages.
In accordance with one aspect of the present invention, a transistor comprises first and second silicon layers and a gate oxide. The first silicon layer has a source region and a drain region separated by a channel region. The gate oxide is formed over the first silicon layer. The second silicon layer is formed over the gate oxide, and the second silicon layer includes a dual work function gate.
In accordance with another aspect of the present invention, a semiconductor device comprises first and second silicon layers and a gate oxide. The first silicon layer has first and second electrodes formed therein. The gate oxide is formed over the first silicon layer. The second silicon layer is formed over the gate oxide, and the second silicon layer comprises a dual work function gate.
In accordance with yet another aspect of the present invention, a method of making a transistor comprises the following: forming a buried oxide layer over a first silicon layer; forming a second silicon layer over the buried oxide layer such that the second silicon layer includes a source region and a drain region separated by a channel region; forming a gate oxide formed over the channel region of the second silicon layer; and, forming a third silicon layer over the gate oxide such that the third silicon layer includes a dual work function gate.
These and other features and advantages will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:
A transistor 100 in accordance with an embodiment of the present invention is shown in
During formation of the transistor 100, a portion (such as half) of the silicon layer 114 in the area of the gate 112 may be masked during implanting (doping) of the source and drain regions 104 and 106 because the unmasked portion (either the first gate region 116 or the second gate region 118) receives the same doping as the source and drain regions 104 and 106. Subsequently, the originally masked gate region may then be unmasked to receive its suitable doping.
Furthermore, the areas of the silicon layer 114 that are doped to form the n+ first gate region 116 and the p+ second gate region 118 may be selectively controlled depending upon the device that is being fabricated. Additionally, the gate 112 may be silicided to reduce resistance.
The breakdown voltage of the transistor 100 depends upon the doping of the source region 104 and the drain region 106. The thickness of the gate oxide 110 is also used to control the breakdown voltage of the transistor 100 such that the thickness of the gate oxide 110 is increased in order to increase the breakdown voltage of the transistor 10. Unlike the transistor 10, however, the transistor 100 has a higher breakdown voltage. The work function of the second gate region 118 may be on the order of 1.0 eV higher than the work function of the first gate region 116. Therefore, the additional potential barrier will be similar to the drain extension of an LDMOS and hence increases the breakdown voltage.
For proper operation of the transistor 100, the alignment between the gate 112, the gate oxide 110, the source region 104, the drain region 106, and the channel region 108 of the transistor 100 is similar to that of the transistor 10.
Furthermore, because n+ and p+ implants are used to form the first and second gate regions 116 and 118, multiple threshold CMOS devices can be implemented such that the p+ polysilicon can be used for a PMOS device, the p+ polysilicon can be used for an NMOS device, the n+ polysilicon can be used for an NMOS device, and the n+ polysilicon can be used for a PMOS device. Therefore, the transistor 100 can be used in applications requiring selective multiple turn on and turn off voltages. The threshold voltages are set by the work function of the gate and threshold implants.
Also, the doping of a polysilicon layer to form the dual work function gate provided by the first and second gate regions 116 and 118 can be implemented for p-MOS to achieve CMOS. Moreover, hot electron degradation, which is normally a problem in fabricating CMOS devices, is minimized, which leads to a minimization of drain induced barrier lowering (DIBL).
Certain modifications of the present invention will occur to those practicing in the art of the present invention. Other modifications will occur to those practicing in the art of the present invention. For example, the transistor 100 may be a CMOS, DMOS, CDMOS, PMOS, NMOS, Bi-CDMOS, or other semiconductor device.
Accordingly, the description of the present invention is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which are within the scope of the appended claims is reserved.
