Dynamic circuit

Abstract

The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result of logic evaluation performed by a replica of the evaluation circuit; and an initialization circuit for receiving the control signal from the control circuit and an external control signal, to control start and stop of initialization of the dynamic node according to the control signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a dynamic circuit of Embodiment 1.

FIG. 2 is a timing chart illustrating adaptive precharge control performed with the dynamic circuit of FIG. 1.

FIG. 3 is a timing chart illustrating suppression of a through current performed with the dynamic circuit of FIG. 1.

FIG. 4 is a timing chart illustrating precharge cancel operation performed with the dynamic circuit of FIG. 1.

FIGS. 5A and 5B are model diagrams illustrating current consumption related to discharge of a dynamic node in FIG. 1.

FIGS. 6A and 6B are views illustrating an effect of circuit scale reduction attained with the dynamic circuit of FIG. 1.

FIG. 7 is a block diagram of a dynamic circuit omitting the adaptive precharge control.

FIG. 8 is a block diagram of a dynamic circuit of Embodiment 2.

FIG. 9 is a block diagram of a dynamic circuit of Embodiment 3.

FIG. 10 is a block diagram of a dynamic circuit of Embodiment 4.

FIGS. 11A and 11B are views illustrating an effect of circuit scale reduction attained with the dynamic circuit of FIG. 10.

FIG. 12 is a layout of transistors constituting the dynamic circuit of FIG. 10 and the like.

FIG. 13 is a block diagram of a semiconductor memory provided with the dynamic circuit of the present invention.

FIG. 14 is a block diagram of a cache memory provided with the dynamic circuit of the present invention.

FIG. 15 is a block diagram of a PLA provided with the dynamic circuit of the present invention.

FIG. 16 is a block diagram of an adder provided with the dynamic circuit of the present invention.

FIG. 17 is a block diagram of a multiplier provided with the dynamic circuit of the present invention.

FIG. 18 is an outline of a communication apparatus provided with the dynamic circuit of the present invention.

FIG. 19 is an outline of an information playback apparatus provided with the dynamic circuit of the present invention.

FIG. 20 is an outline of an image display apparatus provided with the dynamic circuit of the present invention.

FIG. 21 is an outline of an electronic apparatus provided with the dynamic circuit of the present invention.

FIG. 22 is an outline of an electronic control apparatus provided with the dynamic circuit of the present invention and a mobile unit provided with the electronic control apparatus.

Claims

1. A dynamic circuit comprising: a chargeable dynamic node;an evaluation circuit for performing logic evaluation for a plurality of input signals and changing the charged state of the dynamic node based on an evaluation result;a control circuit having a replica circuit of at least part of the evaluation circuit and outputting a first control signal of which the logic level changes according to a result of logic evaluation for at least part of the plurality of input signals performed by the replica circuit; andan initialization circuit for receiving the first control signal from the control circuit and a second control signal from outside, and starting initialization of the dynamic node if the second control signal shifts from a first logic level to a second logic level and stopping the initialization of the dynamic node if the first control signal shifts from a first logic level to a second logic level.

2. The dynamic circuit of claim 1, wherein the replica circuit has the same logic structure and input as the entire of the evaluation circuit.

3. The dynamic circuit of claim 1, wherein the initialization circuit comprises: a first switch circuit connected to either one of a node for supplying an initializing voltage for the dynamic node and the dynamic node at one terminal, the first switch circuit being turned ON if the second control signal shifts to its second logic level; anda second switch circuit connected to the other terminal of the first switch circuit at one terminal and to the other of the two nodes at the other terminal, the second switch circuit being turned OFF if the first control signal shifts to its second logic level.

4. The dynamic circuit of claim 1, wherein the initialization circuit comprises: a logic operation circuit for receiving the first and second control signals and performing logic operation for these signals; anda switch circuit connected to a node for supplying an initializing voltage for the dynamic node at one terminal and to the dynamic node at the other terminal, the switch circuit switching between ON/OFF of electrical connection between these nodes according to an output of the logic operation circuit.

5. The dynamic circuit of claim 1, wherein the control circuit receives the second control signal, and sets the first control signal at its second logic level if the second control signal is in its second logic level and the result of logic evaluation performed by the replica circuit is truth, and otherwise sets the first control signal at its first logic level.

6. The dynamic circuit of claim 5, wherein the control circuit comprises: a first switch circuit connected to a voltage node corresponding to the second logic level of the first control signal at one terminal and to one terminal of the replica circuit at the other terminal, the first switch circuit receiving the second control signal and being turned ON if the second control signal shifts to its second logic level; anda second switch circuit connected to a voltage node corresponding to the first logic level of the first control signal at one terminal and to an output node of the first control signal, the second switch circuit receiving the second control signal and being turned ON if the second control signal shifts to its first logic level, andthe other terminal of the replica circuit is connected to the output node of the first control signal.

7. The dynamic circuit of claim 1, wherein the control circuit receives the second control signal and a voltage of the dynamic node, and sets the first control signal at its second logic level if the second control signal is in its second logic level and either the result of logic evaluation performed by the replica circuit is truth or the voltage of the dynamic node is equal to or higher than a predetermined level, and otherwise sets the first control signal at its first logic level.

8. The dynamic circuit of claim 7, wherein the control circuit comprises: a first switch circuit connected to a voltage node corresponding to the second logic level of the first control signal at one terminal and to one terminal of the replica circuit at the other terminal, the first switch circuit receiving the second control signal and being turned ON if the second control signal shifts to its second logic level;a second switch circuit connected to either one of a voltage node corresponding to the first logic level of the first control signal and an output node of the first control signal at one terminal, the second switch circuit receiving the second control signal and being turned ON if the second control signal shifts to its first logic level;a third switch circuit connected to the other terminal of the second switch circuit and to the other of the voltage node corresponding to the first logic level of the first control signal and the output node of the first control signal at the other terminal, the third switch circuit being ON until the voltage of the dynamic node reaches the predetermined level; anda fourth switch circuit connected in parallel with at least the replica circuit and turned ON once the voltage of the dynamic node reaches the predetermined level, andthe other terminal of the replica circuit is connected to the output node of the first control signal.

9. The dynamic circuit of claim 1, further comprising a constant current source connected in series with the evaluation circuit.

10. The dynamic circuit of claim 1, wherein transistors constituting the replica circuit and transistors constituting the corresponding at least part of the evaluation circuit are configured in pairs, and signal input terminals of the replica circuit and the corresponding at least part of the evaluation circuit are placed between the respective paired transistors.

11. The dynamic circuit of claim 1, wherein the evaluation circuit has a plurality of transistors respectively provided for the plurality of input signals for switching between ON/OFF according to the corresponding input signals, and the plurality of transistors are connected in parallel.

12. A dynamic circuit comprising: a chargeable dynamic node;an initialization circuit for initializing the dynamic node; andan evaluation circuit for performing logic evaluation for a plurality of input signals and changing the charged state of the dynamic node according to an evaluation result,wherein the evaluation circuit has a plurality of transistors respectively provided for the plurality of input signals for switching between ON/OFF according to the corresponding input signals, andthe plurality of transistors are connected in parallel.

13. A semiconductor memory comprising an address decoder and a memory array, wherein the address decoder has a logic operation circuit comprising the dynamic circuit of claim 1.

14. A cache memory comprising a memory array and a tag determination circuit, wherein the tag determination circuit has a logic operation circuit comprising the dynamic circuit of claim 1.

15. A PLA comprising an AND plane circuit and an OR plane circuit, wherein at least one of the AND plane circuit and the OR plane circuit has a logic operation circuit comprising the dynamic circuit of claim 1.

16. An adder comprising a carry calculation circuit, a carry generation circuit and a carry propagation circuit, wherein at least one of the carry calculation circuit, the carry generation circuit and the carry propagation circuit has a logic operation circuit comprising the dynamic circuit of claim 1.

17. A multiplier comprising a booth encoder and a partial product addition tree, wherein at least one of the booth encoder and the partial product addition tree has a logic operation circuit comprising the dynamic circuit of claim 1.

18. A communication apparatus comprising a semiconductor integrated circuit having the dynamic circuit of claim 1.

19. An information playback apparatus comprising a semiconductor integrated circuit having the dynamic circuit of claim 1.

20. An image display apparatus comprising a semiconductor integrated circuit having the dynamic circuit of claim 1.

21. An electronic apparatus comprising a semiconductor integrated circuit having the dynamic circuit of claim 1.

22. An electronic control apparatus comprising a semiconductor integrated circuit having the dynamic circuit of claim 1.

23. A mobile unit comprising the electronic control apparatus of claim 22.

24. A method for initializing a dynamic circuit, comprising the steps of: starting initialization of a dynamic node under a predetermined condition;performing logic evaluation for at least part of a plurality of input signals; andstopping the initialization of the dynamic node if a result of the logic evaluation is true.

25. The method of claim 24, wherein the initialization of the dynamic node is continued until the voltage of the dynamic node reaches a predetermined level if the result of the logic evaluation is false, and is stopped once the voltage of the dynamic node reaches the predetermined level.