Claims
- 1. A dynamic flip-flop circuit comprising:
a first latch having a first input lead, a second input lead, and an output lead, said first latch including a first shutoff circuit, said first shutoff circuit including a first nand gate, a first inverter, and a first n-channel transistor, said first nand gate having a first input lead and a second input lead, said first input lead coupled to an output lead of a second latch, and said second input lead coupled to a compare enable line, said first inverter having an input lead and an output lead, said input lead coupled to said output lead of said first nand gate, and said first n-channel transistor having a first lead coupled to said output lead of said first inverter and a second lead coupled to said output lead of said first latch; and said second latch having an input lead and an output lead, said second latch further including a second shutoff circuit, said second shutoff circuit including a second nand gate, a second inverter, and a second n-channel transistor, said second nand gate having a second input lead and a second input lead, said second input lead coupled to said output lead of said first latch, and said second input lead coupled to said compare enable line, said second inverter having an input lead and an output lead, said input lead coupled to said output lead of said second nand gate, and said second n-channel transistor having a second lead coupled to said output lead of said second inverter and a second lead coupled to said output lead of said second latch.
- 2. The dynamic flip-flop circuit of claim 1, wherein said first latch further includes:
a third transistor having a first lead coupled to a clock signal, a second lead coupled to a first voltage source, and a third lead coupled to said output lead of said first latch; a fourth transistor having a first lead coupled to a data signal, and a second lead coupled to a third lead of said first transistor; and a fifth transistor having a first lead coupled to said clock signal, a second lead coupled to a second voltage source, and a third lead coupled to a third lead of said fourth transistor.
- 3. The dynamic flip-flop circuit of claim 2, wherein said first latch further includes:
a sixth transistor having a first lead coupled to said output lead of said second latch, a second lead coupled to said first voltage source, and a third lead coupled to said output lead of said first latch.
- 4. The dynamic flip-flop circuit of claim 1, further comprising a first output latch, said first output latch comprising:
a third transistor, said third transistor having a first lead, a second lead, and a third lead; a fourth transistor, said first transistor having a first lead, a second lead, and a third lead; an inverter having an input and an output; wherein said first lead of said third transistor is coupled to said output line of said first latch and said third lead of said third transistor is coupled to a first voltage source; wherein said first lead of said fourth transistor is coupled to a second voltage source, said second lead of said fourth transistor is coupled to said second lead of said third transistor, and said third lead of said fourth transistor is coupled to said output line of said first latch; and wherein said output lead of said inverter is coupled to said second lead of said third transistor, and said input lead of said inverter is coupled to said output line of said first latch.
- 5. The dynamic flip-flop circuit of claim 2, further comprising a second output latch, said second output latch comprising:
a fifth transistor, said fifth transistor having a first lead, a second lead, and a third lead; a sixth transistor, said sixth transistor having a first lead, a second lead, and a third lead; a second inverter having an input and an output; wherein said first lead of said fifth transistor is coupled to said output line of said second latch and said third lead of said fifth transistor is coupled to a third voltage source; wherein said first lead of said sixth transistor is coupled to a fourth voltage source, said second lead of said sixth transistor is coupled to said second lead of said fifth transistor, and said third lead of said sixth transistor is coupled to said output line of said second latch; and wherein said output lead of said second inverter is coupled to said second lead of said fifth transistor, and said input lead of said second inverter is coupled to said output line of said second latch.
- 6. The dynamic flip-flop circuit of claim 1, wherein said first input lead of said first latch and said first input lead of said second latch are coupled to a clock line.
- 7. The dynamic flip-flop circuit of claim 6, wherein said compare enable line is coupled to a compare enable latch, said compare enable latch operative to prevent the compare enable line from going positive when said clock line is positive.
- 8. A dynamic flip-flop circuit comprising:
a first latch having a first input lead, a second input lead, a third input lead, and an output lead, said first latch including a shutoff circuit, wherein
said first input lead of said first latch is coupled to receive a clock signal; said second input lead of said first latch is coupled to receive a data signal; said third input lead of said first latch is coupled to receive a compare enable signal; said first latch is operative to output a signal of a first logic level at said output lead of said first latch when said clock signal is low; said first latch is operative to sample a logic level at said second input lead of said first latch when said data signal is high and said clock signal is high; and said first shutoff circuit is operative to cause said first latch to stop sampling when said data signal is high and said clock signal is high, unless said compare enable signal is low. a second latch having an input lead and an output lead, said second latch including a second shutoff circuit, wherein
said second latch is operative to output a signal of said first logic level at said output lead of said second latch when both said clock signal is low; said first input lead of said second latch is coupled to receive said clock signal; and said second input lead of said second latch is coupled to receive a complement of said data signal; said first latch is operative to output a signal of a first logic level at said output lead of said first latch when both said clock signal is low; said first latch is operative to sample a logic level at said second input lead of said first latch when said data signal is high and said clock signal is high; and said first shutoff circuit is operative to cause said first latch to stop sampling when said data signal is high and said clock signal is high, unless said compare enable signal is low. a first output latch having an input lead and an output lead, said input lead of said first output latch coupled to said output lead of said first latch; and a second output latch having an input lead and an output lead, said input lead of said second output latch coupled to said output lead of said second latch.
- 9. The dynamic flip-flop circuit of claim 8, wherein said first shutoff circuit further comprises:
a nand gate having a first input lead coupled to said output lead of said second latch, and a second input lead operatively coupled to said write enable signal; an inverter having an input lead coupled to an output lead of said nand gate; and a first transistor having a first lead coupled to an output lead of said second inverter and a second lead coupled to said output lead of said first latch.
- 10. The dynamic flip-flop circuit of claim 9, wherein said first output latch further includes:
a second transistor having a first lead coupled to said clock signal, a second lead coupled to a first voltage source, and a third lead coupled to said output lead of said first latch; a third transistor having a first lead coupled to said data signal, and a second lead coupled to a third lead of said first transistor; and a fourth transistor having a first lead coupled to said clock signal, a second lead coupled to a second voltage source, and a third lead coupled to a third lead of said second transistor.
- 11. The dynamic flip-flop circuit of claim 10, wherein said first latch further includes:
a fifth transistor having a first lead coupled to said output lead of said second latch, a second lead coupled to said first voltage source, and a third lead coupled to said output lead of said first latch.
- 12. The dynamic flip-flop circuit of claim 8, wherein said first output latch comprising:
a first transistor, said first transistor having a first lead, a second lead, and a third lead; a second transistor, said first transistor having a first lead, a second lead, and a third lead; an inverter having an input and an output; wherein said first lead of said first transistor is coupled to said output line of said first latch and said third lead of said first transistor is coupled to a first voltage source; wherein said first lead of said second transistor is coupled to a second voltage source, said second lead of said second transistor is coupled to said second lead of said first transistor, and said third lead of said second transistor is coupled to said output line of said first latch; and wherein said output lead of said inverter is coupled to said second lead of said first transistor, and said input lead of said inverter is coupled to said output line of said first latch.
- 13. The dynamic flip-flop circuit of claim 12, further comprising a second output latch, said second output latch comprising:
a third transistor, said third transistor having a first lead, a second lead, and a third lead; a fourth transistor, said fourth transistor having a first lead, a second lead, and a third lead; a second inverter having an input and an output; wherein said first lead of said third transistor is coupled to said output line of said second latch and said third lead of said third transistor is coupled to a third voltage source; wherein said first lead of said fourth transistor is coupled to a fourth voltage source, said second lead of said fourth transistor is coupled to said second lead of said third transistor, and said third lead of said fourth transistor is coupled to said output line of said second latch; and wherein said output lead of said second inverter is coupled to said second lead of said fifth transistor, and said input lead of said second inverter is coupled to said output line of said second latch.
- 14. The dynamic flip-flop circuit of claim 8, wherein said compare enable signal is coupled to a compare enable latch, said compare enable latch operative to prevent the compare enable signal from going positive when said clock signal is positive.
STATEMENT OF RELATED APPLICATION
[0001] This application claims priority based on provisional application serial No. 60/199,486, entitled “Dynamic Flop with Power Down Mode” by Jaya Prakash Samala, filed on Apr. 25, 2000 and is related to co-pending application entitled “Method for Operating a Dynamic Flop with Power Down Mode” by Jaya Prakash Samala, filed on May 30, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60199486 |
Apr 2000 |
US |
Divisions (1)
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Number |
Date |
Country |
Parent |
09586477 |
Jun 2000 |
US |
Child |
09859945 |
May 2001 |
US |