Dynamic random access memory applied to an embedded display port

Abstract

A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dynamic random access memory, and particularly to a dynamic random access memory applied to an embedded display port.

2. Description of the Prior Art

An embedded display port (eDP) published by the Video Electronics Standards Association (VESA) is used for acting as a standard display panel interface to connect external devices. For example, the embedded display port can act as an interface between a video card and a notebook panel. In addition, the embedded display port version 1.3 published by the Video Electronics Standards Association adds a panel self refresh (PSR) function, where the panel self refresh function can make a graphic processing unit (GPU) turn off connection between the graphic processing unit and a liquid crystal panel when a frame displayed on the liquid crystal panel is frozen. Thus, power consumption of the graphic processing unit can be significantly reduced and battery endurance ability can be extended.

In addition, a timing controller supporting the panel self refresh function of the liquid crystal display needs to include a frame buffer (e.g. a dynamic random access memory). When the graphic processing unit turns off the connection between the graphic processing unit and the liquid crystal panel, the frame buffer needs to store a last frame before the graphic processing unit turns off the connection between the graphic processing unit and the liquid crystal panel. Therefore, when no data transmission exists between the graphic processing unit and the liquid crystal panel, the timing controller can directly output the last frame stored in the frame buffer.

Although the panel self refresh function can make power consumption of the graphic processing unit be significantly reduced, power consumption of the timing controller is increased due to operation of the frame buffer. Therefore, how to design the frame buffer to reduce the power consumption of the timing controller becomes an important issue of memory manufacturers.

SUMMARY OF THE INVENTION

An embodiment provides a dynamic random access memory applied to an embedded display port. The dynamic random access memory includes a memory core unit and a peripheral circuit unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V.

Another embodiment provides a dynamic random access memory applied to an embedded display port. The dynamic random access memory includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the peripheral circuit unit and the memory core unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

The present invention provides a dynamic random access memory applied to an embedded display port. The dynamic random access memory makes a memory core unit, a peripheral circuit unit, and an input/output unit thereof operate in lower voltages. Compared to the prior art, power consumption of the dynamic random access memory of the present invention is much lower than power consumption of a dynamic random access memory operating in operation voltages specified by the Joint Electron Device Engineering Council. Thus, when the dynamic random access memory of the present invention is applied to an embedded display port, the present invention can make system power consumption (e.g. power consumption of a graphic processing unit) be significantly reduced, not make power consumption of a timing controller be increased due to operation of a frame buffer, and extend battery endurance ability of a portable device.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The FIGURE is a diagram illustrating a dynamic random access memory 100 applied to embedded display port according to an embodiment.

DETAILED DESCRIPTION

Please refer to the FIGURE. The FIGURE is a diagram illustrating a dynamic random access memory 100 applied to an embedded display port according to an embodiment, where the dynamic random access memory 100 acts as a frame buffer of a timing controller of a liquid crystal display, and the dynamic random access memory 100 is compatible with a single data rate (SDR) specification, a double data rate (DDR I) specification, a double data rate two (DDR II) specification, or a double data rate three (DDR III) specification. As shown in the FIGURE, the dynamic random access memory 100 includes a memory core unit 102, a peripheral circuit unit 104, and an input/output unit 106, where the peripheral circuit unit 104 is electrically connected to the memory core unit 102, and the input/output unit 106 is electrically connected to the peripheral circuit unit 104 and the memory core unit 102. Please refer to Table I. Table I illustrates operation voltages (specified by the Joint Electron Device Engineering Council (JEDEC)) of a dynamic random access memory operating in the DDR I specification, a low power DDR I specification, the DDR II specification, and a low power DDR II specification.

TABLE I
	memory core	peripheral circuit	input/output
	unit 102	unit 104	unit 106
DDR I	3.3 V ±	0.3 V or	3.3 V ±	0.3 V or	3.3 V ±	0.3 V or
	2.5 V ±	0.2 V	2.5 V ±	0.2 V	2.5 V ±	0.2 V
Low Power	1.8 V ±	0.1 V	1.8 V ±	0.1 V	1.8 V ±	0.1 V
DDR I
DDR II	1.8 V ±	0.1 V	1.8 V ±	0.1 V	1.8 V ±	0.1 V
Low Power	1.7 V~1.95 V	1.14 V~1.30 V	1.14 V~1.30 V
DDR II

If the dynamic random access memory 100 is designed to have low power consumption to reduce power consumption of the timing controller, the dynamic random access memory 100 needs to have low operation power consumption (e.g. power consumption for the dynamic random access memory 100 outputting storage frames to the timing controller) and low standby power consumption. But, the operation voltages specified by the Joint Electron Device Engineering Council (as shown in Table I) can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3.

Please refer to Table II. Table II illustrates operation voltage ranges of the dynamic random access memory 100 operating in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification according to an embodiment.

TABLE II
	memory core	peripheral	input/output
	unit 102	circuit unit 104	unit 106
operation voltage ranges	<1.1 V	<1.1 V	<1.1 V

As shown in Table II, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is lower than 1.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

As shown in Table II, because the operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are the first predetermined voltage, the dynamic random access memory 100 has lower memory core power consumption; because the operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are the second predetermined voltage, the dynamic random access memory 100 has lower access power consumption; and the operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are the third predetermined voltage, the dynamic random access memory 100 has lower input/output power consumption. In addition, the input/output unit 106 is compatible with an interface provided by the prior art, so power consumption of the dynamic random access memory 100 is much lower than power consumption of the dynamic random access memory operating in the operation voltages specified by the Joint Electron Device Engineering Council.

Please refer to Table III. Table III illustrates operation voltage ranges of the dynamic random access memory 100 operating in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification according to another embodiment.

TABLE III
	memory core	peripheral	input/output
	unit 102	circuit unit 104	unit 106
operation voltage ranges	1.8 V ± 0.1 V	<1.1 V	<1.1 V

As shown in Table III, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is equal to 1.8V±0.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

As shown in Table III, because the operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are the first predetermined voltage, the dynamic random access memory 100 has higher charge pump efficiency; because the operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are the second predetermined voltage, the dynamic random access memory 100 has lower access power consumption; and the operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are the third predetermined voltage, the dynamic random access memory 100 has lower input/output power consumption. In addition, the input/output unit 106 is also compatible with an interface provided by the prior art, so power consumption of the dynamic random access memory 100 is much lower than power consumption of the dynamic random access memory operating in the operation voltages specified by the Joint Electron Device Engineering Council.

To sum up, the dynamic random access memory applied to an embedded display port makes the memory core unit, the peripheral circuit unit, and the input/output unit operate in lower voltages. Compared to the prior art, power consumption of the dynamic random access memory of the present invention is much lower than power consumption of a dynamic random access memory operating in the operation voltages specified by the Joint Electron Device Engineering Council. Thus, when the dynamic random access memory of the present invention is applied to an embedded display port, the present invention can make system power consumption (e.g. power consumption of a graphic processing unit) be significantly reduced, not make power consumption of the timing controller be increased due to operation of the frame buffer, and extend battery endurance ability of a portable device.

Although the present invention has been illustrated and described with reference to the embodiments, it is to be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A dynamic random access memory (DRAM), comprising: a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage within a first voltage range to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell, wherein the first voltage is lower than 1.1V; anda peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage within a second voltage range to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V, andwherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell, and wherein the first voltage is different from the second voltage.

2. A dynamic random access memory (DRAM), comprising: a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage within a first voltage range to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell, wherein the first voltage is lower than 1.1V; anda peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage within a second voltage range to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V;wherein the first voltage is greater than the second voltage.

3. A dynamic random access memory (DRAM), comprising: a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell;an input/output circuit comprised in the DRAM, wherein the input/output circuit is electrically connected to the DRAM core cell, and the input/output circuit is supplied with a third voltage to make the input/output circuit operate at the third voltage, wherein the third voltage is lower than 1.1V; anda peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V and the first voltage is different from the second voltage;wherein the DRAM core cell and the input/output circuit are formed on a single chip, and the input/output circuit is external to the DRAM core cell, and wherein the first voltage is different from the third voltage.

4. The dynamic random access memory of claim 3, wherein the first voltage is lower than 1.1V.

5. The dynamic random access memory of claim 3, wherein the first voltage is different from the second voltage.

6. A dynamic random access memory (DRAM), comprising: a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell; andan input/output circuit comprised in the DRAM, wherein the input/output circuit is electrically connected to the DRAM core cell, and the input/output circuit is supplied with a third voltage to make the input/output circuit operate at the third voltage, wherein the third voltage is lower than 1.1V;wherein the first voltage is greater than the third voltage, and the DRAM operating with the first voltage and the third voltage is capable of being applied to an embedded display port (eDP).

7. The dynamic random access memory of claim 6, wherein the first voltage is lower than 1.1V.

8. The dynamic random access memory of claim 6, further comprising: a peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V.

9. The dynamic random access memory of claim 8, wherein the first voltage is different from the second voltage.