for multiport memories each having random access ports and serial ports

Industry

CPC
G11C7/1075

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1075for multiport memories each having random access ports and serial ports

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Multi-bitcell structure with shared read port
- Patent number 12,165,737
- Issue date Dec 10, 2024
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, method of operating the memory device, memory module...
- Patent number 12,154,651
- Issue date Nov 26, 2024
- Samsung Electronics Co., Ltd.
- Sunyoung Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic random access memory applied to an embedded display port
- Patent number 12,154,652
- Issue date Nov 26, 2024
- Etron Technology, Inc.
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area-efficient scalable memory read-data multiplexing and latching
- Patent number 12,130,654
- Issue date Oct 29, 2024
- Intel Corporation
- Amir Javidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transfer in port switch memory
- Patent number 12,001,713
- Issue date Jun 4, 2024
- Frank F. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 12,001,345
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet routing between memory devices and related apparatuses, meth...
- Patent number 11,947,798
- Issue date Apr 2, 2024
- Micron Technology, Inc.
- John D. Leidel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,940,930
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic random access memory applied to an embedded display port
- Patent number 11,894,098
- Issue date Feb 6, 2024
- Etron Technology, Inc.
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 11,886,353
- Issue date Jan 30, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data structures with multiple read ports
- Patent number 11,875,874
- Issue date Jan 16, 2024
- Groq, Inc.
- Jonathan Alexander Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 11,868,272
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port memory device and a method of using the same
- Patent number 11,837,319
- Issue date Dec 5, 2023
- Samsung Electronics Co., Ltd.
- Hingkwan Huen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transferring data between DRAM and SRAM
- Patent number 11,837,315
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Timothy P. Finkbeiner
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having interconnection in package and method f...
- Patent number 11,837,273
- Issue date Dec 5, 2023
- Samsung Electronics Co., Ltd.
- Jaehyung Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-port, dual-function memory device
- Patent number 11,830,574
- Issue date Nov 28, 2023
- Micron Technology, Inc.
- Poorna Kale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 11,803,486
- Issue date Oct 31, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module with configurable command buffer
- Patent number 11,782,863
- Issue date Oct 10, 2023
- RAMBUS INC.
- Liji Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port storage-class memory interface
- Patent number 11,783,876
- Issue date Oct 10, 2023
- Micron Technology, Inc.
- Joseph Thomas Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic compare and swap in cach...
- Patent number 11,775,446
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different tags
- Patent number 11,762,780
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port SDRAM
- Patent number 11,763,860
- Issue date Sep 19, 2023
- Microsoft Technology Licensing, LLC
- Segev Ravgad
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus to facilitate fully pipelined read-modify-wri...
- Patent number 11,741,020
- Issue date Aug 29, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSFER IN PORT SWITCH MEMORY
- Publication number 20240319909
- Publication date Sep 26, 2024
- Lodestar Licensing Group LLC
- Frank F. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-VOLTAGE RAM USED TO CROSS CLOCK AND VOLTAGE DOMAINS
- Publication number 20240296875
- Publication date Sep 5, 2024
- NVIDIA Corporation
- Jason Golbus
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METH...
- Publication number 20240241641
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- John D. Leidel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
- Publication number 20240112707
- Publication date Apr 4, 2024
- ETRON TECHNOLOGY, INC.
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PORT MEMORY DEVICE AND A METHOD OF USING THE SAME
- Publication number 20240087620
- Publication date Mar 14, 2024
- Samsung Electronics Co., Ltd.
- Hingkwan Huen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20240078190
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20240028523
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20240020242
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT TAGS
- Publication number 20240004800
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controllers, systems, and methods supporting multiple reques...
- Publication number 20230420010
- Publication date Dec 28, 2023
- Rambus Inc.
- Richard E. Perego
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20230401162
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE MEMORY MODULE DESIGNED TO IMPLEMENT COMPUTING OPERAT...
- Publication number 20230352066
- Publication date Nov 2, 2023
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Roman GAUCHI
- G11 - INFORMATION STORAGE
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20230342305
- Publication date Oct 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM
- Publication number 20230333991
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, MEMORY MODULE...
- Publication number 20230298638
- Publication date Sep 21, 2023
- Samsung Electronics Co., Ltd.
- SUNYOUNG LIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Bitcell Structure with Shared Read Port
- Publication number 20230282253
- Publication date Sep 7, 2023
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20230281126
- Publication date Sep 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS...
- Publication number 20230251702
- Publication date Aug 10, 2023
- Tahoe Research, Ltd.
- Yen-Cheng LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20230236974
- Publication date Jul 27, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PORT SDRAM
- Publication number 20230197124
- Publication date Jun 22, 2023
- Microsoft Technology Licensing, LLC
- Segev RAVGAD
- G11 - INFORMATION STORAGE
Information Patent Application
AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING
- Publication number 20230137508
- Publication date May 4, 2023
- Intel Corporation
- Amir JAVIDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE MULTIPLE PORT BUFFER TECHNIQUES
- Publication number 20230127970
- Publication date Apr 27, 2023
- Micron Technology, Inc.
- Jasper S. Gibbons
- G11 - INFORMATION STORAGE

for multiport memories each having random access ports and serial ports

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Multi-bitcell structure with shared read port

Memory device, method of operating the memory device, memory module...

Dynamic random access memory applied to an embedded display port

Methods and apparatus for read-modify-write support in multi-banked...

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Area-efficient scalable memory read-data multiplexing and latching

Methods and apparatus for eviction in dual datapath victim cache sy...

Methods and apparatus to facilitate read-modify-write support in a...

Victim cache with write miss merging

Data transfer in port switch memory

Victim cache that supports draining write-miss entries

Packet routing between memory devices and related apparatuses, meth...

Methods and apparatus to reduce read-modify-write cycles for non-al...

Methods and apparatus to facilitate atomic operations in victim cache

Dynamic random access memory applied to an embedded display port

Hybrid victim cache and write miss buffer with fence operation

Data structures with multiple read ports

Methods and apparatus for allocation in a victim cache system

Multi-port memory device and a method of using the same

Transferring data between DRAM and SRAM

Semiconductor device having interconnection in package and method f...

Dual-port, dual-function memory device

Write merging on stores with different privilege levels

Memory module with configurable command buffer

Multi-port storage-class memory interface

Methods and apparatus to facilitate atomic compare and swap in cach...

Write merging on stores with different tags

Multi-port SDRAM

Methods and apparatus to facilitate fully pipelined read-modify-wri...

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

DATA TRANSFER IN PORT SWITCH MEMORY

VICTIM CACHE WITH WRITE MISS MERGING

MULTI-VOLTAGE RAM USED TO CROSS CLOCK AND VOLTAGE DOMAINS

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

PACKET ROUTING BETWEEN MEMORY DEVICES AND RELATED APPARATUSES, METH...

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

MULTI-PORT MEMORY DEVICE AND A METHOD OF USING THE SAME

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

WRITE MERGING ON STORES WITH DIFFERENT TAGS

Memory controllers, systems, and methods supporting multiple reques...

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

RECONFIGURABLE MEMORY MODULE DESIGNED TO IMPLEMENT COMPUTING OPERAT...

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM

MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, MEMORY MODULE...

Multi-Bitcell Structure with Shared Read Port

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS...

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

MULTI-PORT SDRAM

AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING

MEMORY MODULE MULTIPLE PORT BUFFER TECHNIQUES