Claims
- 1. A processor system comprising:
a central processing unit; a graphics unit; a shared cache coupled to the central processing unit and the graphics unit; monitor circuitry to monitor hits or misses in the shared cache resulting from accesses by the graphics unit; and, cache replacement circuitry, responsive to the monitor circuitry, to limit eviction in selected regions of the shared cache based on over-utilization by the graphics unit.
- 2. A processor system as recited in claim 1 wherein the shared cache is a secondary level cache.
- 3. A processor system as recited in claim 1 wherein the monitor circuitry is a statistic counter.
- 4. A processor system as recited in claim 3 wherein the cache replacement circuitry includes a programmable mode register.
- 5. A processor system as recited in claim 4 wherein an application program reads the statistic counter to determine whether to program the programmable mode register.
- 6. A processor system as recited in claim 4 wherein a software driver reads the statistic counter to determine whether to program the programmable mode register.
- 7. A processor system comprising:
a central processing unit; a unified cache coupled to the central processing unit; monitor circuitry to monitor hits or misses in the unified cache resulting from accesses by a predetermined application; and, cache replacement circuitry, responsive to the monitor circuitry, to limit eviction in selected regions of the unified cache based on over-utilization by the predetermined application.
- 8. A processor system as recited in claim 7 wherein the predetermined application is a number of hits in the unified cache for instructions for the central processing unit.
- 9. A processor system as recited in claim 7 wherein the predetermined application is a number of hits in the unified cache for data for the central processing unit.
- 10. A processor system as recited in claim 7 wherein the monitor circuitry is a statistic counter.
- 11. A processor system as recited in claim 10 wherein the cache replacement circuitry includes a programmable mode register.
- 12. A processor system as recited in claim 11 wherein an application program reads the statistic counter to determine whether to program the programmable mode register.
- 13. A processor system as recited in claim 11 wherein a software driver reads the statistic counter to determine whether to program the programmable mode register.
- 14. A method of dynamically altering cache replacement rules in a processor system having a unified cache comprising steps of:
(a) monitoring hits or misses in the unified cache resulting from accesses by a predetermined application to identify over-utilization by the predetermined application; and, (b) responsive to step (a), limiting eviction by the predetermined application to selected regions in the unified cache.
- 15. The method recited in claim 14 wherein the predetermined application is a graphics unit storing texture maps in the unified cache.
- 16. The method recited in claim 14 wherein the unified cache is a secondary level cache.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to commonly assigned and co-pending U.S. patent applications Ser. No. ______ (attorney's docket number 04176) entitled “Multimedia Processor Employing A Shared CPU-Graphics Cache” and Ser. No. ______ (attorney's docket number 04178) entitled “Hierarchical Texture Cache”, contemporaneously filed herewith and all herein incorporated by reference.