Claims
- 1. An apparatus for providing to an emulation controller at a pin boundary of an integrated circuit concurrent access to concurrent debug signal activity of first and second data processing cores embedded within the integrated circuit, comprising:
a first signal path from the first data processing core to a first pin of the integrated circuit for carrying a selected debug signal of the first data processing core to the first pin; a second signal path from the second data processing core to said first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to said first pin; and a third signal path from the second data processing core to a second pin of the integrated circuit for carrying said selected debug signal of the second data processing core to said second pin.
- 2. The apparatus of claim 1, including a first multiplexer having an output coupled to said first pin and having first and second inputs respectively coupled to said first and second data processing cores, wherein said first multiplexer defines a portion of said first signal path and a portion of said second signal path.
- 3. The apparatus of claim 2, including a second multiplexer having an output coupled to said second pin and having an input coupled to said second core, wherein said second multiplexer defines a portion of said third signal path.
- 4. The apparatus of claim 3, including a register coupled to a control input of one of said multiplexers for controlling operation thereof.
- 5. The apparatus of claim 4, wherein said register is provided within said integrated circuit.
- 6. The apparatus of claim 1, wherein one of said data processing cores is a DSP core.
- 7. The apparatus of claim 1, wherein one of said data processing cores is a microprocessor core.
- 8. The apparatus of claim 1, including a further signal path from the first data processing core to a further pin of the integrated circuit for carrying the selected debug signal of the first data processing core to the further pin.
- 9. The apparatus of claim 1, wherein said selected debug signal of the first data processing core is a trace signal.
- 10. The apparatus of claim 9, wherein the selected debug signal of the second data processing core is a trace signal.
- 11. The apparatus of claim 9, wherein the selected debug signal of the second data processing core is a trigger signal.
- 12. A data processing integrated circuit, comprising:
first and second embedded data processing cores for performing data processing operations; a first signal path from the first data processing core to a first pin of the integrated circuit for carrying a selected debug signal of the first data processing core to the first pin; a second signal path from the second data processing core to said first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to said first pin; and a third signal path from the second data processing core to a second pin of the integrated circuit for carrying said selected debug signal of the second data processing core to said second pin.
- 13. The integrated circuit of claim 12, wherein one of said processing cores is a DSP core.
- 14. The integrated circuit of claim 12, wherein one of said data processing cores is a microprocessor core.
- 15. The integrated circuit of claim 12, including a first multiplexer having an output coupled to said first pin and having first and second inputs respectively coupled to said first and second data processing cores, wherein said first multiplexer defines a portion of said first signal path and a portion of said second signal path.
- 16. The integrated circuit of claim 15, including a second multiplexer having an output coupled to said second pin and having an input coupled to said second core, wherein said second multiplexer defines a portion of said third signal path.
- 17. The integrated circuit of claim 16, including a register coupled to a control input of one of said multiplexers for controlling operation thereof.
Parent Case Info
[0001] This application claims the priority under 35 U.S.C. 119(e)(1) of the following co-pending U.S. provisional application No. 60/186,326 (Docket TI-30526) filed on Mar. 2, 2000; and No. 60/219,340 (Docket TI-30498) originally filed on Mar. 2, 2000 as non-provisional U.S. Ser. No. 09/515,093 and thereafter converted to provisional application status by a petition granted on Aug. 18, 2000.
Provisional Applications (2)
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Number |
Date |
Country |
|
60186326 |
Mar 2000 |
US |
|
60219340 |
Mar 2000 |
US |