Patent Application
20240154032
The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to enhanced edge termination structures for use in a semiconductor device, and methods of fabricating such structures.
Vertically conducting semiconductor devices in an integrated circuit (IC) include an active region that is surrounded by an edge termination region. In such vertical devices, the edge of the die is invariably at the same or similar voltage potential as that of a bottom of the device due primarily to saw damage when the device is singulated, or lack of a blocking junction at the edge of the device. Therefore, an edge termination region is a critical part of the device design to ensure lateral blocking of voltage between the active region and edge of the die.
Traditional charge balance or superjunction devices sometimes employ concentric charge balance regions within the edge termination region. However, for charge balance regions that are electrically isolating, this scheme is limited to lower breakdown voltages (e.g., typically less than 150 volts). This is due primarily to the limitation of breakdown voltage of the insulating regions contained within the charge balance regions. Therefore, there is a need for edge termination schemes that allow higher voltage operations (e.g., greater than 150 volts) while utilizing electrically isolated charge balance structures.
The present invention, as manifested in one or more embodiments, beneficially provides an enhanced edge termination structure for use in a charge balanced semiconductor device. In one or more embodiments, the edge termination comprises a plurality of edge termination trenches that point outwards from an active region of the device on at least two adjacent sides of the active region; that is, the edge termination trenches are orthogonal to the edge of the active region. The outward-facing edge termination trenches further provide a continuous conduction path, which is advantageous.
In accordance with an embodiment of the invention, an edge termination structure for use in a charge balanced semiconductor device includes a plurality of charge balance edge termination trenches formed in an edge termination region of the semiconductor device. The change balance edge termination trenches extend outwardly from an active region of the semiconductor device toward the edge termination region on at least two sides of the active region. The charge balance edge termination trenches are orthogonal to an edge of the active region. The edge termination structure further includes a plurality of semiconductor mesa regions, each of the mesa regions being between adjacent charge balance edge termination trenches.
In accordance with an embodiment of the invention, a charge balanced semiconductor device comprises an active region including at least one active element therein, and an edge termination region at least partially surrounding the active region when viewed in a plan view. The edge termination region includes at least one edge termination structure comprising a plurality of charge balance edge termination trenches formed in an edge termination region of the semiconductor device. The change balance edge termination trenches extend outwardly from the active region of the semiconductor device toward the edge termination region on at least two sides of the active region. The charge balance edge termination trenches are orthogonal to an edge of the active region. The edge termination structure further includes a plurality of semiconductor mesa regions, each of the mesa regions being between adjacent charge balance edge termination trenches.
In accordance with another embodiment of the invention, a method of forming an edge termination structure in a charge balanced semiconductor device includes: forming a plurality of charge balance edge termination trenches in an edge termination region of the semiconductor device, the change balance edge termination trenches being configured to extend outwardly from an active region of the semiconductor device toward the edge termination region on at least two sides of the active region, the charge balance edge termination trenches being orthogonal to an edge of the active region; and forming a plurality of semiconductor mesa regions, each of the mesa regions being between adjacent charge balance edge termination trenches.
In accordance with yet another embodiment of the invention, a method of forming a charge balanced semiconductor device includes: forming an active region including at least one active element therein; and forming an edge termination region at least partially surrounding the active region when viewed in a plan view, the edge termination region including at least one edge termination structure. In forming the edge termination structure, the method further includes: forming a plurality of charge balance edge termination trenches in an edge termination region of the semiconductor device, the change balance edge termination trenches being configured to extend outwardly from an active region of the semiconductor device toward the edge termination region on at least two sides of the active region, the charge balance edge termination trenches being orthogonal to an edge of the active region; and forming a plurality of semiconductor mesa regions, each of the mesa regions being between adjacent charge balance edge termination trenches.
As may be used herein, “facilitating” an action includes performing the action, making the action easier, helping to carry the action out, or causing the action to be performed. Thus, by way of example only and without limitation, in the context of a semiconductor fabrication methodology, steps performed by one entity might facilitate an action carried out by another entity to cause or aid the desired action(s) or steps to be performed. For the avoidance of doubt, where an actor facilitates an action by other than directly performing the action, it is assumed that the action is nevertheless performed by some entity or combination of entities.
Techniques of the present invention can provide substantial beneficial technical effects. By way of example only and without limitation, edge termination structures and/or methods of fabricating edge termination structures according to embodiments of the invention may provide one or more of the following advantages:
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
Non-limiting and non-exhaustive embodiments of the present invention will be described with reference to the following drawings which are presented by way of example only, wherein like reference numerals (when used) indicate corresponding elements throughout the several views unless specified otherwise, and wherein:
It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments.
Principles of the present invention, as manifested in one or more embodiments thereof, will be described herein in the context of illustrative edge termination structures for use in a charge balanced semiconductor device, and methods for fabricating such structures, which have beneficial application, for example, in a power device or power system environment for providing direct current (DC)-DC or alternating current (AC)-DC conversion. It is to be appreciated, however, that the invention is not limited to the specific structures and/or methods illustratively shown and described herein. Rather, it will become apparent to those skilled in the art given the teachings herein that numerous modifications can be made to the embodiments shown that are within the scope of the claimed invention. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.
In vertically conducting devices, an edge 110 of the die 100 is invariably at the same or similar voltage potential as that of a bottom surface of the device, due primarily to saw damage when the device is singulated or lack of a blocking junction at the edge of the device. Therefore, there is a need to not only block voltages between the top and bottom surfaces of the vertical device, but also to block voltages laterally between the active region 102 of the device and edge 110 of the die; the edge termination region 104 is the region in the device that provides this lateral voltage blocking capability.
Edge termination structures that employ charge balance regions that include some type of electrical isolation are particularly challenging, as the electrical isolation can undesirably restrict the flow of current needed to establish the required change in voltage between the active region 102 and edge termination region 104 of the die. For example,
If electrically “floating” regions are created due to the electrical isolation of these charge balance and mesa regions 206, 208, then their potentials will be determined initially by capacitive coupling, and in steady state, due primarily to leakage current paths, each of these regions will have an indeterminate voltage over time. The voltage at the surface of these “floating” regions will converge in time to the same potential as the bottom surface of the die to which they remain connected.
Traditionally, by using concentric charge balance regions 206 in the edge termination region 204, electrically isolated charge balance regions would result in the full voltage being applied across the first charge balance region, rather than being distributed across all structures in the edge termination region; this first edge termination mesa 208 is floating (i.e., not directly connected to the surface of the active region surface), and will therefore drift to the same potential as the bottom surface of the die. Hence, there is a limitation for charge balance regions that have electrical isolation where the maximum blocking voltage is limited to the blocking voltage of a single charge balance region.
Advantageously, embodiments of the present invention provide a means for achieving charge balance in the edge termination region while simultaneously ensuring the flow of currents (e.g., capacitive and leakage currents) required to make a functioning edge termination structure, as will be described in further detail herein below. Illustrative device structures in which aspects of the invention are particularly well-suited include, but are not limited to, the devices shown in
By way of example only and without limitation,
In
It is to be appreciated that although several exemplary p-n diode configurations are depicted in
In
As previously stated, each of the vertical power devices illustrated in
In this illustrative embodiment, the active region 402 includes a plurality of charge balance regions 406, which may be implemented using trenches. The trenches 406 extend horizontally and continuously, in the same orientation, through the active region 402 and into the edge region 404. In one or more embodiments, each of the charge balance trenches 406 preferably comprises a high-k insulating material (although the charge balance trenches may alternatively comprise a semiconductor material, in some embodiments) and is spaced laterally from adjacent trenches by a semiconductor mesa 408 (e.g., in a manner consistent with the arrangement of the trenches 206 and mesas 208 shown in
As previously stated, for structures employing conventional trenches that are continuous in nature with electrical isolation, this arrangement creates floating mesas with no path for current flow in the edge region 404 to the top surface of the active region 402, which is problematic. A solution to this problem, according to one or more embodiments of the invention, is to incorporate slots (or gaps or the like) 410 in the trenches 406 which facilitates current flow and ensures that there is a current path for all parts of the edge region 404 to the top surface of the active region 402. More particularly, the slots 410 may be configured to provide an electrical connection between prescribed points, regions or areas in the edge region 404 and the top surface of the active region 402. Preferably, the slots 410 in the trenches 406 are staggered, such that the slots formed in one trench do not align laterally (i.e., in a plane parallel to an upper surface of the IC device 400) with slots in an adjacent trench. Since the trenches 406 may affect charge balance, forming the trenches with offset slots may provide a more uniform structure and hence improved breakdown voltage in the IC device 400. Forming trenches with offset slots may have an added effect of increasing resistance in the edge termination region.
In an edge termination scheme according to one or more embodiments of the invention, the trenches 504 are arranged so that they are orthogonal to an edge of the active region 502 on all four sides of the active region; that is, the trenches 504 in the medial portions of the edge region are arranged so that they extend outwardly in an x-axis or y-axis direction (i.e., parallel to an upper surface of a substrate (not explicitly shown) in which the IC device 500 is formed) from the active region 502 toward the edge region. In other embodiments, the trenches 504 may be configured to extend outwardly from the active region 502 toward the edge region on at least one side (i.e., one, two, three or four sides) of the active region 502, the trenches 504 being orthogonal to an edge of the active region 502.
The outward-facing trenches 504 may provide a continuous current conduction path for mesa regions 506 in the IC device 500, which can be advantageous. For example, in edge termination schemes like the illustrative structure 325 shown in
The IC device 500 may include one or more corner structures 508 formed, each of the corner structures 508 being disposed in a corresponding corner of the edge region (i.e., between adjacent sides of the IC device 500), such that the plurality of trenches 504 in each medial portion of the edge region are between two corner structures 508. Each of the corner structures 508, in one or more embodiments, comprises a plurality of trenches (not explicitly shown, but implied), which may be consistent with the trenches 504. The trenches in the corner structures are preferably arranged differently compared to the trenches 504 in the medial portions of the edge region, however a similar design philosophy of ensuring a continuous conduction path for all n-type silicon regions (for devices employing an n-type epitaxial layer) between the active region 502 and the edge of the IC device 500 is preferably followed. It is to be appreciated that embodiments of the invention contemplate numerous edge termination designs for the corner structures 508, some examples of which will be described in further detail herein below.
Optionally, the IC device 500, in some embodiments, may include a boundary trench (i.e., peripheral isolation trench) surrounding a periphery of the device (not explicitly shown, but implied), consistent with the arrangement shown in
Some benefits of edge termination designs according to one or more embodiments of the present disclosure may include improved stability of breakdown voltage in the device due, at least in part, to the elimination of floating mesas, since all edge termination regions may have a direct conduction path to the active area surface (e.g., anode for a diode, source for a MOSFET), and (for some embodiments) a direct connection of the charge balance regions to the active area surface, and hence any p-type region created by the charge balance region. Conventional edge termination schemes cannot achieve these benefits. Moreover, edge termination designs according to one or more embodiments of the invention are compatible with other known edge termination features that are used to improve the effectiveness of edge termination structures, including the use of inner field plates, outer field plates, junction termination extensions (JTEs), variable lateral diffusion (VLD), and the inclusion of a charged or resistive layer on the surface of the edge termination structure, among other schemes.
By way of example only and without limitation or loss of generality,
If the device shown in
The corner structure 600 may be configured to provide an interface between facing end portions of a first subset of charge balance edge termination trenches (i.e., vertical trenches) 608 extending in a first direction (e.g., y-axis direction) from a first side of the active region 602 and corresponding end portions of a second subset of charge balance edge termination trenches (i.e., horizontal trenches) 610 extending in a second direction from a second side of the active region 602 adjacent to the first side of the active region. Stated differently, the corner structure is configured to provide an interface region in which corresponding end portions of the trenches 608 and 610 extending outwardly from adjacent sides of the active region 602 meet.
As apparent from
In the corner structure 600 of the edge termination region 604, facing ends of the horizontal trenches 610 and the vertical trenches 608 may meet at an interface represented by line 616. In some embodiments, the interface 616 between facing end portions of the trenches 608 and 610 may be angled (e.g., about 45 degrees) relative to corresponding edges of the adjacent first and second sides of the active region 602, although embodiments of the invention are not limited to any specific angle. In one or more embodiments, an end of each of the horizontal trenches 610 is aligned with a mesa between adjacent vertical trenches 608, and vice versa, in a “zipper” configuration; that is, corresponding facing ends of the vertical trenches 608 and horizontal trenches 610 may be offset relative to one another. This allows the mesas to be electrically connected to the active region 602. Note, that in
With regard to the mesas, it is to be understood that a continuous path along a mesa is not necessarily required for the mesas to be electrically connected to the active region 602. The mesas just need to have a path to a place where they can share electrical connection to the active region 602. For example, in
The corner structure 600, in one or more embodiments, may further comprise a continuous boundary trench 618 which follows an outside perimeter of the IC device in which the corner structure 600 is formed. While the boundary trench 618 may be optional, it does provide additional benefits. For example, for a RESURF (reduced surface field) structure, the boundary trench 618 may ensure that a bottom potential is at a surface on the outside of the edge termination region, which ensures that the entire voltage is dropped in the defined edge termination region; that is, the trench boundary functions as a traditional channel stopper. For trench photolithography and etch uniformity, multiple “dummy” boundary trenches may be optionally employed.
A further benefit of using this boundary trench 618 is that this trench can also support some voltage and hence improve the voltage blocking performance of the overall edge termination structure in which the corner structure 600 resides. How effective this is may depend on one or more design factors, such as the spacing and/or the width of this trench, among other factors. Note, that this boundary trench 618 is preferably fabricated using the same processing as the edge trenches, but this does not have to be the case, especially if a boundary trench having different dimensions than the edge trenches (e.g., wider, deeper, etc.) is desired.
The boundary trench 618 is preferably, but not necessarily, separated from the vertical and horizontal trenches 608, 610 in the edge termination region 604 by a trench end gap 620. The width of the trench end gap 620 (i.e., spacing between the end of the trenches 608, 610 and the boundary trench 618) may be important. For example, if the trench end gap 620 is too wide (in a plan view), then a bottom potential can reach the surface due to a lack of charge balance in this region. However, a smaller width for the trench end gap 620 can be beneficial in that with a small gap, some additional voltage can be dropped across the last trench, thereby improving breakdown voltage in the device or allowing a narrower edge termination. As the terms are used herein, a “small” gap is intended to refer to a gap size that is less than the mesa width, and a “wide” gap is intended to refer to a gap size that is greater than the mesa width. In one or more embodiments, the trench end gap 620 can be zero (i.e., the outward-facing trenches 608, 610 extend directly into the boundary trench 618).
In terms of function of the trench end gap 620, it is generally desirable to maintain some level of charge balance at the end of the structure, and by having a small gap the level of charge balance in that region can be controlled; if the gap is zero, there may be too much charge (unless the peripheral trench does not contribute materially to the charge balance)—so the trench end gap 620 may function, in some ways, like the gap 612 between the horizontal trenches 610 and the first vertical trench 614. Furthermore, sometimes having a T-junction makes fabrication more problematic; etching and filling this junction is different as it has a wider geometry. Note, that in
The active region 704 includes a plurality of charge balancing horizontal trenches 708 (i.e., oriented in an x-axis direction) which extend continuously through the guard ring 702 and into a portion of the edge termination region 706. The edge termination region 706 in the corner structure 700 further includes a plurality of charge balancing vertical trenches 710 (i.e., oriented in a y-axis direction) which are separate and orthogonal to the active region trenches 708. In one or more embodiments, to minimize current crowding of any current flowing within a termination mesa, a portion of at least a subset of the vertical trenches 710 may originate in the active region 704 itself, passing through the guard ring 702 and into the edge termination region 706. It is to be appreciated that embodiments of the invention are not limited to the specific type of material forming the trenches or the direction in which the trenches are oriented.
In a manner similar to the exemplary corner structure 600 shown in
In one or more embodiments, the illustrative corner structure 700 employs one or more field plates to facilitate distribution of the electric field in the device, among other benefits. Field plates are often used to reduce high electric fields that can occur on the guard ring. Edge termination schemes employing field plates will be known to those skilled in the art. With continued reference to
In one or more embodiments, the corner structure 700 includes a junction termination extension (JTE) implant 716 formed in at least a portion of the edge termination region 706, proximate an upper surface of the edge termination region. The JTE implant 716 is preferably disposed between the guard ring 702 and an outer periphery of the horizontal and vertical trenches 708, 710 in the edge termination region 706. The JTE implant 716 assists in distributing the voltage laterally across the edge termination region 706, thereby helping to minimize electric field peaks and thus beneficially maximize breakdown voltage in the device. An insulating layer 718 preferably electrically isolates the JTE implant 716 from the inner field plate 712. Optionally, the corner structure 700 may include a boundary trench 720 surrounding a periphery of the IC device, in a manner consistent with the boundary trench 618 shown in
It is to be appreciated that a similar effect to a JTE implant can be achieved by employing a layer incorporating fixed charge at a concentration sufficient to invert the silicon surface above the silicon surface.
In some embodiments, the IC device includes an edge termination region that utilizes a boundary trench surrounding a perimeter of the device. By way of example only,
Similar to the device shown in
In a manner consistent with the IC device shown in
The boundary trench 814 is preferably separated from the horizontal and vertical trenches 808, 810 in the edge termination region 802 by a trench end gap 816. The width of the trench end gap 816 (i.e., spacing between the end of the trenches 808, 810 and the boundary trench 814) is important. If the trench end gap 816 is too wide, then a bottom potential can reach the surface due to a lack of charge balance. While this can still work effectively, a smaller trench end gap 816 can be beneficial in that with a small gap, some voltage can be dropped across the last trench (i.e., edge termination trenches 808, 810 closest to the boundary trench 814), thereby improving breakdown voltage in the device or providing a narrower edge termination.
In one or more embodiments, a JTE implant 818 may be formed in at least a portion of the edge termination region 802, proximate an upper surface of the edge termination region and covering all or at least a portion of the edge termination trenches 808, 810. The JTE implant 808 is preferably disposed between the guard ring 806 and the boundary trench 814 in the edge termination region 802. The JTE implant 818 assists in distributing the voltage laterally across the edge termination region 802, thereby helping to minimize electric field peaks and thus beneficially maximize breakdown voltage in the device.
A gap 820 between an outer edge of the JTE implant 818 and the boundary trench 814 has been found to play an important role in controlling breakdown voltage in the IC device. If the JTE gap 820 is too small (i.e., the outer edge of the JTE implant 818 is disposed too close to the boundary trench 814), there is a loss of breakdown voltage, but this preferred gap size may depend on other factors as well, such as JTE implant dose and length of the termination region. In one or more embodiments, the JTE gap 820 is formed similar in length to a thickness of the epitaxial layer (e.g., about 10 μm-20 μm for devices with breakdown voltages in a range of about 200-400 volts, or a range of about 0.5× to 2× the epitaxial layer thickness).
With continued reference to
An alternative to using a JTE implant having a substantially constant doping concentration, as in the illustrative IC device shown in
With continued reference to
As previously described in connection with the illustrative corner structure 600 shown in
The active region 1002 includes a plurality of vertical trenches 1008. The edge termination region 1004 includes a first plurality of trenches 1010, which are vertically oriented (i.e., along a y-axis direction), and a second plurality of trenches 1012, which are oriented orthogonally relative to the vertical trenches 1010 (i.e., horizontally, or along an x-axis direction). In this illustrative embodiment, the vertical trenches 1010 in the edge termination region 1004 are distinct (i.e., disconnected) from the vertical trenches 1008 in the active region 1002.
In the corner structure 1000, a trench 1014 is formed in a break between the vertical active region trenches 1008 and the vertical edge termination region trenches 1010. The trench 1014 is oriented orthogonally (i.e., horizontally) in relation to the vertical trenches 1008, 1010. While the trench 1014 may not be necessary for operation of the IC device, it can assist in charge balancing the region where the break between the vertical active region trenches 1008 and edge termination trenches 1010 occurs.
One beneficial reason to separate the vertical active region trenches 1008 from the vertical edge termination region trenches 1010 is that it allows a different pitch and/or different trench or mesa width to be used for the active region and edge termination region trenches. Edge termination trenches tend to have a lower breakdown voltage than the active region trenches due at least in part to a curvature of the potential lines. Therefore, edge termination design, in one more embodiments, seeks to ensure that the breakdown voltage of the edge termination region is as close as possible to the active region breakdown voltage. A consequence of this breakdown voltage mismatch is that under high current avalanche breakdown, the IC device is vulnerable to failure in the edge termination region (typically, corners are more vulnerable than edges).
In a charge balance structure, the degree of charge balance that is targeted will impact the breakdown voltage. Thus, by having different levels of charge balance in the active and edge termination regions 1002, 1004 (and possibly also different levels of charge balance in the corners of the device), one can ensure that the breakdown voltage in the active region has the lowest breakdown voltage. As an example, the edge termination region can be made “overcharged,” which can increase breakdown voltage under avalanche breakdown thereby ensuring that under avalanche conditions, the breakdown voltage in the edge termination region will reach that of the active region to ensure uniform current sharing. Note, that when a region is “overcharged,” as the term is used herein, it is intended to mean that the charge in the field balancing region (i.e., trench) is greater than the charge in the voltage sustaining/mesa region.
There are various ways to arrange the break between the active region trenches 1008 and the edge termination region trenches 1010 that are contemplated by the present invention. By way of example only and without limitation,
Turning now to
With reference now to
An IC device configured in the manner shown in
Another factor that can affect breakdown voltage in the IC device is the width and/or depth of the trenches in the active region and/or edge termination region of the device. If the active region trenches do not extend fully through the drift region to the substrate, which is often the case, then achieving deeper trenches in the edge termination region can advantageously increase breakdown voltage of the edge termination structure. In this regard, it is important to note that breakdown voltage is proportional to how far the trenches extend vertically through the drift region. A drift region is generally considered to be the part of a semiconductor device that is used to accommodate the majority of any applied reverse bias and is commonly created by epitaxial growth in vertical devices. In this particular case, it is the region that is sandwiched between the charge balance regions and depicted as the n-type semiconductor material layer 304 in
With reference in particular to
By making the edge termination region trenches 1304 wider, a deeper trench d2 can be achieved in the edge termination region (where d2>d1), thereby beneficially increasing breakdown voltage in the edge termination region. Note, that by using the technology according to one or more embodiments of the invention, it can be shown that trench width can affect the actual charge, so this approach also beneficially enables a level of charge differentiation between the active region and edge termination region, particularly when using atomic layer deposition (ALD) for filling the trenches.
It is to be appreciated that one or more of the unique features according to aspects of the invention can be combined to achieve further performance enhancements. By way of example only and without limitation, the mesa width variation features illustrated in the exemplary charge balanced IC device shown in
With continued reference to
In order to control the charge balance in the edge termination region relative to the active region, a plurality of slots or breaks 1410 can be placed in at least a subset of the edge termination region trenches 1404, in one or more embodiments. Adding breaks 1410 to the edge termination trenches 1404 may improve susceptibility to failure with high currents by allowing avalanche current flowing in one mesa to spread to neighboring mesas. The breaks 1410 in the edge termination trenches 1404 can also beneficially assist in relieving wafer stress introduced by the deep trenches.
By combining trench breaks with multiple pitch variations in the edge termination region, a graded charge balance can be achieved throughout the edge termination region.
Although in this illustrative embodiment, the trench pitch gets progressively smaller across the edge termination region as the trenches extend out from the active region of the IC device 1500, it is to be appreciated that in some embodiments, an opposite pitch variation scheme may be employed, such that the trench pitch gets progressively wider across the edge termination region as the trenches extend out from the active region.
As previously stated in conjunction with
The trenches in the edge termination region 1604, both those trenches aligned along the same direction as the trenches in the active region 1602 as well as those edge termination region trenches oriented orthogonally relative to the active region trenches, extend continuously through the guard ring 1606 and a prescribed distance into the active region 1602. This configuration allows a larger contact area to the mesas in the active region. Furthermore, this configuration moves any charge imbalance and/or breakdown voltage weakness, caused primarily by the change in trench orientation, into the active region 1602 which provides superior contact and metal coverage, thereby assisting in current spreading and cooling.
The outward-facing trenches in the edge termination region of the exemplary IC device 1600 shown in
Alternatively, the illustrative corner structure 1750 shown in
In one or more embodiments of the invention, another alternative to the “zipper” corner configuration described, for example, in connection with
With reference to
Since the corners of the IC device often exhibit lower breakdown voltage compared to other areas of the device, one objective in designing the parquet corner structure 1800 is to ensure that a resistance of the current path in the corner structure is higher than in the other areas of the device. This resistance “ballasting” approach means that there will be a voltage drop across these higher resistance paths, thereby increasing the breakdown voltage at higher currents such that the breakdown voltage in the other areas of the device will be reached.
The parquet corner structure 1800 is designed to replace the zipper corner configuration previously described, but from a design perspective the corner is really based on the curvature of the guard ring 1802. Therefore, performance enhancements can be achieved through improved “ballasting” for the whole corner structure and beyond using an extended parquet corner configuration. For instance,
Like the parquet corner structure 1800 shown in
In the extended parquet corner structure 1900, outward-facing trenches are modified compared to the arrangement shown in
In one or more embodiments, each of at least a subset of the charge balance trenches 2006 may be at least partially filled with a high-k insulating material (although the charge balance trenches 2006 may alternatively comprise a semiconductor material, in other embodiments) and is spaced laterally (in the y-axis direction) from adjacent trenches by a semiconductor mesa 2010 (e.g., in a manner consistent with the arrangement of the trenches 206 and mesas 208 shown in
The illustrative IC device 2000 may include a termination structure on a top edge (and a bottom edge, not explicitly shown) of the IC device 2000 in a y-axis direction intersecting the x-axis direction. In some embodiments, the top edge termination structure may comprise a single wide trench 2012 (i.e., a top edge termination trench) extending along a periphery of the IC device 2000 in the x-axis direction, parallel to the charge balance trenches 2006. The top edge termination trench 2012 may be adjacent to a topmost one of the charge balance trenches 2014 in the y-axis direction. The IC device 2000 may further include a boundary trench 2016 extending in a y-axis direction along a left side 2008 of the IC device, between the top edge termination trench 2012 and a bottom edge termination trench (not explicitly shown), perpendicular to the charge balance trenches 2006 and top edge termination trench 2012.
It is to be appreciated that, although not explicitly shown in
In some embodiments, one or more JTE implants 2018 may be formed in at least a portion of the edge termination region 2004, proximate an upper surface of the edge termination region (in the z-axis direction) and covering all or at least a portion of the trenches 2006. The JTE implants 2018 may be disposed between the top edge termination trench 2012 and the bottom edge termination trench (not explicitly shown) and extending in the y-axis direction in the edge termination region 2004. As previously described, the JTE implants 2018 may assist in distributing the voltage laterally across the edge termination region 2004 (i.e., in the x-axis direction and/or y-axis direction), thereby helping to minimize electric field peaks and thus maximize breakdown voltage in the IC device 2000.
Although not explicitly shown for enhanced clarity, a conductive layer (e.g., metal) may be formed over at least a subset of portions of the charge balance trenches 2006 in the edge termination region 2004 in the IC device 2000. In one or more embodiments, the conductive layer may cover the entire edge termination region 2004, including the top edge termination trench 2012 and the bottom edge termination trench (not explicitly shown), the left side boundary trench 2016 and right side boundary trench (not explicitly shown), the JTE implants 2018, and at least the portions of the charge balance trenches 2006 extending into the edge termination region 2004. The metal layer may serve as a field plate configured to facilitate the distribution of electric fields in the IC device 2000 for increasing breakdown voltage in the device, among other benefits.
Although the overall fabrication methods and the structures formed thereby are entirely novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to those having ordinary skill in the relevant arts given the teachings herein. Moreover, many of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008; and R. K. Willardson et al., Processing and Properties of Compound Semiconductors, Academic Press, 2001, which are both hereby incorporated herein by reference in their entireties for all purposes. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would also fall within the scope of the invention.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such semiconductor devices may not be explicitly shown in a given figure to facilitate a clearer description. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual device.
In one or more embodiments, formation of the exemplary device structures described herein may involve deposition of certain materials and layers by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, including, for example, plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions can be epitaxial processes, and the deposited material can be crystalline. In one or more embodiments, formation of a layer can be achieved using a single deposition process or multiple deposition processes, where, for example, a conformal layer is formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill is formed by a second process (e.g., CVD, electrodeposition, PVD, etc.); the multiple deposition processes can be the same or different.
As used herein, the term “semiconductor” may refer broadly to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor material, or it may refer to intrinsic semiconductor material that has not been doped. Doping may involve adding dopant atoms to an intrinsic semiconductor material, which thereby changes electron and hole carrier concentrations of the intrinsic semiconductor material at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor material determines the conductivity type of the semiconductor material.
The term “metal,” as used herein, is intended to refer to any electrically conductive material, regardless of whether the material is technically defined as a metal from a chemistry perspective or not. Thus “metals” as used herein will include such materials as, for example, aluminum, copper, silver, gold, etc., and will include such materials as, for example, graphene, germanium, gallium arsenide, highly-doped polysilicon (commonly used in most MOSFET devices), etc. This is to be distinguished from the definition of a “metal” from a physics perspective, which usually refers to those elements having a partially filled conduction band and having lower resistance toward lower temperature.
The term “gate” as used herein may refer broadly to a structure used to control output current (i.e., flow of carriers in a channel) of a semiconducting device through the application of electrical or magnetic fields.
The term “crystalline” as used herein may refer broadly to any material that is single-crystalline or multi-crystalline (i.e., polycrystalline).
The term “non-crystalline material” generally refers to any material that is not crystalline, including any material that is amorphous, nano-crystalline, or micro-crystalline.
The term “intrinsic” as used herein may refer broadly to any material which is substantially free of dopant atoms, or material in which the concentration of dopant atoms is less than a prescribed amount, such as, for example, about 1015 atoms/cm3.
As used herein, the term “insulating” may generally denote a material having a room temperature conductivity of less than about 10−10 (Ω-m)−1.
As used herein, “p-type” may refer broadly to the addition of impurities to an intrinsic semiconductor material that creates deficiencies of valence electrons. In a silicon-containing material, examples of p-type dopants (i.e., impurities) may include, but are not limited to, boron, aluminum, gallium and indium.
As used herein, “n-type” may refer broadly to the addition of impurities that contribute free electrons to an intrinsic semiconductor material. In a silicon-containing material, examples of n-type dopants may include, but are not limited to, antimony, arsenic and phosphorous.
The term “gate dielectric” as used herein may refer broadly to insulating materials such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-dielectric constant (high-k) materials, or any combination of these materials. Non-limiting examples of high-k materials may include, for example, metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, ceramics, etc. High-k materials may further include dopants such as lanthanum, aluminum, etc.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “atop,” “above,” “on” or “over” another element, it is broadly intended that the element be in direct contact with the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, it is intended that there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Furthermore, positional (i.e., directional) terms such as “above,” “below,” “upper,” “lower,” “under,” and “over” as may be used herein, are intended to indicate relative positioning of elements or structures to each other as opposed to absolute position. Thus, for example, if a particular element is described as having a “top surface,” that same top surface may be considered to be a “bottom surface” of the element when that element is rotated by 180 degrees.
At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures and/or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Any of the exemplary structures illustrated in the accompanying figures, or portions thereof, may be part of an integrated circuit. Integrated circuits so manufactured are considered part of this invention.
Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, in packaged form, or incorporated as parts of intermediate products or end products that benefit from having enhanced edge termination structures therein (e.g., power IC devices) formed in accordance with one or more embodiments of the invention.
An integrated circuit in accordance with aspects of the present disclosure can be employed in essentially any application and/or electronic system involving enhanced breakdown voltage structures, such as, but not limited to, power MOSFET devices, Schottky diodes, etc. Suitable systems and applications for implementing embodiments of the invention may include, but are not limited to, AC-DC and DC-DC conversion, motor control, and power supply OR-ing (“OR-ing” is a particular type of application that parallels multiple power supplies to one common power bus in a redundant power system architecture). Systems incorporating such integrated circuits are considered part of this invention. Given the teachings of the present disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
The illustrations of embodiments of the invention described herein are intended to provide a general understanding of the various embodiments, and they are not intended to serve as a complete description of all the elements and features of apparatus and systems that might make use of the structures and semiconductor fabrication methodologies described herein. Many other embodiments will become apparent to those skilled in the art given the teachings herein; other embodiments are utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. The drawings are also merely representational and are not necessarily drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Embodiments of the invention are referred to herein, individually and/or collectively, by the term “embodiment” merely for convenience and without intending to limit the scope of this application to any single embodiment or inventive concept if more than one is, in fact, shown. Thus, although specific embodiments have been illustrated and described herein, it should be understood that an arrangement achieving the same purpose can be substituted for the specific embodiment(s) shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will become apparent to those of skill in the art given the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
The abstract is provided to comply with 37 C.F.R. § 1.72(b), which requires an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in less than all features of a single embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.
Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of embodiments of the invention. Although illustrative embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to those precise embodiments, and that various other changes and modifications are made therein by one skilled in the art without departing from the scope of the appended claims.
This application claims priority under 35 U.S.C. § 119 to Provisional Application No. 63/420,339, filed on Oct. 28, 2022, entitled “Enhanced Edge Termination for a Charge Balanced Semiconductor Device and Method of Fabrication Thereof,” the disclosure of which is incorporated by reference herein in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63420339 | Oct 2022 | US |
