Patent Application
20050145922
Not Applicable
Not Applicable
1. Technical Field
This invention relates in general to semiconductor circuits and, more particularly, to an EEPROM and FLASH EEPROM design.
2. Description of the Related Art
Many mobile devices, such as mobile phones, PDAs (personal digital assistants), mobile computers and music players (such as MP3 players) rely on non-volatile semiconductor memory to maintain data and programs in the event of insufficient battery power. The most popular forms of semiconductor non-volatile memory are EPROMs (erasable programmable read only memory), which are erasable using UV light and EEPROMs (electrically erasable programmable read only memory), which are electrically erasable. One variation of an EEPROM is the FLASH EEPROM, which allows multiple memory cells to be erased at one time.
One time programmable EPROMs are relatively compact, but can only be erased using UV light, which makes them unsuitable in many situations. Early EEPROMs were fabricated using a multi-polysilicon process, forming a control gate above a floating gate. This process required multiple masks, longer process turnaround times, lower yields, higher costs, and lower reliability. More recently, a single polysilicon approach has been developed. A single polysilicon approach is especially suited for providing an EEPROM array in an integrated solution along with a processor and dynamic memory, where a second polysilicon would not be otherwise needed.
A problem with the single polysilicon process is the larger size of the cell. This can be a significant problem in an integrated solution, where other components have large die requirements.
Accordingly, a need exists for an EEPROM with a smaller cell size.
In the present invention, an electronically erasable read only memory includes a capacitor comprising a diffusion layer of a first conductivity type formed in well of a second conductivity type, an insulating layer overlying the diffusion layer and a floating gate overlying the diffusion layer. A MOS transistor comprises first and second active regions formed in the well, adjacent to an extended portion of the floating gate.
The present invention provides significant advantages over the prior art. First, the memory cell is very compact compared to other EEPROMs which require multiple wells. Second, the process is compatible with many other process technologies, without requiring additional polysilicon layers. Third, the cell can be programmed using either Fowler-Nordheim tunneling or hot electron injection. Fourth, the cell supports flash erasure.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
a and 1b illustrate a plan view and a cross-sectional side views of a prior art EEPROM memory cell;
The present invention is best understood in relation to
a and 1b illustrate a plan view and a cross-sectional side views of a prior art EEPROM memory cell 10. An NMOS transistor 12 formed within a p-well 14 includes n+ type source and drain active regions 16 and 18, respectively, and a polysilicon floating gate 20 separated from the p-well 14 by gate oxide layer 22. The floating gate 20 extends into a capacitor 24. The floating gate 20 overlies an n-well 28, the floating gate being separated from the n-well 28 by gate oxide layer 22. An n+ active region 30 is formed in the n-well 28 in areas not underlying the floating gate 20. An erase gate 32 is formed as an n+ region 34 within an n-well 36. A backgate 38 is formed as a p+ region 40 within a p-well. 42. N-wells and p-wells are separated by field oxide regions 44.
In operation, the EEPROM memory cell 10 is programmed using Fowler-Nordheim electron tunneling by applying a voltage of approximately 13 volts to the control gate (CG), while leaving the erase gate (EG), source 16, drain 18 and backgate 38 grounded. The floating gate 20, oxide layer 22 and n+ active region 30. (along with the n-well 28) form a capacitor 24. Hence, the increase in the voltage at the control gate CG (one plate of capacitor 24) causes an increase in the voltage at the floating gate 20 (the other plate of capacitor 24). The floating gate voltage will rise to about ten volts. Through Fowler-Nordheim electron tunneling, electrons will be drawn from the grounded areas beneath the floating gate 20 to the floating gate itself. When the control gate (CG) is returned to ground, the floating gate will remain at around 2-3 volts.
To read from the EEPROM memory cell 10, a voltage of zero to three volts is placed on the control gate (CG) and a low voltage of around one volt is placed on the drain 18. If the memory cell has been programmed, the voltage on the floating gate will cause an inversion region between the source 16 and drain 18, causing current to flow. If not, current will not be able to flow from source to drain. By measuring the voltage at the source, it can be determined whether or not the memory cell 10 is programmed.
To erase the EEPROM memory cell 10, thirteen volts is applied to the erase gate (EG). Since the erase gate has only a small capacitive relationship with the floating gate, the higher voltage at the active region 34 will draw electrons from the floating gate 22 into the active region 34, thereby removing the charge on the floating gate.
A problem with an EEPROM memory cell of the type shown in
An EEPROM memory cell 50 (which can also be arrayed and used in a flash EEPROM unit) 50 is shown in
Referring to
The memory cell is shown in a schematic view in
In operation, the floating gate potential serves to invert region under the floating gate 60 to p-type, thus forming a capacitor within a small area; the VTN p− diffused region assists in defining a p region under the floating gate. The memory cell 50 can be programmed either using channel hot electron (CHE) injection or Fowler-Nordheim electron tunneling. Using a CHE approach, −10 volts is applied to the control gate (CG), −6 volts is applied to the drain 58, with the source 56 and backgate 74 grounded. The voltage on the control gate pulls down the voltage on the floating gate 60, due to the capacitance between the floating gate 60 and the p+ active region 70 and the p− diffused region 68. The voltage on the drain 58 causes a current between source and drain, with electrons being attracted to the floating gate 60, the electric field across the control capacitor to aid injection into the floating gate. Hence the floating gate will acquire a voltage which creates an inversion layer between source 56 and drain 58. Alternatively, CHE injection can also be achieved by applying seven volts to the backgate and source relative to the control gate and drain. This is shown in
Using Fowler-Nordheim electron tunneling, a voltage of −13 volts is applied to the control gate (CG), with the source 56, drain 58 and backgate 74 remaining grounded. The voltage on the control gate pulls down the voltage on the floating gate 60, due to the capacitance between the floating gate 60 and the p+ active region 70 and the p− diffused region 68. The difference in voltage between the floating gate 60 and the grounded areas underlying the floating gate attracts electrons to the floating gate 60. Once again, the floating gate will acquire a voltage which creates an inversion layer between source 56 and drain 58.
The memory cell can be read using a voltage of −3.3 volts on the control gate (CG), and −1 volt on the drain. Alternatively, as shown in
To erase the memory cell 50 using Fowler-Nordheim electron tunneling, a voltage of −13 volts is applied to the drain 58, with the source floating. The control gate (CG) and backgate 72 are grounded. In prior art EEPROMs, a voltage as high as −13 volts would cause junction breakdown; however, with the p− diffused region, the junction breakdown threshold is increased. Therefore, the increased voltage on the drain will cause electrons from the floating gate 60 to flow to the drain 58, thereby discharging the floating gate 60. By leaving the source 56 floating, voltage applied to the drain-will not be reduced by a current between source and drain. In a memory cell array, selected cells can be erased by applying the −13 volts only to the drains of cells 50 to be erased.
Alternatively, the memory cell 50 can be erased using Fowler-Nordheim tunneling by applying a 13 volt signal on the backgate 74 with the control gate grounded, as shown in
It should be noted that the voltages set forth above can vary based on the processing technology used.
An example of a process flow for forming the memory cell 50 in a P type substrate is as follows:
The present invention provides significant advantages over the prior art. First, the memory cell 50 is very compact compared to other EEPROMs which require multiple n-wells. In typical structure such as that shown in
Second, the process is compatible with many other process technologies, without requiring additional polysilicon layers, which makes it particularly suited for integration with other devices, such as processors. Third, the cell can be programmed using either Fowler-Nordheim tunneling or hot electron injection. Fourth, the cell supports flash erasure.
It should be noted that while the present invention has been described in connection with p-type diffusion regions formed in an n-well, the principles described herein could be equally applied to diffusions of opposite polarities (i.e., an isolated p-well with an n-type control capacitor, with an NMOS transistor).
Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.
