Claims
- 1. An in-system programming/erasing/verifying structure for non-volatile programmable logic devices including:
- a data input pin;
- a data output pin;
- an instruction register;
- a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, wherein said ISP register includes an address field, a data field, and an n-bit status field; and
- a controller for synchronizing the clocking of said instruction register and said plurality of data registers.
- 2. The structure of claim 1 further including a multiplexer for selectively providing bits from one of said address field and said data field to said n-bit status field.
- 3. An in-system erasing method for a non-volatile programmable logic device including:
- shifting a erase instruction into an instruction register, thereby selecting an ISP register as the active data register;
- shifting an address and status code into said ISP register;
- initiating an erasing pulse at said address;
- terminating said erasing pulse; and
- automatically performing a verify operation on said address.
- 4. The in-system erasing method of claim 3 wherein said verify operation determines whether a selected memory cell is erased.
- 5. The in-system erasing method of claim 4 wherein if said memory cell is erased, then a predetermined status code is loaded into said ISP register.
RELATED APPLICATIONS
This application is a continuation-in-part application of U.S. patent application Ser. No. 08/512,796, entitled "Efficient In-System Programming Structure and Method for Non-Volatile Programmable Logic Devices", filed on Aug. 9, 1995, now U.S. Pat. No. 5,734,868.
US Referenced Citations (11)
Foreign Referenced Citations (1)
Number |
Date |
Country |
920225768 |
Aug 1992 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Reference Book "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE Std 1149.1, Oct. 21, 1993, Published by the Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, NY, NY 10017, pp. 3-1 through 5-16 and 7-1 through 7-28. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
512796 |
Aug 1995 |
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