Patent Grant
9466244
The present disclosure relates to an EL display device having electroluminescence (hereinafter referred to as EL) elements using organic materials as luminescent materials, which are arranged in a matrix, and a production method therefor.
Active matrix EL display devices that each include organic EL elements in a matrix are used as display devices such as smart phones, and commercialized. Recently, EL display panels are being developed for enlargement.
This EL display device requires a plurality of transistors to configure pixels, and also requires gate signal lines that control the transistors, as shown in PTLs 1, 2 and 3. Therefore, compared to a liquid crystal panel, a pixel configuration is complicated, and a driving method is also complicated.
An EL display device of the present disclosure includes: an EL display panel that has a display area provided with a plurality of pixels arranged in a matrix, each of the pixels having an EL element; a source driver circuit that supplies a video signal through a source signal line connected to each of the pixels; and a gate driver circuit that supplies a selection voltage or a non-selection voltage through a gate signal line connected to each of the pixels. Each of the pixels has: a driving transistor that supplies a current to the EL element; a first switching transistor that is connected to the driving transistor and controls the current supplied to the EL element; and a second switching transistor that is connected to the source signal line and supplies the video signal to each of the pixels. Furthermore, the gate driver circuit includes: a first gate driver circuit that is formed and disposed along with each of the pixels on the EL display panel; and a second gate driver circuit that is externally connected to the gate signal lines of the EL display panel. The first gate driver circuit is connected to a gate terminal of the first switching transistor of each of the pixels via the gate signal line, and the second gate driver circuit is connected to the gate terminal of the second switching transistor of each of the pixels via the gate signal line.
A production method for an EL display device of the present disclosure is a production method for an EL display device including: an EL display panel that has a display area provided with a plurality of pixels arranged in a matrix, each of the pixels having an EL element; a source driver circuit that supplies a video signal through a source signal line connected to each of the pixels; and a gate driver circuit that supplies a selection voltage or a non-selection voltage through a gate signal line that is connected to each of the pixels. Each of the pixels has; a driving transistor that supplies a current to the EL element; a first switching transistor that is connected to the driving transistor and controls the current supplied to the EL element; and a second switching transistor that is connected to the source signal line and supplies the video signal to each of the pixels. Furthermore, the gate driver circuit has: a first gate driver circuit that is formed and disposed along with each of the pixels on the EL display panel; and a second gate driver circuit that is externally connected to the gate signal lines of the EL display panel. The first gate driver circuit is connected to a gate terminal of a first switching transistor of each of the pixels via the gate signal line, and second gate driver circuit is connected to a gate terminal of the second switching transistor of each of the pixels via the gate signal line. Furthermore, the EL display panel is formed with a test circuit that supplies a test signal to each of the pixels through the source signal line. After performing inspection for supplying the test signal to each of the pixels of the EL display panel, the test circuit is separated from the EL display panel.
With this configuration, it is possible to implement optimum on/off control for each of a plurality of transistors that configure pixels, and therefore it is possible to implement an EL display device that facilitates inspection with a simple configuration. Additionally, it is possible to rapidly perform inspection at the time of panel inspection.
Hereinafter, an EL display device according to an exemplary embodiment is described with reference to the drawings.
As shown in
A configuration of the pixel is now described. Single pixel 10 has a configuration in which a source terminal of switching transistor 11d is connected to a drain terminal of P-channel driving transistor 11a, and an anode terminal of EL element 12 is connected to a drain terminal of transistor 11d. Transistors 11b, 11c, 11e and 11f are other switching transistors provided in pixel 10, and capacitors 13a, 13b, 13c, 13d and 13e are capacitors for controlling ON/OFF of transistors 11a to 11f.
Cathode voltgage Vss is applied to a cathode terminal of EL element 12, anode voltage Vdd is applied to a source terminal of transistor 11a from an anode electrode of the EL display device, and anode voltage Vdd and cathode voltgage Vss are set to have a relation of anode voltage Vdd>cathode voltgage Vss.
The drive circuit has source driver IC 14 that serves as a source driver circuit, gate driver IC 15 that serves as a gate driver circuit, and gate driver circuit 16 that is incorporated in EL display panel 1. Source driver IC 14, gate driver IC 15 and gate driver circuit 16, and pixel 10 are electrically connected to each other via gate signal lines 17 (17a, 17b, 17c, 17d, 17e) and source signal line 18. Additionally, gate driver circuit 16 that has terminal electrode 16a, to which gate signal line 17d is connected, is formed and disposed along with pixel 10 on EL display panel 1, so that gate driver circuit 16 is incorporated in EL display panel 1. That is, gate driver circuit 16 is simultaneously formed by use of a manufacturing process of the transistor of pixel 10 of EL display panel 1. On the other hand, gate driver IC 15 is mounted on flexible board (hereinafter referred to as a COF) 19 that serves as a circuit board having terminal electrodes 19a, to which gate signal lines 17a, 17b and 17c and 17e are connected. Gate driver IC 15 is externally connected to gate signal lines 17a, 17b and 17c and 17e of EL display panel 1 via this COF 19. Gate driver IC 15 may be externally directly connected to a connection terminal of EL display panel 1 without COF 19 to be mounted.
Gate driver IC 15 and gate driver circuit 16 may be formed by any method of high temperature polysilicon, low temperature polysilicon, continuous grain boundary silicon, transparent amorphous oxide semiconductor, amorphous silicon, and the like. Additionally, gate driver IC 15 and gate driver circuit 16 have shift register circuits and buffer circuits for sequentially supply signals to gate signal lines 17, as described later. A scanning direction of the shift register circuit is inverted, so that a display screen of EL display panel 1 is vertically inverted to be displayed.
In
As shown in
That is, a source terminal and a drain terminal of transistor 11b are connected between a gate terminal and the drain terminal of transistor 11a, and an ON-state voltage is applied to gate signal line 17b (Gb), resulting in a short circuit (connection) between the gate terminal and the drain terminal of transistor 11a. One of terminals of capacitor 13b is connected to the gate terminal of transistor 11a, and the other terminal of capacitor 13b is connected to the drain terminal of transistor 11b. A source terminal of transistor 11c is connected to source signal line 18 through transistor 11b. When an ON-state voltage of gate signal line 17c (Gc) is applied to a gate terminal of transistor 11c, transistor 11c is turned on, and voltage Vss is applied to pixel 10 in accordance with the video signal supplied to source signal line 18.
One of terminals of capacitor 13a of pixel 10 is connected to the drain terminal of transistor 11b, and the other terminal is connected to the anode electrode of the EL display device, so that anode voltage Vdd is applied.
Drain terminal of transistor 11e is connected to the drain terminal of transistor 11b, and source terminal of transistor 11e is connected to a signal line, to which a reset voltage Va is applied. An ON-state voltage is applied to gate signal line 17a (Ga), so that transistor 11e is turned on, and reset voltage Va is applied to capacitor 13a.
Herein, for transistors 11c and 11e, P-channel transistors are employed, and an LDD structure is employed. That is, a structure in which gates of a plurality of transistors are connected in series is employed, thereby enabling favorable off-characteristics of transistors 11c and 11e. Similarly, for the transistors other than transistors 11c and 11e, P-channel transistors are preferably employed, and an LDD structure is preferably employed. A multi-gate structure is employed as necessary, so that off-leakage can be suppressed, and favorable contrast and offset cancellation operation can be implemented.
Although capacitor 13a has a configuration in which anode voltage Vdd is applied, the present disclosure is not limited to this, and other arbitrary DC voltage may be connected. Similarly, transistor 11a may have a configuration in which an arbitrary DC voltage other than anode voltage Vdd is applied. That is, the same voltage is not applied to capacitor 13a and the source terminal of transistor 11a, and different voltages are applied to capacitor 13a and the source terminal of transistor 11a. For example, such a connection configuration in which anode voltage Vdd is applied to the source terminal of transistor 11a, and DC voltage Vb (5 (V)) is applied to capacitor 13a may be applied.
In a case of a digital driving system in which pixel 10 is turned on and off, or is digitally lit, like a PWM driving system, a predetermined voltage value is applied to pixel 10 through transistor 11b, transistor 11d is turned on/off in accordance with the number of bits corresponding to gradation of a video signal, and light emitting driving control is performed by gradation display. Additionally, on/off control of transistor 11d is performed, so that zonal black display (non-display) is caused in the display area, thereby controlling an amount of a current that flows in the display area.
Actions of capacitors 13c and 13d, shown by dotted lines in
In
Thus, a gate terminal voltage of driving transistor 11a (potential of capacitor 13e) is changed via a capacity of capacitor 13c, thereby enabling favorable black display.
When transistor 11d is in an ON-state, VGL2 voltage is applied to gate signal line 17d. When transistor 11d is in an OFF-state, VGH2 voltage is applied to gate signal line 17d. Transistor 11d is in an OFF-stage during offset cancellation operation. When EL element 12 is caused to emit light, transistor 11d is in an ON-state. Therefore, at the time of display start, gate signal line 17d is changed from VGH2 voltage to VGL2 voltage. Accordingly, the gate terminal voltage of transistor 11a is reduced by the action of through capacitor 13d. When the gate terminal voltage of transistor 11a is reduced, transistor 11a can causes a large current to flow through EL element 12, thereby enabling high luminance display.
Thus, the gate terminal voltage of driving transistor 11a is changed via a capacity of capacitor 13d, so that amplitude of the current that flows through EL element 12 is increased, thereby enabling high luminance display.
The capacity of capacitor 13c is preferably between 1/12 and ⅓ (inclusive) of a capacity of capacitor 13a or capacitor 13b. When a capacity ratio of capacitor 13c is too small, a change rate of the gate terminal voltage of transistor 11a becomes too large, and a difference from an ideal value of an offset cancellation state becomes too large. Additionally, when the capacity ratio is too large, the change of gate terminal voltage of transistor 11a becomes small, thereby making it difficult to obtain an effect.
Capacitor 13c that causes a through voltage is preferably changed on the basis of R, G and B pixel sizes modulated by pixels, magnitude of a current to be supplied, or a WL ratio of a driving transistor. This is because driving currents of respective EL elements 12 of R, G and B pixels are different, and current values or voltage values of a black level are different. For example, in a case where capacitor 13c of the R pixel is set to 0.02 pF, capacitors 13c of other colors (G and B pixels) are set to 0.025 pF. In a case where capacitor 13c of the R pixel is set to 0.02 pF, capacitor 13c of the G pixel is set to 0.03 pF, and capacitor 13c of the B pixel is set to 0.025 pF.
Thus, the capacity of capacitor 13c is changed for each of the R, G and B pixels, so that an offset cancellation voltage, a driving current of the black level, or a voltage of the black display can be adjusted for each of the R, G and B pixels.
Furthermore, the through voltage is determined by a difference of a relative capacity between holding capacitors 13a and 13b and through voltage generating capacitor 13c, and therefore the present disclosure is not limited to change of the capacities of capacitors 13c for the R, G and B pixels, and the capacity of holding capacitor 13a may be made variable. For example, in a case where capacitor 13a of the R pixel is set to 1.0 pF, capacitor 13a of the G pixel may be set to 1.2 pF, and capacitor 13a of the B pixel may be set to 0.9 pF.
A capacity of capacitor 13c for a through voltage may be changed in the right and left of the display area. Pixel 10 that is located near gate driver IC 15 or gate driver circuit 16 is disposed on a signal supply side. Therefore, rising of a gate signal is fast, or a slew rate is high, and therefore the through voltage becomes large. Rising of a gate signal of a pixel that is formed at a central part of the display area, or at a position far from gate driver IC 15 and gate driver circuit 16 is slow, and therefore the through voltage becomes small. Therefore, the capacity of capacitor 13c for a through voltage of pixel 10 located near a side of connection with gate driver IC 15 is simply made small, and the capacity of capacitor 13c of pixel 10 located at the position far from gate driver IC 15 is simply made large.
Offset cancellation current If flows through transistor 11a, from potential Vdd of the source terminal toward DC voltage Vb applied to a drain terminal of transistor 11f via channels of transistor 11a, 11c, 11f. The magnitude of the voltages is set to have a relation of anode voltage Vdd>DC voltage Vb, and reset voltage Va>DC voltage Vb.
Offset cancellation current If flows, thereby reducing a drain terminal potential of transistor 11a. Additionally, reset current Ir flows by reset voltage Va, and Va voltage is applied to a terminal of capacitor 13b.
Transistor 11a is turned on, and offset cancellation current If flows for a very short period. At least a drain terminal voltage of transistor 11a drops to a lower level than anode voltage Vdd by offset cancellation current If, thereby allowing an operable state.
Transistor 11d is turned off, and transistor 11c is turned on, so that offset cancellation current If flows toward the gate terminal of transistor 11a. Relatively large offset cancellation current If initially flows. As a potential of the gate terminal of transistor 11a rises, and is close to an OFF-state, the current that flows is reduced. Finally, the current becomes 0 μA, or a current value near 0 μA.
By the aforementioned operation, transistor 11a enters an offset cancellation state. The offset cancellation voltage is held by capacitor 13b. Capacitor 13b has one terminal held by reset voltage Va. The offset cancellation voltage is held by the other terminal (terminal connected to the gate terminal of transistor 11a).
On the other hand, video signal voltage Vs is applied to source signal line 18. Transistor 11b is turned on, so that video signal voltage Vs is applied to capacitor 13b. The voltage of terminal of capacitor 13b is changed from reset voltage Va to video signal voltage Vs. Therefore, a voltage based on video signal voltage Vs+offset cancellation voltage is held by capacitor 13b.
Video signal voltage Vs is a voltage based on anode voltage Vdd. Anode voltage Vdd is different in the panel by wiring voltage drop in the panel. Therefore, video signal voltage Vs is also variable or changed on the basis of anode voltage Vdd applied to the pixel.
In
Source driver IC 14 that serves as a source driver circuit may be incorporated with not only a mere driver function, but also a power supply circuit, a buffer circuit (including a circuit such as a shift resister), a data conversion circuit, a latch circuit, command data, a shift circuit, an address conversion circuit, an image memory, and the like.
Gate driver circuit 16 may configure a shift register and an output buffer circuit by use of the P-channel transistors, and the capacitors. Only the P-channel transistors are configured, so that the number of masks to be used in a process is reduced, and the panel can be implemented at a low cost.
Transistors 11a to 11f may be formed by any of formation methods by high temperature polysilicon, low temperature polysilicon, continuous grain boundary silicon, transparent amorphous oxide semiconductor, amorphous silicon, infrared RTA, and the like. These transistors have top gate structures, so that parasitic capacities are reduced, and gate electrode patterns of top gates become light shielding layers, and light emitted from EL element 12 is shielded by the light shielding layers. Consequently, it is possible to reduce incorrect operation of the transistors, and an off-leakage current.
As a wiring material of gate signal line 17 or source signal line 18, or wiring materials of both of gate signal line 17 and source signal line 18, a material that allows implementation of a process capable of employing copper wiring or copper alloy wiring is preferable, because wiring resistance can be reduced, and a large EL display panel can be implemented.
Thus, in the present disclosure, gate driver circuit 16 that is incorporated in EL display panel 1, and gate driver IC 15 that is not incorporated in EL display panel 1 are used, gate driver circuit 16 is used in order to control a current supplied to EL element 12, and gate driver IC 15 is used in order to control transistor 11b which applies a video signal to pixel 10. Detailed description is made later.
A configuration of the EL display panel is now described.
A temperature sensor (not shown) is disposed in a space between sealing plate 30 and array substrate 31, on a surface of sealing plate 30, or the like and duty ratio control, lighting rate control of the EL display panel, or the like is performed by an output result of this temperature sensor. Furthermore, during panel inspection, an operating speed of the gate driver circuit is adjusted on the basis of detection output of the temperature sensor.
A thin film transistor array substrate side is described at first. In
The method of performing color display in the EL display panel includes a method of forming a blue light emitting EL layer, and converting the emitted blue light into R, G and B light with R, G and B color conversion layers, in addition to a method using color filters 33 as described above.
As shown in
A light emission part side is described below. In
As cathode electrode 42, silver (Ag), aluminum (Al), magnesium (Mg), calcium (Ca), or these alloys, a transparent electrode such as ITO, IGZO and IZO can be used.
Herein, an example shown in
In a panel of an example shown in
A configuration of the EL display device and an inspection method in production are described below.
As shown in
Like gate signal lines 17b of transistors 11b, video signals are applied to pixels 10, and gate signal lines that control transistors necessary for high-speed writing are connected to external gate driver IC 15. In a case where a plurality of the transistors are connected to a single gate signal line like each gate signal line 17a, the gate signal line is connected to external gate driver IC 15.
On the other hand, like gate signal lines 17d of transistors 11d, the gate signal lines that control light emitting currents supplied to EL elements 12 from driving transistors 11a are connected to gate driver circuit 16 that is incorporated in the panel.
In
Herein, gate signal lines 17 (gate signal lines 17a, 17b, 17c, 17e) that are driven (controlled) by gate driver IC 15, and need high-speed response are formed of three layers of copper (Cu), or titanium (Ti)-copper (Cu)-titanium (Ti), or copper (Cu) alloy such that resistance values are reduced. On the other hand, gate signal lines 17 (gate signal lines 17d) driven by gate driver circuit 16 do not need relatively high-speed response, and therefore are configured by aluminum (Al), molybdenum (Mo), tungsten (W), or alloy of these metals that allow relatively high impedance.
That is, gate signal lines 17 controlled by external gate driver IC 15 are each configured by such a metal material that wiring resistance is lower than that of gate signal line 17 controlled by incorporated gate driver circuit 16. The method of reducing wiring resistance may be not a method of changing a metal material itself, but a method of changing a film thickness or a width of wiring.
As shown in
Herein, gate driving ability of an output stage of shift register circuit 16b is small, and therefore gate driver circuit 16 is incapable of directly driving gate signal lines 17d with gate circuits that configure shift register circuits 16b. Accordingly, it is necessary to connect inverter circuits 16c and 16d in stages. When the number of connection stages of inverter circuits 16c and 16d are large, characteristic differences of connected inverter circuits 16c and 16d are accumulated, thereby causing a difference in transmission time from shift register circuit 16b to terminal electrode 16a. For example, in an extreme case, an ON/OFF signal is output to terminal electrode 16a in 1.0 μsec after an output pulse is output from shift register circuit 16b.
Specifically, in
As shown in
0.25≦(Wn−1/Ln−1)/(Wn/Ln)≦0.75
Additionally, a W/L ratio of a P-channel of each of inverter circuits 16c and 16d (Wp/Lp) and a W/L ratio of an n-channel (Ws/Ls) needs to satisfy the following relation.
0.4≦(Ws/Ls)/(Wp/Lp)≦0.8
As shown in
Test transistors T are transistors (switch circuits) for application of red (R), green (G), and blue (B) voltage, and switching transistors for sequentially applying voltages to respective pixels 10R, 10G and 10B of RGB. Gate terminals of transistors T are connected to electrode terminals Y1 to Y4, and probes 22a to 22d are connected to electrode terminals Y1 to Y4, and ON/OFF voltages of transistors T are applied. On/off control of transistors T is performed on the basis of the voltages applied to electrode terminals Y1 to Y4. The ON/OFF voltages applied to electrode terminals Y1 to Y4 each are a voltage equivalent to the video signal voltage. For example, ON-state voltage is applied with OFF-state voltage VGH, and ON-state voltage VGL, so that transistors T are turned on, and a test voltage is applied to each pixel 10. That is, magnitude of a test voltage is varied, so that display luminance of pixel 10 can be changed.
A the time of a test of EL display panel 1, an ON-state voltage is applied to probe 22a, transistors T are turned on, and a test voltage is applied to each source signal line 18. At the time of the test, gate driver circuit 16 is operated, and a gate signal line position to be selected is moved, thereby performing inspection. Additionally, gate driver IC 15 is operated as necessary, thereby performing inspection.
Thus, at the time of the test, test circuit 20 and gate driver circuit 16 are controlled at the same time, and panel inspection is performed, thereby obtaining effects of facilitating panel inspection, and rapidly performing accurate inspection.
In order to perform black display of pixel 10, when driving transistor 11a of the pixel is a P-channel driving transistor, the test voltage is generally set to a voltage value near anode voltage Vdd. In order to perform white display, the test voltage is generally set to a ground voltage or a voltage value near cathode voltgage Vss.
As shown in
In
As shown in
After the inspection of EL display panel 1 is thus performed, the substrate of EL display panel 1 is cut with A-A line and B-B line of
After the inspection, voltages that allow the transistors in test circuit 20 to be turned off are always applied to test circuit 20, so that the substrate of EL display panel 1 may not be cut with B-B line. Also on the side of gate signal lines 17a, 17b and 17c, the T1 terminal, the T2 terminal and the T3 terminal are not provided, and probes for inspection are electrically brought into direct contact with gate signal lines 17a, 17b and 17c to allow supply of the predetermined test signals, so that the cutting of the substrate after the inspection is not needed.
As shown in
A probe for inspection is brought into the T1 terminal, the ON/OFF voltages (VGL, VGH) are applied to gate signal lines 17b, so that on/off control of transistors 11b is performed. The ON/OFF voltages (VGL, VGH) are applied to gate signal lines 17a from the T2 terminal, so that on/off control of transistors 11e and 11f is performed. The ON/OFF voltages (VGL, VGH) are applied to gate signal lines 17c from the T3 terminal, so that on/off control of transistors 11c is performed.
ON/OFF signal voltages of the transistors of test circuit 20 are applied to a Y2 terminal. The transistors of test circuit 20 is P-channel transistors, and the VGL voltage is applied to the Y2 terminal, thereby turning on the transistors. Video signal voltage Vs is applied to a Y1 terminal, an appropriate voltage according to a video signal is applied to each of red (R), green (G), and blue (B) pixels. This voltage applied to each pixel is intermittently applied, so that RGB pixels of EL display panel 1 can be intermittently lit.
The inspection method is described with the example in which EL elements 12 are brought into lighting states or non-lighting states, and inspection is performed. However, a current that flows through a short circuit part is detected, thereby enabling inspection of short circuit defects of transistors 11 or the like. The detection of the current that flows through the short circuit part may employ a method of bringing a probe for pickup into contact with source signal lines 18 or the like, and detecting the current.
Video signal voltage Vs is made variable, so that light emission luminance of the pixels can be changed. Driving transistors 11a of pixels 10 are P-channel transistors, and therefore video signal voltage Vs is made to be a voltage near anode voltage Vdd so that light emission luminance of pixels 10 becomes low. On the other hand, video signal voltage Vs is made to be a voltage near ground or cathode voltgage Vss, so that light emission luminance of pixels 10 becomes high. As a matter of course, video signal voltage Vs is adjusted or is made variable, so that light emission luminance of EL elements 12 of pixels 10 can be adjusted.
As shown in
The VGL voltage is applied to the T2 terminal during a t4 period, so that transistors 11e and 11f connected to gate signal lines 17a (Ga) are turned on. Additionally, ON-state voltages VGL are applied to gate signal lines 17d (Gd), so that transistors 11d are turned on. Transistors 11d and transistors 11f are turned on, so that current paths of anode voltages Vdd→transistors 11a→transistors 11d→transistors 11f→Vb terminals are generated, the drain terminals of driving transistors 11a are lowered.
The VGL voltage is applied to the T3 terminal during t3, so that transistors 11c connected to gate signal lines 17c (Gc) are turned on, and offset cancellation of transistors 11a is performed. Then, the VGH voltages are applied to the T2 terminal and the T3 terminal, and transistors 11e, 11f and 11c are turned on. The VGL voltage is applied to the T1 terminal during a t5 period, so that transistors 11b connected to gate signal lines 17b are turned on. Transistors 11b are turned on, so that video signals are applied to pixels 10.
The t3, t4 and t5 periods are made variable or adjusted, so that offset cancellation operation of pixels 10 can be performed. Additionally, application time of reset voltage Va is made variable, so that operation states of transistors 11 can be changed or adjusted, and an operation test of pixels 10 can be performed.
Control of emission (ON) and non-emission (OFF) of EL elements 12 of pixels 10 is performed with a signal supplied to an enable terminal (EN terminal) of gate driver circuit 16 incorporated in the panel. When the EN terminal is set to an H level in a logic level, the VGL voltage is output to gate signal line 17d (Gd), and transistor 11d is turned on. Transistor 11d is turned on, so that a current path, which allows a light emitting current from driving transistor 11a to be supplied to EL element 12, is generated, and corresponding EL element 12 emits light. When the EN terminal is set to an L level in the logic level, the VGH voltage is output to gate signal line 17d (Gd), and transistor 11d is turned off. Transistor 11d is turned off, so that the current path, which allows the light emitting current from driving transistor 11a to be supplied to EL element 12, is not present, and corresponding EL element 12 does not emit light.
In synchronization with the control of EL element 12, a video signal is applied to the Y2 terminal. The ON-state voltage (VGL) is applied to the Y1 terminal, the transistors of test circuit 20 is turned on, and a video signal voltage for a test is applied to source signal line 18.
The video signal voltage for a test is applied for the t2 period or the t1 period in
The voltage waveform shown in
As shown in
As described above, the present disclosure relates to an EL display device including: EL display panel 1 that has a display area provided with a plurality of pixels 10 arranged in a matrix, each of pixels 10 having EL element 12; source driver IC 14 that serves as a source driver circuit which supplies a video signal through source signal line 18 connected to each pixel 10; and a gate driver circuit that supplies a selection voltage or a non-selection voltage through gate signal line 17 that is connected to each pixel 10. Each pixel 10 has: driving transistor 11a that supplies a current to EL element 12; first switching transistor 11d that is connected to driving transistor 11a and controls the current supplied to EL element 12; and second switching transistors 11b, 11c and 11e that are connected to source signal line 18 and supply video signals to pixel 10. The gate driver circuit includes: gate driver circuit 16 that serves as a first gate driver circuit which is formed and disposed along with pixels 10 on EL display panel 1; and gate driver IC 15 that serves as a second gate driver circuit which is externally connected to gate signal lines 17a, 17b and 17c of EL display panel 1. Gate driver circuit 16 is connected to a gate terminal of first switching transistor 11d of each pixel 10 via gate signal line 17d, and gate driver IC 15 is connected to gate terminals of second switching transistors 11b, 11c and 11e of each pixel 10 via gate signal lines 17a, 17b and 17c.
With such a configuration, first switching transistors 11d having small loads are driven with gate driver circuit 16 that is incorporated in EL display panel 1, and second switching transistors 11b, 11c and 11e having large loads are driven with the gate driver circuit IC that is externally connected to EL display panel 1. It is possible to implement optimum on/off control of each of a plurality of the transistors that configures each pixel 10, and to implement an EL display device that has allows simple inspection with a simple configuration. Additionally, at the time of panel inspection, incorporated gate driver circuit 16 is operated, and a probe is simply brought into press contact with only a terminal that needs inspection, so that the panel can be inspected. Consequently, it is possible to perform rapid inspection.
The EL display device can be utilized as a display of a video camera, a digital camera, a goggle type display, a navigation system, a car audio, an audio component, a computer, a game machine, a personal digital assistant (a mobile computer, a mobile phone, a handheld game console, an electronic book, or the like), picture reproducer including a recording medium, or the like.
As described above, the present invention is useful for implementation of a high reliable EL display device.
| Number | Date | Country | Kind |
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| PCT/JP2012/007728 | 12/3/2012 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2013/118219 | 8/15/2013 | WO | A |
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