Patent Application
20100277401
The present invention relates to a self-luminous display panel such as an EL display panel which employs organic or inorganic electroluminescent (EL) elements. Also, it relates to an information display apparatus and the like which employ the EL display panel, a drive method for the EL display panel, and the drive circuit for the EL display panel.
Generally, active-matrix display apparatus display images by arranging a large number of pixels in a matrix and controlling the light intensity of each pixel according to a video signal. For example, if liquid crystals are used as an electrochemical substance, the transmittance of each pixel changes according to a voltage written into the pixel. Even with active-matrix display apparatus which employ an organic electroluminescent (EL) material as an electrochemical substance, the basic operation is the same as in the case of using liquid crystals.
In a liquid crystal display panel, each pixel works as a shutter, and images are displayed as a backlight is blocked off and revealed by the pixels or shutters. An organic EL display panel is of a self-luminous type in which each pixel has a light-emitting element. Consequently, the self-luminous type display panel such as an organic EL display panel has the advantages of being more viewable than liquid crystal display panels, requiring no backlighting, having high response speed, etc.
Brightness of each light-emitting element (pixel) in an organic EL display panel is controlled by an amount of current. That is, organic EL display panels differ greatly from liquid crystal display panels in that light-emitting elements are driven or controlled by current.
A construction of organic EL display panels can be either a simple-matrix type or active-matrix type. It is difficult to implement a large high-resolution display panel of the former type although the former type is simple in structure and inexpensive. The latter type allows a large high-resolution display panel to be implemented, but involves a problem that it is a technically difficult control method and is relatively expensive. Currently, active-matrix type display panels are developed intensively. In the active-matrix type display panel, current flowing through the light-emitting elements provided in each pixel is controlled by thin-film transistors (transistors) installed in the pixels.
Such an organic EL display panel of an active-matrix type is disclosed in Japanese Patent Laid-Open No. 8-234683. An equivalent circuit for one pixel of the display panel is shown in
The organic EL element 15, in many cases, may be referred to as an OLED (organic light-emitting diode) because of its rectification. In
Incidentally, the light-emitting element 15 according to the present invention is not limited to an OLED. It may be of any type as long as its brightness is controlled by the amount of current flowing through the element 15. Examples include an inorganic EL element, a white light-emitting diode consisting of a semiconductor, a typical light-emitting diode, and a light-emitting transistor. Rectification is not necessarily required of the light-emitting element 15. Bidirectional diodes are also available. While the reference numeral 15 is described as an EL element, it is sometimes used as the meaning of an EL film or an EL structure.
In the example of
Incidentally, although it is stated herein that the transistor elements 11a which supply current used to drive the EL elements 15 are p-channel transistors, this is not restrictive and they may be n-channel transistors.
Of course, the transistors 11 may be bipolar transistors, FETs, or MOSFETs. The board 71 is not limited to a glass substrate and may be a silicon substrate or metal substrate.
To drive the pixel 16, a video signal which represents brightness information is first applied to the source signal line 18 with the gate signal line 17a selected. Then, the transistor 11a conducts, the storage capacitance 19 is charged or discharged, and gate potential of the transistor 11b matches the potential of the video signal. When the gate signal line 17a is deselected, the transistor 11a is turned off and the transistor 11b is cut off electrically from the source signal line 18. The gate potential of the transistor 11a is maintained stably by the storage capacitance 19. Current delivered to the light-emitting element 15 via the transistor 11a depends on gate-source voltage Vgs of the transistor 11a and the light-emitting element 15 continues to emit light at an intensity which corresponds to the amount of current supplied via the transistor 11a.
Organic EL display panels are made of low-temperature polysilicon transistor arrays. However, since organic EL elements use current to emit light, there has been a problem that variations in the characteristics of the transistors will cause display irregularities.
In view of the above problems with conventional EL elements, an object of the present invention is to provide a drive method of an EL display apparatus which can achieve more uniform display than conventional methods even if there are variations in characteristics of pixel transistors and which causes blurred moving pictures less than the conventional methods.
To achieve the above object, a first invention of the present invention is a drive method for an EL display panel, the EL display panel comprising:
EL elements arranged in a matrix;
driver transistors which supply current to be passed through the EL elements;
first switching elements placed in current paths of the EL elements;
a gate driver circuit which turns on and off the first switching elements for control; and
a source driver circuit which supplies programming current to the driver transistors,
wherein the driver transistors are p-channel transistors,
unit transistors which generate the programming current in the source driver circuit are n-channel transistors, and
the gate driver circuit turns off the first switching elements at least two or more times during one frame period or one field period.
A second invention of the present invention is a drive method for an EL display panel, the EL display panel comprising:
EL elements arranged in a matrix;
driver transistors which supply current to be passed through the EL elements;
first switching elements placed in current paths of the EL elements;
a gate driver circuit which turns on and off the first switching elements for control; and
a source driver circuit which supplies programming current to the driver transistors,
wherein the driver transistors are p-channel transistors,
unit transistors which generate the programming current in the source driver circuit are n-channel transistors, and
the gate driver circuit keeps the first switching elements off for two horizontal scanning periods during one frame period or one field period.
A third invention of the present invention is a drive method for an EL display panel, the EL display panel comprising:
EL elements arranged in a matrix;
driver transistors which supply current to be passed through the EL elements;
first switching elements placed in current paths of the EL elements;
a gate driver circuit which turns on and off the first switching elements for control; and
a source driver circuit which supplies programming current to the driver transistors,
wherein the driver transistors are p-channel transistors,
unit transistors which generate the programming current in the source driver circuit are n-channel transistors,
a period during which pixel row is selected and programmed with current is constructed from a first period and a second period,
a first current is applied during the first period,
a second current is applied during the second period,
the first current is larger than the second current, and
the source driver circuit outputs the first current during the first period and outputs the second current during the second period which comes after the first period.
A fourth invention of the present invention is the drive method for the EL display panel according to the first invention of the present invention, wherein the first switching elements are turned off periodically during one frame period or one field period.
A fifth invention of the present invention is an EL display panel, comprising:
a source driver circuit which outputs programming current;
EL elements arranged in a matrix;
driver transistors which supply current to be passed through the EL elements;
first switching elements placed in current paths of the EL elements;
second switching elements which constitute paths used to transmit programming current to the driver transistors;
a first gate driver circuit which turns on and off the first switching elements for control;
a second gate driver circuit which turns on and off the second switching elements for control;
a source driver circuit which supplies programming current to the driver transistors,
wherein the driver transistors are p-channel transistors,
unit transistors which generate the programming current in the source driver circuit are n-channel transistors,
the first gate driver circuit turns off the first switching elements a number of times during one frame period or one field period,
the first gate driver circuit is placed or formed on one side of the display panel, and
the second gate driver circuit is placed or formed on another side of the display panel.
A sixth invention of the present invention is the EL display panel according to the fifth invention of the present invention, wherein the gate driver circuits are formed in the same process as the driver transistors and the source driver circuit is made of a semiconductor chip.
A seventh invention of the present invention is an EL display panel, comprising:
gate signal lines;
source signal lines;
a source driver circuit which outputs programming current;
a gate driver circuit;
EL elements arranged in a matrix;
driver transistors which supply current to be passed through the EL elements;
first transistors placed in current paths of the EL elements;
second transistors which constitute paths used to transmit programming current to the driver transistors; and
a source driver circuit which supplies programming current to the driver transistors,
wherein the driver transistors are p-channel transistors,
unit transistors which generate the programming current in the source driver circuit are n-channel transistors,
the source driver circuit outputs programming current to the source signal lines,
the gate driver circuit is connected to the gate signal lines,
gate terminals of the second transistors are connected to the gate signal lines,
source terminals of the second transistors are connected to the source signal lines,
drain terminals of the second transistors are connected to drain terminals of the driver transistors, and
the gate driver circuit selects a plurality of gate signal lines and supplies the programming current to the driver transistors of a plurality of pixels.
An eighth invention of the present invention is an EL display panel, comprising:
a display area consisting of I pixel rows (I is an integer larger than 1) and J pixel columns (J is an integer larger than 1);
a source driver circuit which applies an image signal to source signal lines in the display area;
a gate driver circuit which applies a turn-on voltage or turn-off voltage to gate signal lines in the display area; and
a dummy pixel row formed outside the display area,
wherein EL elements are arranged in a matrix in the display area and emit light based on the image signal from the source driver circuit, and
the dummy pixel row either does not to emit light or emits light not visible to the eye.
A ninth invention of the present invention is the EL display panel according to the seventh invention of the present invention,
wherein the gate driver circuit selects a plurality of pixel rows at a time and applies the image signal from the source driver circuit to the plurality of pixel rows; and
a dummy pixel row is selected when the first pixel row or I-th pixel rows is selected.
A tenth invention of the present invention is the EL display panel according to the seventh invention of the present invention, wherein the gate driver circuit is constructed of p-channel transistors.
An eleventh invention of the present invention is an EL display panel, comprising:
EL elements arranged in a matrix;
driver transistors which supply current to be passed through the EL elements;
first switching elements placed in current paths of the EL elements;
a gate driver circuit which turns on and off the first switching elements for control; and
a source driver circuit which supplies programming current to the driver transistors,
wherein the driver transistors and the first switching elements are p-channel transistors, and
unit transistors which generate the programming current in the source driver circuit are n-channel transistors.
A twelfth invention of the present invention is a drive method for an EL display panel, comprising the steps of: supplying EL elements with a current which makes the EL elements emit light brighter than a predetermined brightness; and making the EL elements emit light for a period equal to 1/N of one frame period or one field period (N is larger than 1).
A thirteenth invention of the present invention is the drive method for the EL display panel according to the twelfth invention of the present invention, wherein the period equal to 1/N of a frame is divided into a plurality of periods.
A fourteenth invention of the present invention is a drive method for an EL display panel which uses a current to program currents to be passed through EL elements, comprising the steps of: making the EL elements emit light brighter than a predetermined brightness; displaying a display area equal to 1/N (N>1) of an entire screen; and shifting the display area of 1/N of the entire screen in sequence to display the entire screen.
A fifteenth invention of the present invention is an EL display apparatus comprising an EL display panel having the EL display panel in turn comprising EL elements arranged in a matrix; driver transistors which supply current to be passed through the EL elements; first switching elements placed in current paths of the EL elements; and a gate driver circuit which turns on and off the first switching elements, and a receiver.
One of the aspects of the present invention described herein includes two operations.
The first operation involves supplying driver transistors 11a of pixels 16 with current (drawn) from a current driver circuit (IC) 14 and programming the driver transistors 11a with a predetermined current.
The second operation involves passing the current programmed in the driver transistors 11a through EL elements 15.
In this way, by programming the driver transistors 11a with a current and passing the current through the EL elements 15, it is possible to pass the predetermined current which has been programmed, even if there are variations in characteristics of the driver transistors 11a. This makes it possible to achieve a uniform screen display. The current passed through each EL element 15 is driven intermittently by a transistor 11d formed or placed between the EL element 15 and driver transistor 11a.
Another aspect of the present invention is a method of performing current programming by selecting the driver transistors 11a of multiple pixel rows at a time. The selected pixel rows are scanned in sequence. For example, if a current of 1 μA is outputted from the current driver 14 and two pixel rows are selected at a time, a current of 0.5 μA (=½) is programmed into each pixel row.
To do this, a dummy pixel row is formed at least along the top or bottom edge of the screen. The dummy pixel row is designed not to emit light even when programmed with current.
The number of dummy pixel rows formed or disposed equals to the number of pixel rows selected simultaneously minus one.
Parasitic capacitance is present in source signal lines 18 to which current is outputted from the current driver 14.
If the parasitic capacitance cannot be charged and discharged sufficiently, it is pot possible to write a predetermined current into the pixels 16. To improve charging and discharging, output current from the current driver 14 should be increased. However, the current outputted from the current driver 14 is written into the driver transistors 11a of the pixels 16. Thus, an increase in the output current from the current driver 14 increases the current written into the driver transistors 11a as well, resulting in a proportional increase in emission brightness of the pixels 15. Consequently, predetermined brightness is not available.
If the driver transistors 11a of multiple pixel rows are selected simultaneously, the output current from the current driver 14 is programmed into the multiple pixel rows, being divided among them. This makes it possible to increase the current outputted from the current driver 14 and decrease the current written into the driver transistors 11a.
Another aspect of the present invention illuminates pixels 16 intermittently. That is, intermittent screen display is provided. Intermittent screen display eliminates blurred moving pictures. This achieves proper movie display without residual images as in the case of a CRT. Intermittent display can be achieved by controlling the transistors 11d placed or formed between the driver transistors 11a and EL elements 15.
Incidentally, with the above configuration, if the pixel transistors are programmed, for example, with 10 times larger current (N=10), a 10 times larger current flows through the EL elements 15 and the EL elements 15 emit 10 times brighter light. To obtain predetermined emission brightness, the time during which the current flows through the EL elements can be reduced to 1/10 of one frame (1 F). This way, the parasitic capacitance of the source signal lines can be charged and discharged sufficiently and the predetermined emission brightness can be obtained. Since the pixels are programmed with N times larger current, the parasitic capacitance of the source signal lines can be charged and discharged sufficiently.
This allows accurate current programming, resulting in a uniform screen display. Also, current is passed through the EL element 15 only for a period of 1 F/N, but current is not passed during the remaining period (1 F (N−1)/N). In this display condition, image data display and black display (non-illumination) are repeated every 1 F. This makes it possible to achieve proper movie display without edge blur of images.
Some parts of drawings herein are omitted and/or enlarged/reduced herein for ease of understanding and/or illustration. For example, in a sectional view of a display panel shown in
Incidentally, what is described with reference to drawings or the like can be combined with other examples or the like even if not noted specifically. For example, a touch panel or the like can be attached to a display panel in
Also, thin-film transistors are cited herein as driver transistors 11 and switching transistors 11 etc., this is not restrictive. Thin-film diodes (TFDs) or ring diodes may be used instead. Also, the present invention is not limited to thin-film elements, and transistors formed on silicon wafers may also be used. Needless to say, FETs, MOS-FETs, MOS transistors, or bipolar transistors may also be used. They are basically, thin-film transistors. It goes without saying that the present invention may also use varistors, thyristors, ring diodes, photodiodes, phototransistors, or PLZT elements. That is, the switching element 11 and driving element 11 can be constructed by using any of the above elements.
An EL panel according to the present invention will be described below with reference to drawings.
As shown in
A large current flows through the wiring which supplies current to the anode or cathode (anode wiring 86 or cathode wiring 87). For example, current on the order of 100 A flows through an EL display apparatus with a 40-inch screen.
Thus, the resistance values of the anode wiring and cathode wiring fabricated (formed) should be sufficiently low.
To solve this problem, according to the present invention, the anode wiring and the like (wiring which supplies light-emitting current to the EL elements) are formed of thin film. Then, the thickness of the thin-film wiring is increased by electro-plating it in multiple layers using electroless plating or electrolytic plating technologies.
Available plating metals include, for example, chromium, nickel, gold, copper, and aluminum as well as alloys and amalgam thereof. Also, copper foil is affixed as wiring itself or to wiring, as required. Alternatively, copper paste or the like is screen-printed on wiring in multiple layers to increase the thickness of the wiring and thereby decrease the wiring resistance. Also, a bonding technique may be used to bond wires composing the wiring. Also, if necessary, an insulating layer may be formed on the wiring and conductive layers may be stacked on the wiring to form a ground pattern, thereby forming a capacitor (capacitance) between the wiring and ground pattern.
Preferably, the metal electrode 106 is made of metal with a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy thereof. In particular, it is preferable to use, for example, an Al—Li alloy. The transparent electrodes 105 may be made of conductive materials with a large work function such as ITO, or gold and the like. If gold is used as an electrode material, the electrodes become translucent. Incidentally, IZO or other material may be used instead of ITO. This also applies to other pixel electrodes 105.
Needless to say, the EL film 15 according to the present invention may be formed not only by vapor deposition, but also by ink jetting. That is, the EL elements 15 according to the present invention may be formed not only of low molecular-weight material by a vapor deposition process, but also of high molecular-weight material by ink jetting and the like. Besides, they may be formed of screen printing or offset printing.
A desiccant 107 is placed in a space between the sealing lid 85 and array board 71. This is because the organic EL film 15 is vulnerable to moisture. With the EL film 15 shut off from the open air by the sealing lid 85, the desiccant 107 absorbs water penetrating a sealant and thereby prevents deterioration of the organic EL film 15.
Although the glass sealing lid 85 is used for sealing in
Desirably, film thickness of the thin film 111 is such that n·d is equal to or less than main emission wavelength λ of the EL element 15 (where n is the refraction factor of the thin film and d is the film thickness of the thin film; if two or more thin films are laminated, n·d of each thin film is calculated; and the results are summed). By satisfying this condition, it is possible to more than double the efficiency of light extraction from the EL element 15 compared to when a glass substrate is used for sealing. Also, an alloy, mixture, or laminate of aluminum and silver may be used.
A technique which uses an encapsulation film 111 for sealing instead of a sealing lid 85 as described above is called thin film encapsulation. In the case of “underside extraction (see
In the case of “topside extraction (see
Half the light produced by the organic EL layer 15 is reflected by the reflective film 106 and emitted through the array board 71. However, the reflective film 106 reflects extraneous light, resulting in glare, which lowers display contrast. To deal with this situation, a λ/4 phase plate 108 and polarizing plate (polarizing film) 109 are placed on the array board 71. These are generally called circular polarizing plates (circular polarizing sheets).
Incidentally, if the pixels are reflective electrodes, the light produced by the organic EL layer 15 is emitted upward. Thus, needless to say, the phase plate 108 and polarizing plate 109 are placed on the side from which light is emitted. Reflective pixels can be obtained by making pixel electrodes 105 from aluminum, chromium, silver, or the like. Also, by providing projections (or projections and depressions) on a surface of the pixel electrodes 105, it is possible to increase an interface with the organic EL layer 15, and thereby increase the light-emitting area, resulting in improved light-emission efficiency. Incidentally, the reflective film which serves as the cathode 106 (anode 105) is made as a transparent electrode. If reflectance can be reduced to 30% or less, no circular polarizing plate is required. This is because glare is reduced greatly. Light interference is reduced as well.
Glare can be reduced by the application of carbon-containing acrylic resin (black matrix (BM)), leaving pixel apertures uncoated. Any resin may be used as long as it absorbs light. Light diffusing materials are also available, including black metal such as hexavalent chromium; paint; thin film, thick film, or members with fine irregularities on a surface; titanium oxide; aluminum oxide; magnesium oxide; and opal glass. The materials do not necessarily need to be black or dark if they are colored by a dye or pigment complementary to the color produced by a light-modulating layer 24.
The pixel electrodes 105 are formed of transparent electrodes (ITO). The organic EL film 15 is formed on the pixel electrodes 105. As an electric field is applied to an EL element 15 pinched between the cathode electrode 106 and pixel electrode 105, the EL element 15 emits light.
A problem is that all the EL layers 15 to which the electric field is applied emit light. Areas which are located under the pixel electrodes 105 and in which the transistors 11 and gate signal lines 17 are formed are impervious to light (they are referred to as nontransparent areas). Even if the EL layers 15 in the nontransparent areas emit light, the emitted light is blocked. However, power is consumed if light is emitted. Thus, the larger the EL layers in the nontransparent areas, the lower the power efficiency.
To solve this problem, according to the present invention, an insulating film 681 is formed in non-luminous areas as illustrated in
The insulating film is, for example, a thin film of inorganic material such as SiO2, SiO, TiO2, or Al2O3.
Alternatively, it may be a thin or thick film of organic material such as acrylic resin or resist. Incidentally, the pixel electrodes in the nontransparent areas may be removed by patterning. Also, needless to say, thin metal film and the like forming the cathode may be removed by patterning.
As the insulating film 681 is formed or the electrodes of EL elements 15 are removed by patterning, electric charges are not poured into the EL layers 15. Consequently, the EL elements 15 in the non-luminous areas do not emit light. This results in improved power efficiency.
Incidentally, needless to say, pixel size may be varied among R, G, and B as illustrated in
To increase the quantity of light emitted from the board 71 to the outside, it is recommended to form a diffraction grating illustrated in
This increases the amount of light emitted from the board 71, achieving a high-brightness display.
a) shows an example in which a diffraction grating 691 is formed on pixel electrodes 105. Diffraction effect can be obtained by patterning the pixel electrodes 105 or forming a diffraction grating under or on the pixel electrodes 105.
The shape of diffraction grating may be circular, triangular, serrated, rectangular, or sinusoidal.
However, in terms of characteristics and efficiency, preferably the diffraction grating is sinusoidal. Preferably, the pitch of the diffraction grating is between 1 μm and 20 μm (both inclusive). More preferably, it is between 2 μm and 10 μm (both inclusive). Preferably, the height of the diffraction grating is between 2 μm and 20 μm (both inclusive). More preferably, it is between 3 μm and 10 μm (both inclusive). Also, preferably, the diffraction grating is three-dimensional (dot-matrix) rather than linear (two-dimensional). This is because linear shape will cause polarization dependence.
b) shows an example in which a diffraction grating 691 is formed on cathode electrodes 106. Diffraction effect can be obtained by patterning the cathode electrode 106 or forming a diffraction grating under or on the cathode electrode 106.
The diffraction gratings 691a and 691b can be formed to be two-dimensional (linear) and the formation direction of the diffraction gratings 691a and 691b can be configured to be orthogonal to each other. Of course, needless to say, one or both of the diffraction gratings 691a and 691b may be three-dimensional.
Preferably, LDD (low doped drain) structure is used for the transistors 11. The EL elements will be described herein taking organic EL elements (known by various abbreviations including OEL, PEL, PLED, OLED) 15 as an example, but this is not restrictive and inorganic EL elements may be used as well.
An organic EL display panel of active-matrix type must satisfy two conditions that:
1. it is capable of selecting a specific pixel and give necessary information and
2. it is capable of passing current through the EL element throughout one frame period.
To satisfy the two conditions, in a conventional organic EL pixel configuration shown in
To display a gradation using this configuration, a voltage corresponding to the gradation must be applied the gate of the driver transistor 11a. Consequently, variations in a turn-on current of the driver transistor 11a appear directly in display.
The turn-on current of a transistor is extremely uniform if the transistor is monocrystalline (ex. a transistor formed on a silicon substrate). However, in the case of a low-temperature polycrystalline transistor formed on an inexpensive glass substrate by low-temperature polysilicon technology at a temperature not higher than 450, its threshold varies in a range of ±0.2 V to 0.5 V. The turn-on current flowing through the driver transistor 11a varies accordingly, causing display irregularities. The irregularities are caused not only by variations in the threshold voltage, but also by mobility of the transistor and thickness of a gate insulating film. Characteristics also change due to degradation of the transistor 11.
Variations in the characteristics of the transistor is not limited to low-temperature polysilicon technologies, and can occur in transistors formed on semiconductor films grown in solid-phase (CGS) by high-temperature polysilicon technology at a process temperature of 450 degrees (centigrade) or higher. Besides, the phenomenon can occur in organic transistors and amorphous silicon transistors. Description will be given herein mainly of transistors produced by the low-temperature polysilicon technology.
In a method which displays gradations by the application of voltage as shown in
Each pixel structure in an EL display panel according to the present invention comprises four transistors 11 and an EL element as shown concretely in
In this circuit, a single pixel contains four transistors 11. The gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to the gate signal line 17a. The drain of the transistor 11b is connected to the source of the transistor 11c and source of the transistor 11d. The drain of the transistor 11c is connected to the source signal line 18. The gate of the transistor 11d is connected to the gate signal line 17b and the drain of the transistor 11d is connected to the anode electrode of the EL element 15.
Incidentally, the transistors 11b and 11c are examples of the second switching elements according to the present invention. On the other hand, the transistor 11d is an example of the first switching elements according to the present invention.
As the gate signal line (a first scanning line) 17a is activated (a turn-on voltage is applied), the driver transistor 11a and switching transistor 11c of the EL element 15 are turned on. At the same time, the current to be passed through the EL element 15 is delivered by the source driver circuit 14.
Also, the transistor 11b turns on to short-circuit the gate and drain of the transistor 11a and the current delivered by the source driver circuit 14 is stored in a capacitor (storage capacitance, additional capacitance) 19 connected between the gate and source of the transistor 11a (see
Next, the gate signal line 17a is deactivated (a turn-off voltage is applied), a gate signal line 17b is activated, and a current path is switched to a path which includes the first transistor 11a, a transistor 11d connected to the EL element 15, and the EL element 15 to deliver the stored current to the EL element 15 (see
If the capacity of the capacitor 19 needed for a single pixel is Cs (pF) and an area (pixel size rather than an aperture ratio) occupied by the pixel is Sp (square μm), a condition 500/Sp≦Cs≦20000/Sp, and more preferably a condition 1000/Sp≦Cs≦10000/Sp should be satisfied. Incidentally, since gate capacity of the transistor is small, Cs as referred to here can be regarded as the capacity of the storage capacitance (capacitor) 19 alone.
Preferably, the capacitors 19 are generally formed in non-display areas of pixels. Generally, for full-color organic EL 15, the organic EL layers 15 are formed by masked vapor deposition using metal masks. If masks are misaligned, there is a danger that the organic EL layers 15 (15R, 15G, and 15B) of different colors may overlap. Thus, adjacent pixels of different colors must be separated 10μ or more by non-display areas. These areas do not contribute to light-emission (non-luminous areas). Thus, by forming the storage capacitance 19 in these areas, it is possible to make effective use of the space in the pixels, providing an effective means of increasing an aperture ratio.
Incidentally, all the transistors in
In
Optimally, P-channel transistors should be used for all the transistors 11 composing pixels as well as for the built-in gate driver circuit 12. By composing an array solely of P-channel transistors, it is possible to reduce the number of masks to 5, resulting in low costs and high yields.
The current-driven pixel configurations in
A checking method according to the present invention will be described below.
The driver transistor 11a operates in such a way as to pass a predetermined programming current Iw. That is, the potential at the gate (G) terminal of the driver transistor 11a changes. The potential at the gate (G) terminal of the driver transistor 11a required to pass the predetermined programming current Iw is denoted by Vt.
For example, to pass the current Iw through the driver transistor 11a of a pixel, the potential at its gate (G) terminal must be lower than the Vdd voltage by Vt2 (solid line in
That is, the potential at the gate terminal of the driver transistor 11a of the selected pixel 16 becomes the potential of the source signal line 18. Since the current passed by a driver transistor 11a is determined by adjusting the potential at the gate terminal of the driver transistor 11a, it is possible to measure characteristics of the driver transistor 11a by looking at the potential at the gate terminal of the driver transistor 11a. Also, defects which occur in the pixel 16 cause the source signal line 18 to output an abnormal potential. Thus, defects and the like can be detected.
Apply a turn-on voltage to one gate signal line 17a by controlling the gate drive circuit 12. That is, select pixel rows one by one in sequence (a turn-off voltage is applied to the other gate signal lines 17a). Also, set the source signal line 18 to pass the current Iw. As a turn-on voltage is applied to the gate signal line 17a, the gate terminal of the driver transistor 11a of the selected pixel 16 assumes the Vt voltage required to pass the predetermined current Iw.
Apply a turn-off voltage to the gate signal line 17b.
The application of the turn-off voltage turns off the transistor 11d, cutting off the driver transistor 11a and EL element 15 from each other. Thus, the checking method according to the present invention can be applied even to an array board on which EL elements 15 are yet to be formed.
In this way, as the location of the gate signal line 17a to which a turn-on voltage is applied is shifted in sequence in sync with a horizontal scanning period (1 H), the potential of the source signal line 18 changes as illustrated in
In the checking system (checking device, checking method) according to the present invention, it may be apparent that two or more pixel rows may be selected simultaneously. This is because pixel defects and the like can be detected if an abnormal output is sent to the source signal line 18 even if two or more pixel rows are selected simultaneously. The current outputted from the pixel 16 being checked is a minute current on the order of μA. If short-circuit defects or the like occur in the pixel 16, an output at least on the order of mA is sent to the source signal line 18. Thus, two or more pixel rows can be selected and checked simultaneously. In extreme cases, all the pixel rows in the display area 50 can be selected and checked at once. Also, half the screen 50 may be checked at a time.
The programming current Iw is set to between 1 μA and 10 μA. Basically, use the maximum current needed to drive the panel. Alternatively, a small current not larger than 100 nA may be used for measurement to examine black writing mode (during black display).
The reference voltage Va outputted by the reference voltage circuit 991 is applied to the plus terminal (positive terminal) of the operational amplifier 995. The plus terminal and minus terminal of the operational amplifier are at the same potential, and thus the same current Iw (=Va/Rm) that flows through the source signal line 18 flows through the transistor 994. Consequently, a constant current Iw flows through all the source signal lines 18. The current Iw can be changed easily by changing the reference voltage Va.
Incidentally, although it is stated herein that the same current Iw is passed through all the source signal lines 18, this is not restrictive. For example, checks may be run by passing different constant currents through adjacent source signal lines 18. Also, the method of connecting the probe 997 to the electrode 996 is not limited to the one described above. For example, they may be bonded by an ACF technique.
Also, gold bumps or nickel bumps may be used for the connection.
Also, in the checking method according to the present invention, although it is stated herein that constant current Iw is passed through the source signal lines 18, this is not restrictive. For example, current (alternating current) having a rectangular waveform may be used for the checking.
It is also possible to use two modes in combination: a first mode in which voltage is applied to source signal lines 18 to detect a short circuit between adjacent source signal lines 18 and a second mode in which constant current is passed through source signal lines 18 to detect pixel defects. It is also possible to perform checking by applying signals (voltage or current) to the cathode electrode and anode electrode of an EL element 15 and detecting or measuring the signals by a source signal line 18.
With the configuration in
The source signal lines 18, through which minute current flows, are in a high-impedance state. To measure changes (or their absolute values) in the potential of the source signal lines 18 properly in this state, a high-impedance circuit (a positive input terminal of an input operational amplifier consisting of a FET circuit) is connected to each source signal line 18. That is, the probes 997 are electrically connected with the positive input terminals of the input operational amplifiers (not shown) of the respective input circuits 993.
A QCIF panel has 176×RGB=528 source signal lines 18. It is difficult to place AD converters on all the source signal lines 18. Thus, a multiplexer type analog switch (not shown) is placed on the output side of the input operational amplifier of each input circuit 993. An AD converter is placed at the output of the analog switch and data from the AD converter is captured into the PC 992. In
c) shows a data capture signal to data input means 992 (this signal can also be viewed as an analog switch changeover signal in the input circuit 993). Data is captured into the data input means 992 on a rising edge of the data capture signal. The PC 992 evaluates/judges values of the captured data.
Also, it accumulates the values of the data. Based on obtained results, defect state, defect locations, defect mode, faulty conditions, etc. of the array or panel are detected or checked.
With the pixel configuration in
If a short circuit (referred to as an SD short or channel short) occurs between the source terminal S and drain terminal D of the transistor 11a, the Vdd voltage is outputted to the source signal line 18 (the SD short in
Also, if the gate signal line 17a is broken, no path is formed for the programming current Iw, and thus the potential of the source signal line 18 becomes close to ground potential (see a broken gate signal line in
Also, with a turn-off voltage applied to all the gate signal lines 17a, if an unusual voltage is outputted to the source signal line 18, it can be detected that the transistor 11c or 11b of some pixel 16 is defective. Also, the signal outputted to the source signal line 18 varies with whether the Vdd voltage (anode voltage) is applied or the Vdd terminal is opened. This makes it possible to check and examine defects in the pixel 16 in detail. Regarding the cathode electrode, since the signal outputted to the source signal line 18 varies again with signal applications, it is possible to detect defects in the pixel 16.
Needless to say, it is also possible to detect defects in a pixel 16 by applying a signal to the source signal line 18 and detecting a signal outputted to the cathode electrode, conversely. Again, pixel rows can be scanned by selecting them one by one with a turn-on voltage.
While the pixel row selected by the gate driver circuit 12 is shifted in sequence, the potential of the source signal line 18 is measured sequentially in sync with the shift operation. The display panel (array board 71) can be checked when the above operation is repeated from top to bottom of the screen 50 (checks on one pixel column are completed).
As illustrated in
As illustrated in
The checking method according to the present invention checks pixels 16 by controlling the gate driver circuit 12, thereby applying a turn-on voltage to at least one gate signal line 17a, and thereby passing programming current through the source signal line 18.
Incidentally, although it has been stated in the above example that the Vt outputted to the source signal line 18 is measured or checked by selecting pixel rows one by one, this is not restrictive. Two or more pixel rows may be selected simultaneously. It is also possible to check odd-numbered pixels 16 in sequence first by selecting odd-numbered pixel rows in sequence and then check even-numbered pixels 16 in sequence by selecting even-numbered pixel rows in sequence.
Pixel defects (broken gate signal lines, SD shorts, etc.) can also be detected in this way as illustrated in
To speed up checking, a plurality of gate signal lines 17a can be selected, approximate defect locations and defect mode can be detected, and then a turn-on voltage can be applied to each gate signal line 17a in a portion having defects in sequence to identify the defect locations and defect state.
The checking method according to the present invention does not require that all the source signal lines 18 should be probed at once. For example, the checking method according to the present invention may be performed by connecting probes 997 to the terminal electrodes 996 of the odd-numbered source signal lines 18b with the even-numbered source signal lines 18a kept open, and then by connecting probes 997 to the terminal electrodes 996 of the even-numbered source signal lines 18a with the odd-numbered source signal lines 18b kept open.
Of course, every fourth pixel column may be probed by shifting in sequence.
Incidentally, although the gate driver circuit 12 in
Although it has been stated with reference to
The checking system with the pixel configuration in
As described above, the checking system (checking device, checking method) according to the present invention relates to an EL display apparatus or an array board 71 used in the EL display apparatus. The checking system performs checking by applying a selection voltage to a gate signal line 17a which selects a pixel 16 and thereby connecting the driver transistor 11a of the pixel to a source signal line 18. Also, by applying a signal such as a voltage (or current) to a terminal (signal line) such as a cathode or anode electrode which receives external inputs, the checking system detects whether the signal is outputted from the source signal line 18. Basically, it performs checking by applying a constant current to the source signal lines 18. Also, it selects and scans the gate signal lines 17a in sequence.
Preferably, in the display panel, the source driver circuit 14 is not formed directly on the array board 71.
This will ease checking. Preferably, checking is performed before sealing glass (sealing lid) is installed after EL elements 15 are formed on the array board 71. This will reduce the cost of discarding non-conforming panels.
To facilitate understanding, the configuration of the EL element in
The second timing is the one when the transistor 11a and transistor 11c are closed and the transistor 11d is opened. The equivalent circuit available at this time is shown in
Display results of this operation are shown in
In the pixel configuration in
During a period when the current flows through the EL element 15, the transistors 11c and 11b turn off and the transistor 11d turns on as shown in
A timing chart is shown in
As can be seen from
Incidentally, the gate of the transistor 11a and gate of the transistor 11c are connected to the same gate signal line 17a. However, the gate of the transistor 11a and gate of the transistor 11c may be connected to different gate signal lines 17 (see
By sharing the gate signal line 17a and gate signal line 17b and using different conductivity types (N-channel and P-channel) for the transistors 11c and 11d, it is possible to simplify the drive circuit and improve the aperture ratio of pixels.
With this configuration, a write paths from signal lines are turned off according to operation timing of the present invention That is, when a predetermined current is stored, an accurate current value is not stored in a capacitance (capacitor) between the source (S) and gate (G) of the transistor 11a if a current path is branched. By using different conductivity types for the transistors 11c and 11d and controlling their thresholds, it is possible to ensure that when scanning lines are switched, the transistor 11d is turned on after the transistor 11c is turned off.
Incidentally, although it has been stated with reference to
This also applies to the examples described below.
In that case, however, since the thresholds of the transistors must be controlled accurately, it is necessary to pay attention to processes. The circuit described above can be implemented using four transistors at the minimum, but even if more than four transistors including a transistor 11e are cascaded for more accurate timing control or for reduction of mirror effect (described later), the principle of operation is the same. By adding the transistor 11e, it is possible to deliver programming current to the EL element 15 more precisely via the transistor 11c.
Referring to
This configuration makes it possible to pass minute current from the driver transistor 11a through the EL element 15 accurately. Also, by controlling the voltage applied to the gate terminal of the transistor 11e (applied to the gate signal line 17f), it is possible to vary conditions of current output from the driver transistor 11a. Incidentally, the same voltage as the voltage applied to the gate signal line 17f is applied to the pixels in the display area. Of course, it is possible to form a gate driver circuit 12, which drives the gate signal line 17f, and apply an ac signal to the gate signal line 17f by operating the gate driver circuit 12.
Incidentally, gate signal line 17a, gate signal line 17b, and gate signal line 17f may be driven by different gate driver circuits or by a single gate driver circuit 12 as shown in FIG. 2. The other part of the configuration is the same as that shown in
Incidentally, the pixel configuration is not limited to those shown in
In
A terminal b of the changeover switch 631 is connected to cathode voltage (indicated as ground in
A terminal c of the changeover switch 631 is connected with a cathode terminal of the EL element 15. Incidentally, the changeover switch 631 may be of any type as long as it has a capability to turn on and off the current flowing through the EL element 15. Thus, its installation location is not limited to the one shown in
Also, the term “off” here does not mean a state in which no current flows, but it means a state in which the current flowing through the EL element 15 is reduced to below normal. The items mentioned above also apply to other configurations of the present invention.
The changeover switch 631 will require no explanation because it can be implemented easily by a combination of P-channel and N-channel transistors. For example, it can be implemented by two circuits of analog switches. Of course, the switch 631 can be constructed of only P-channel or N-channel transistors because it only turns off the current flowing through the EL element 15.
When the switch 631 is connected to the terminal a, the Vdd voltage is applied to the cathode terminal of the EL element 15. Thus, current does not flow through the EL element 15 regardless of the voltage state of voltage held by the gate terminal G of the driver transistor 11a. Consequently, the EL element 15 is non-illuminated.
When the switch 631 is connected to the terminal b, the GND voltage is applied to the cathode terminal of the EL element 15. Thus, current flows through the EL element 15 according to the state of voltage held by the gate terminal G of the driver transistor 11a. Consequently, the EL element 15 is illuminated.
Thus, in the pixel configuration shown in
In the pixel configurations shown in
In
In the example shown in
Variations in the characteristics of the transistor 11a are correlated to the transistor size. To reduce the variations in the characteristics, preferably the channel length of the first transistor 11a is from 5 μm to 100 μm (both inclusive). More preferably, it is from 10 μm to 50 μm (both inclusive). This is probably because a long channel length L increases grain boundaries contained in the channel, reducing electric fields, and thereby suppressing kink effect.
Preferably, the transistors 11 of the pixels are polysilicon transistors formed by laser recrystallization (laser annealing) and the channel directions of all the transistors coincide with the direction of laser emission. In particular, it is preferable that the direction of laser emission coincides with the formation direction of the source signal lines 18. This will make the characteristics of the driver transistors 11a along the source signal lines 18 uniform and reduce amplitude fluctuations of the source signal lines 18 during current programming. Reduced amplitudes make it possible to perform current programming accurately.
An object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect display. Four or more transistors are required for that. When determining circuit constants using transistor characteristics, it is difficult to determine appropriate circuit constants unless the characteristics of the four transistors are not consistent. Both thresholds of transistor characteristics and mobility of the transistors vary depending on whether the channel direction is horizontal or vertical with respect to the longitudinal axis of laser irradiation.
Incidentally, variations are more of the same in both cases. However, the mobility and average threshold vary between the horizontal direction and vertical direction. Thus, it is desirable that all the transistors in a pixel have the same channel direction.
Also, if the capacitance value of the storage capacitance 19 is Cs and the turn-off current value of the second transistor 11b is Ioff, preferably the following equation is satisfied.
3<Cs/Ioff<24
More preferably the following equation is satisfied.
6<Cs/Ioff<18
By setting the turn-off current of the transistor 11b to 5 pA or less, it is possible to reduce changes in the current flowing through the EL to 2% or less. This is because when leakage current increases, electric charges stored between the gate and source (across the capacitor) cannot be held for one field with no voltage applied. Thus, the larger the storage capacity of the capacitor 19, the larger the permissible amount of the turn-off current. By satisfying the above equation, it is possible to reduce fluctuations in current values between adjacent pixels to 2% or less.
Also, preferably transistors composing an active matrix are p-channel polysilicon thin-film transistors and the transistor 11b is a dual-gate or multi-gate transistor. More preferably, the transistor has three or more gates. Unless the transistor 11b has good turn-off characteristics, the capacitor 19 cannot hold electric charges. This will cause excessive brightness resulting in a whitish screen.
As high an ON/OFF ratio as possible is required of the transistor 11b, which acts as a source-drain switch for the transistor 11a. By using a dual-gate or multi-gate structure for the transistor 11b, it is possible to achieve a high ON/OFF ratio.
The semiconductor films composing the transistors 11 in the pixel 16 are generally formed by laser annealing in low-temperature polysilicon technology. Variations in laser annealing conditions result in variations in transistor 11 characteristics. However, if the characteristics of the transistors 11 in the pixel 16 are consistent, it is possible to drive the pixel using current programming such as the one shown in
Incidentally, the formation of the semiconductor film of the transistor 11 according to the present invention is not limited to the laser annealing method. The present invention may also use a heat annealing method and a method which involves solid-phase (CGS) growth. Besides, the present invention is not limited to the low-temperature polysilicon technology and may use high-temperature polysilicon technology. Also, the semiconductor films may be formed by performing doping and diffusion on a silicon substrate. Also, the semiconductor films may be formed of organic material.
The present invention moves a laser spot (laser irradiation range) 72 in parallel to the source signal line 18 as shown in
Pixels are constructed in such a way that three pixels of RGB will form a square shape. Thus, each of the R, G, B pixels has oblong shape. Consequently, by performing annealing using an oblong laser spot 72, it is possible to eliminate variations in the characteristics of the transistors 11 within each pixel. Also, the characteristics (mobility, Vt, S value, etc.) of the transistors 11 connected to the same source signal line 18 can be made uniform (i.e., although the transistors 11 connected to adjacent source signal lines 18 may differ in characteristics, the characteristics of the transistors 11 connected to the same source signal line can be made almost equal).
Generally, the laser spot 72 has a fixed length such as 10 inches. Since the laser spot 72 is moved, the panels must be placed in such a way that they can fit in a range in which the laser spot 72 can be moved (i.e., in such a way that laser spots 72 will not overlap in the center of a panel's display area 50).
In the configuration shown in
Preferably, the laser annealing method (which involves emitting a linear laser spot in parallel to the source signal line 18) described with reference to
For example, in the case of white raster display, since almost the same current is passed through the transistors 11a in adjacent pixels, the current outputted from the source driver IC 14 does not have significant amplitude changes. If the transistors 11a in
A method which involves programming two or more pixel rows simultaneously and which are described with reference to
Incidentally, although an IC chip is illustrated in
The present invention, in particular, ensures that a voltage threshold Vth2 of the driver transistor 11b will not fall below a voltage threshold Vth1 of the corresponding driver transistor 11a in the pixel. For example, gate length L2 of the transistor 11b is made longer than gate length L1 of the transistor 11a so that Vth2 will not fall below Vth1 even if process parameters of these thin-film transistors change. This makes it possible to suppress subtle current leakage.
Incidentally, the items mentioned above also apply to pixel configuration of a current mirror shown in
In
Next, the EL display panel or EL display apparatus of the present invention will be described.
Incidentally, the minimum output current of one current mirror circuit is from 10 nA to 50 nA (both inclusive). Preferably, the minimum output current of the current mirror circuit should be from 15 nA to 35 nA (both inclusive) to secure accuracy of the transistors composing the current mirror circuit in the driver IC 14.
Besides, a precharge or discharge circuit is incorporated to charge or discharge the source signal line 18 forcibly. Preferably, voltage (current) output values of the precharge or discharge circuit which charges or discharges the source signal line 18 forcibly can be set separately for R, G, and B. This is because the thresholds of the EL element 15 differ among R, G, and B.
Organic EL elements are known to have heavy temperature dependence (temperature characteristics). To adjust changes in emission brightness caused by the temperature characteristics, reference current is made in an analog fashion by adding nonlinear elements such as thermistors or posistors to the current mirror circuits to vary output current and adjusting the changes due to the temperature characteristics with the thermistors or the like.
According to the present invention, the source driver circuit 14 is made of a semiconductor silicon chip and connected with a terminal on the source signal line 18 of the board 71 by chip-on-glass (COG) technology. Metals such as chromium, copper, aluminum, and silver are used for wiring of signal lines such as the source signal lines 18. These metals provide low resistance with thin wiring width. If pixels are a reflective type, preferably the wiring is formed of the same material as reflecting films simultaneously with the reflecting films. This will simplify production processes.
The source driver circuit 14 can be mounted not only by the COG technology. It is also possible to mount the source driver circuit 14 by chip-on-film (COF) technology and connect it to the signal lines of the display panel. Regarding the driver IC, it may be made of three chips by constructing a power supply IC 82 separately.
On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed in the same process as the transistors in pixels. This is because the gate driver circuit 12 has a simpler internal structure and lower operating frequency than the source driver circuit 14. Thus, it can be formed easily even by low-temperature polysilicon technology and allows bezel width to be reduced. Of course, it is possible to construct the gate driver circuit 12 from a silicon chip and mount it on the board 71 using the COG technology. Also, switching elements such as pixel transistors as well as gate drivers may be formed by high-temperature polysilicon technology or may be formed of an organic material (organic transistors).
The gate driver circuit 12 incorporates a shift register circuit 61a for a gate signal line 17a and a shift register circuit 61b for a gate signal line 17b. The shift register circuits 61 are controlled by positive-phase and negative-phase clock signals (CLKxP and CLKxN) and a start pulse (STx). Besides, it is preferable to add an enable (ENABL) signal which controls output and non-output from the gate signal line and an up-down (UPDWN) signal which turns a shift direction upside down. Also, it is preferable to install an output terminal to ensure that the start pulse is shifted by the shift register and is outputted. Incidentally, shift timings of the shift registers are controlled by a control signal from a control IC 81. Also, the gate driver circuit 12 incorporates a level shift circuit which level-shifts external data. It also incorporates a checking circuit.
Since the shift register circuits 61 have small buffer capacity, they cannot drive the gate signal lines 17 directly. Therefore, at least two or more inverter circuits 62 are formed between each shift register circuit 61 and an output gate 63 which drives the gate signal line 17.
The same applies to cases in which the source driver circuit 14 is formed on the board 71 by polysilicon technology such as low-temperature polysilicon technology. A plurality of inverter circuits are formed between an analog switching gate such as a transfer gate which drives the source signal line 18 and the shift register of the source driver circuit 14. The following matters (shift register output and output stages which drive signal lines (inverter circuits placed between output stages such as output gates or transfer gates)) are common to the gate driver circuit and source driver circuit.
For example, although the output from the source driver circuit 14 is shown in
The inverter circuit 62 consists of a P-channel MOS transistor and N-channel MOS transistor. As described earlier, the shift register circuit 61 of the gate driver circuit 12 has its output end connected with multiple stages of inverter circuits 62 and the final output is connected to the output gate 63. Incidentally, the inverter circuit 62 may be composed solely of P-channel MOS transistors or N-channel MOS transistors.
The shift register circuit 61a of the gate driver circuit 12 controls control signals for the gate signal lines 17a while the shift register circuit 61b controls control signals for the gate signal lines 17b. An output buffer 63 is formed or placed in the output stage of the inverter 62. Incidentally, the buffer and the like are formed on the array board 71 using low-temperature polysilicon process technology.
As illustrated in
Incidentally, the gate driver circuit 12 in
The gate driver circuit 12 in
As illustrated in
Since only p-channel transistors are used for the gate driver circuits 12 in
If the pixels 16 are constructed of P-channel transistors, they will match well with the gate driver circuits 12 which employ P-channel transistors shown in
Also, by using P-channel for the driver transistors (transistor 11a in
The level shifter (LS) circuit may be formed directly on the array board 71. That is, N-channel and P-channel transistors are used for the level shifter (LS) circuit. A logic signal from a controller (not shown) is boosted by the level shifter circuit formed directly on the array board 71 so that it will match the logic level of the gate driver circuits 12 constructed from a P-channel transistor. The boosted logic voltage is applied to the gate driver circuits 12.
For ease of explanation, the pixel configuration in
Also, it is applicable to two transistors (selection transistor is transistor 11b and driver transistor is transistor 11a) such as those illustrated in
Also, the configuration in which p-channel transistors are used as selection transistors of pixels 16 and for gate driver circuits is not limited to organic EL or other self-luminous devices (display panels or display apparatus). For example, it is also applicable to liquid crystal display panels.
The inverting terminals (DIRA and DIRB) apply common signals to all the unit gate output circuits 1111.
As can be seen from an equivalent circuit diagram in
Incidentally, the circuit configuration in
The clock signals (SCK0, SCK1, SCK2, and SCK3) are fed differently between adjacent unit gate output circuits 1111. For example, in the unit gate output circuit 1111a, OC is fed by the clock terminal SCK0 while RST is fed by the clock terminal SCK2. This is also the case with the unit gate output circuit 1111c. However, in the unit gate output circuit 1111b (the unit gate output circuit in the next stage) adjacent to the unit gate output circuit 1111a, OC is fed by the clock terminal SCK1 while RST is fed by the clock terminal SCK3. In this way, every other unit gate output circuit 1111 is fed by clock terminals in a different manner: OC is fed by SCK0 and RST is fed by SCK2, OC is fed by SCK1 and RST is fed by SCK3 in the next stage, OC is fed by SCK0 and RST is fed by SCK2 in the next stage, and so on.
When driver circuits are built solely of P-channel transistors, it is basically difficult to maintain the output voltage of the gate signal lines 17 at an H level (Vd voltage in
In the circuit configuration in
According to the drive method in
Incidentally, although 165(b) shows a mode in which adjacent rows of pixels are selected, it is also possible to select rows of pixels other than adjacent pixel rows as shown in
In
According to the present invention, pixel rows equal in number as a clock count make a set, and one pixel row or pixel rows no larger in number than half the pixel rows in each set are selected (for example, two pixel rows (=4/2) are selected if four pixel rows make a set). Thus, there are always non-selected pixel rows in each set of pixel rows.
When one pixel row is selected as shown in
Operation of the selection-side gate driver circuit 12a is shown in
b) shows a state which results when a turn-on voltage is applied to the gate signal lines 17b of two pixel rows in each 4-pixel-row set. The location of a displayed pixel row 53 shifts one by one in sync with a horizontal synchronization signal (HD). Of course, it is free to decide whether to select two pixel rows (apply a turn-off voltage to the gate signal lines 17b of the other two pixel rows) or no pixel row (apply a turn-off voltage to the gate signal lines 17b of the four pixel rows) in the 4-pixel-row set. Since this is configured into the shift register, the selection is shifted in sync with a horizontal synchronization signal.
a) shows a state which results when a turn-on voltage is applied to the gate signal line 17b of one pixel row in each 4-pixel-row set.
As described earlier, the subscript in the gate signal line 17b( ) indicates a pixel row. Incidentally, for ease of explanation, pixel rows begin with (1). Also, the numerals in the top row of the table indicate horizontal scanning period numbers.
As illustrated in
According to the example in
Thus, in
That is, in white raster display, maximum brightness is obtained when 55 pixel rows are displayed. The display screen can be made darker by decreasing the number of displayed pixel rows as follows: 55→54→53→52→51→ . . . 5→4→3→2→1→0. Conversely, the screen can be made brighter by increasing the number of displayed pixel rows as follows: 0→1→2→3→4→5→ . . . 50→51→52→53→54→55. Thus, the brightness can be adjusted in multiple steps.
In this brightness adjustment, the brightness of the screen changes linearly in proportion to the number of displayed pixel rows. Besides, gamma characteristics which correspond to the brightness do not change (the number of gradations remains constant regardless of whether the screen is bright or dark).
Although in the above example, the number of displayed pixel rows is changed in increments of 1 to adjust the brightness of the screen 50, this is not restrictive. It may be changed as follows: 54→52→50→48→46→ . . . 6→4→2→0. Alternatively, it may be changed as follows: 55→50→45→40→35→ . . . 15→10→5→0.
Similarly, in
Although the number of displayed pixel rows is changed in increments of 2 to adjust the brightness of the screen 50, this is not restrictive. It may be changed in increments of 4 or more than 4. When curtailing displayed pixel rows to adjust brightness, preferably pixel rows are curtailed in a distributed manner wherever possible rather than in a concentrated manner. This is to reduce flickering.
Brightness can also be adjusted by varying illumination time per horizontal scanning period instead of using the number of pixel rows (the pixel rows are illuminated or non-illuminated approximately over an entire horizontal scanning period). That is, the brightness of the display screen is adjusted by illuminating pixel rows for part of one horizontal scanning period (e.g., for ⅛ of 1H or for 15/16 of 1H).
This adjustment (control) is performed using a main clock (MCLK) of the display panel.
In the case of a QCIF panel, MCLK is approximately 2.5 MHz.
This means that 176 clock pulses can be counted in one horizontal scanning period (1 H). Thus, by counting MCLK pulses and controlling the duration for which a turn-on voltage (Vgl) is applied to the gate signal lines 17b based on the count value, it is possible to turn on and off the EL elements 15 in each pixel row.
Specifically, this can be done by controlling the positions where the clocks (SCK) are set to the low level and the duration for which the clocks (SCK) are set to the low level in timing charts in
With the drive method in
Similarly, in (b) of
With the drive method in
Similarly, in (b) of
Incidentally, if the clock is adjusted by changing the configuration of the gate driver circuit 12 somewhat, the voltage can be applied to the gate signal lines 17b in
The drive method in
However, in the case of a driver circuit (shift register) which is composed or formed of p-channel transistors, on-illuminated pixel rows 52 are at least placed (inserted) among displayed pixel rows 53.
This condition depends on persistence of human vision. That is, images which blink faster than at predetermined intervals appear to illuminate continuously because of the human vision. This results in blurred moving pictures. However, when images blink slower than at predetermined intervals, although they visually appear to be continuous, inserted non-display (black display) areas become recognizable and the displayed images become discrete (although nothing looks unusual visually). Consequently, in movie display, images become discrete and no image blur occurs. That is, blurred moving pictures are eliminated.
In area A in
Incidentally, the term “area A” or “area B” is used above only for ease of explanation. In
As described above, with the drive method according to the present invention, in
In
Thus, when display modes of an arbitrary pixel row (pixels) is observed, the drive method according to the present invention alternates two periods: a first period during which image display and non-display are repeated at least once for a period of less than 4 msec (or less than ¼ of one frame (field) period) and a second period during which the pixel row (pixels) changes from display mode to non-display mode (black display or low-brightness display lower than a predetermined brightness) and enters display mode again after 4 msec or more (or ¼ of one frame (field) period or more). The above driving makes it possible to achieve proper image display. Also it uses a simple configuration of the control circuit (the gate driver circuit 12 and the like), resulting in reduced costs.
In
Incidentally, although one area B (period B) is shown in
However, in
Conversely, in the case of movie display, black display should be inserted for at least 4 msec as described with reference to
Thus, also in the case of movie display, it is possible to achieve more optimum image display by varying or adjusting the condition of black insertion. Needless to say, the above items also apply to examples described below.
An input image signal is checked for moving pictures (ID detection). If the signal represents moving pictures or contains many moving pictures, the drive system in
Switching between the drive systems in
The location of each gate signal line 17b to which a turn-on voltage is applied is scanned every pixel row.
Incidentally, although it has been stated in the above example that pixel rows are scanned one by one, the present invention is not limited to this. For example, in the case of interlaced scanning, pixel rows are scanned skipping one pixel row. That is, even-numbered pixel rows are scanned in the first field. Odd-numbered pixel rows are scanned in the second field. When the first field is being rewritten, the images written into the second field are retained. However, blinking is caused (or may not be caused). When the second field is being rewritten, the images written into the first field are retained. Of course, blinking may be caused as in the example of
In the case of interlaced scanning, one frame consists of two fields, which is normally the case with CRTs. However, the present invention is not limited to this. For example, one field may consist of four fields. In that case, images in the (4N+1)-th pixel rows are rewritten in the first field (where n is an integer not smaller than 1). Images in the (4N+2)-th pixel rows are rewritten in the second field. Images in the (4N+3)-th pixel rows are rewritten in the third field. Images in the (4N+4)-th pixel rows are rewritten in the final fourth field. Thus, writing into pixel rows according to the present invention is not limited to sequential scanning. The above items also apply to other examples. The interlaced scanning as referred to herein means typical skip scanning and is not limited to “2 fields=1 frame.” That is, one frame may consist of a plurality of fields.
Needless to say, the drive system in
As in the case of
As in the case of
Incidentally, in the above example, area A and area B coexist in the screen 50. That is, area A and area B always exist during any period in screen display mode (of course, the location of area A varies). This means that period A and period B exist in one field (one frame, i.e., a refresh period of the screen). However, since black insertion (black display or low-brightness display) can be used to improve movie display, the present invention is not limited to the drive system in
In
In the first field, the even-numbered pixel rows are selected in sequence to rewrite images as illustrated in
Incidentally, the words “images are written” and “images are displayed” are used in
However, the present invention is not limited to these display modes. To improve at least movie display condition, black insertion mode such as the one shown in
The drive system in the example of
A timing chart for an example described below is shown in
In
In
Incidentally, in
In the above example, the same turn-on/turn-off voltage patterns are applied to the gate signal lines 17b in each frame (unit period). However, according to the present invention, different pixel rows (pixels) are illuminated (display) or non-illuminated (non-display) for approximately equal durations during a predetermined period. Thus, in the drive system, where one frame consists of two fields, the signal waveforms applied to the first field and second field may vary among different gate signal lines 17b. For example, a turn-on voltage may be applied to an arbitrary pixel row for a period of 10 Hs in the first field, and for a period of 20 Hs in the second field (in a unit period of two fields, a turn-on voltage is applied for a period of 10 Hs+20 Hs). A turn-on voltage is also applied to the other pixel rows for a period of 30 Hs.
An example is shown in
Incidentally, although it has been stated with reference to
Although it has been stated in the above example that the total durations for which a turn-on voltage is applied during a unit period are equal among all the gate signal lines 17b, this does not apply to the following cases.
Such is the case when a screen 50 (i.e., one display panel) contains multiple screens 50 which differ in brightness. That is, for example, when the screen 50 consists of a first screen 50a and second screen 50b which differ in brightness. The two screens 50 can be varied in brightness by adjusting the programming current Iw, but they can be varied more easily by scanning the gate signal lines 17b and varying the illumination (display) period of pixel rows between the first screen 50a and second screen 50b. For example, regarding each pixel row in the first screen 50a, a turn-on voltage is applied to the gate signal lines 17b for 1 H in every 4 Hs. For each pixel row in the second screen 50b, a turn-on voltage is applied to the gate signal lines 17b for 1H in every 8 Hs. In this way, by varying the application duration of the turn-on voltage among different screens, it is possible to adjust screen brightness and make gamma curves of the screens similar to each other.
The power supply circuit (IC) 82 (see
Thus, the logic signals can be level-shifted (LS) conveniently by the power supply IC 82. For this reason, gate driver circuit 12 control signals outputted from a controller (not shown) are fed into the power supply IC 82 and level-shifted there before it is fed into the gate driver circuits 12 according to the present invention. Source driver circuit 14 control signals outputted from the controller (not shown) are fed into the source driver circuit 14 and the like according to the present invention (there is no need for level shifting).
However, the present invention does not limit all the transistors formed on the array board 71 to p-channel transistors. By using only p-channel transistors for the gate driver circuits 12 as described later with reference to
In the case of a 2.2-inch QCIP panel, the width of a gate driver circuit 12 can be reduced to 600 μm if a 6-μm rule is adopted. The width will be 700 μm even including power wiring of the gate driver circuit 12. If CMOS (n-channel and p-channel transistors) is used for a similar circuit configuration, the width will be increased to 1.2 mm. Thus, by using only p-channel transistors for the gate driver circuits 12, it is possible to achieve a characteristic effect of bezel width reduction.
Also, if the pixels 16 are constructed of p-channel transistors, they will match well with the gate driver circuits 12 which are composed of p-channel transistors. The p-channel transistors (the transistors 11b and 11c and transistor 11d in the pixel configuration in FIG. 1) turn on when the voltage becomes low (Vgl). On the other hand, the lower voltage serves as the selection voltage for the gate driver circuits 12 as well. Gate drivers with p-channel transistors achieve good matching if the lower level is used as the selection level as can be seen from a configuration in
Also, by using p-channel transistors for the driver transistors (transistor 11a in
The level shifter (LS) circuit may be formed directly on the array board 71. That is, n-channel and p-channel transistors are used for the level shifter (LS) circuit. A logic signal from a controller (not shown) is boosted by the level shifter circuit formed directly on the board 71 so that it will match the logic level of the gate driver circuits 12 constructed from a p-channel transistor. The boosted logic voltage is applied to the gate driver circuits 12.
Incidentally, the level shifter circuit may be constructed from a semiconductor chip and mounted on the board 71 using COG technology or the like. Also, the source driver circuit 14 is constructed basically from a semiconductor chip and mounted on the board 71 using COG technology. However, the source driver circuit 14 is not limited to being constructed from a semiconductor chip, and may be formed directly on the board 71 using polysilicon technology. If p-channel transistors are used as the transistors 11a of pixels 16, programming current flows in the direction from the pixels 16 to the source signal lines 18. Thus, n-channel transistors should be used as the constant-current circuit in the source driver circuit. That is, the source driver circuit 14 should be configured in such a way as to draw the programming current Iw.
Thus, if the driver transistors 11a of the pixels 16 (in the case of
In
Preferably, the source driver circuit 14 contains an image memory. Image data may go through an error diffusion process or dithering process before being stored in the image memory.
In
When the display panel is used for information display apparatus such as a cell phone, it is preferable to mount (form) the source driver IC (circuit) 14 and gate driver IC (circuit) 12 on one side of the display panel as shown in
Incidentally, the three-side free configuration includes not only a configuration in which ICs are placed or formed directly on the board 71, but also a configuration in which a film (TCP, TAB, or other technology) with a source driver IC (circuit) 14 and gate driver IC (circuit) 12 mounted are pasted on one side (or almost one side) of the board 71. That is, the three-side free configuration includes configurations and arrangements in which two sides are left free of ICs and all similar configurations.
If the gate driver circuit 12 is placed beside the source driver circuit 14 as shown in
Incidentally, the thick solid line in
Spacing between the gate signal lines 17 formed on the side C is from 5 μm to 12 μm (both inclusive). If it is less than 5 μm, parasitic capacitance will cause noise on adjacent gate signal lines. It has been shown experimentally that parasitic capacitance has significant effects when the spacing is 7 μm or less. Furthermore, when the spacing is less than 5 μm, beating noise and other image noise appear intensely on the display screen. In particular, noise generation differs between the right and left sides of the screen and it is difficult to reduce the beating noise and other image noise. When the spacing exceeds 12 μm, bezel width D of the display panel becomes too large to be practical.
To reduce the image noise, a ground pattern (conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) can be placed under or above the gate signal lines 17. Alternatively, a separate shield plate (shield foil: a conductive pattern which has been fixed at a constant voltage or set generally at a stable potential) may be placed on the gate signal lines 17.
The gate signal lines 17 on the side c in
Incidentally, although it has been stated with reference to
Also, the source driver IC 14 and gate driver IC 12 may be integrated into a single chip. Then, it suffices to mount only one IC chip on the display panel. This also reduces implementation costs. Furthermore, this makes it possible to simultaneously generate various voltages for use in the single-chip driver IC.
In the configuration shown in
For example, when a current of 0.01 A is delivered per square centimeter, the terminal voltage of the EL elements for blue (B) is 5 V while the terminal voltage of the EL elements for green (G) and red (R) is 9 V. That is, the terminal voltage for B differs from the terminal voltage for G and R. Thus, the source-drain voltage (SD voltage) of the transistor 11a for B differs from that for G and R. Consequently, drain-source off-leakage current differs among different colors. If off-leakage current occurs and off-leakage characteristics vary with the color, flickering occurs with color balance disturbed and gamma characteristics deviate in correlation with emitted colors, resulting in complicated display condition.
To deal with this problem, preferably the potential of the cathode electrode for one of at least the RGB colors is different from the potential of the cathode electrode for the other colors. Alternatively, it is preferable that the Vdd potential (anode potential) for one of the RGB colors is different from the Vdd potential for the other colors.
Needless to say, the terminal voltages of the EL elements 15 for R, G, and B are identical whenever possible. Material and structure should be selected in such a way that the terminal voltages of the EL elements for R, G, and B are 10 V or below at least at white peak brightness and in a color temperature range of 7000 K to 12000 K (both inclusive). Also, among R, G, and B, the difference between the maximum terminal voltage and minimum terminal voltage of the EL elements should be 2.5 V or less. For example, if the terminal voltage of the EL elements for R is 7 V when maximum current is passed through the EL elements 15, preferably the terminal voltage of the EL elements 15 for R, G and B should be between 7-2.5 V (minimum) and 7+2.5 V (maximum) both inclusive when maximum current is passed through the EL elements. More preferably, the difference should be 1.5 v or less.
Although it has been stated that pixels are of the three primary colors of R, G, and B, this is not restrictive. They may be of three colors of cyan, yellow, and magenta. They may be of two colors of B and yellow or the like. Of course, they may be monochromatic. Alternatively, they may be of six colors of R, G, B, cyan, yellow, and magenta or of five colors of R, G, B, cyan, and magenta. These are natural colors which provide an expanded color reproduction range, enabling good display. Besides, the pixels may be of four colors of R, G, B, and white. Alternatively, they may be of seven colors of R, G, B, cyan, yellow, magenta, black, and white. It is also possible to form (build) white light-emitting pixels over the entire display area 50 and produce the three primary colors using RGB color filters or the like. Also, a single pixel may be two-colored such as B and yellow. Thus, the EL display apparatus according to the present invention is not limited to those which provide color display using the three primary colors of R, G, and B.
Mainly three methods are available to colorize an organic EL display panel. One of them is a color conversion method. It suffices to form a single layer of blue as a light-emitting layer. The remaining green and red colors needed for full color display can be produced from the blue color through color conversion. Thus, this method has the advantage of eliminating the need to paint the R, G, and B colors separately and prepare organic EL materials for the R, G, and B colors. The color conversion method does not lower yields unlike the multi-color painting method. Any of the three methods can be applied to the EL display panel of the present invention.
Also, in addition to the three primary colors, white light-emitting pixels may be formed. The white light-emitting pixels can be created (formed or constructed) by laminating R, G, and B light-emitting structures. A set of pixels consists of pixels for the three primary colors RGB and a white light-emitting pixel 16. Forming the white light-emitting pixels makes it easier to express peak brightness of white, and thus possible to implement bright image display.
Even when using a set of pixels for the three primary colors RGB, it is preferable to vary pixel electrode areas for the different colors. Of course, an equal area may be used if luminous efficiencies of the different colors as well as color purity are well balanced.
However, if one or more colors are poorly balanced, preferably the pixel electrodes (light-emitting areas) are adjusted. The electrode area for each color can be determined based on current density. That is, when white balance is adjusted in a color temperature range of 7000 K (Kelvin) to 12000 K (both inclusive), difference between current densities of different colors should be within ±30%. More preferably, the difference should be within ±15%. For example, if current densities are around 100 A/square meter, all the three primary colors should have a current density of 70 A/square meter to 130 A/square meter (both inclusive). More preferably, all the three primary colors should have a current density of 85 A/square meter to 115 A/square meter (both inclusive).
The organic EL element 15 is a self-luminous element. When light from this self-luminous element enters a transistor serving as a switching element, a photoconductive phenomenon occurs. The photoconductive phenomenon is a phenomenon in which leakage (off-leakage) increases due to photoexcitation when a switching element such as a transistor is off.
To deal with this problem, the present invention forms a shading film under the gate driver circuit 12 (source driver circuit 14 in some cases) and under the pixel transistor 11. The shading film is formed of thin film of metal such as chromium and is from 50 nm to 150 nm thick (both inclusive). A thin film will provide a poor shading effect while a thick film will cause irregularities, making it difficult to pattern the transistor 11A1 in an upper layer.
A smoothing film made of inorganic material, 20 to 100 nm thick (both inclusive), is formed on the light-shielding film. One of the electrodes of the storage capacitance 19 may be formed of this layer of the light-shielding film. In that case, preferably the thickness of the smooth film is minimized to increase the capacitance value of the storage capacitance. It is also possible to form the light-shielding film of aluminum, form a silicon oxide film on the light-shielding film using anodizing technology, and use the silicon oxide film as a dielectric film for the storage capacitance 19. Pixel electrodes of a high aperture (HA) structure are formed on the smoothing film.
In the case of the driver circuit 12 and the like, it is necessary to reduce penetration of light not only from the topside, but also from the underside. This is because the photoconductive phenomenon will cause malfunctions. If cathode electrodes are made of metal films, the present invention also forms a cathode electrode on the surface of the driver 12 and the like and uses it as a shading film.
An antireflection film is formed on a light-emitting surface of the board 71. The antireflection film is formed of thin multilayer film of titanium oxide or magnesium fluoride.
If a cathode electrode is formed on the driver 12, electric fields from the cathode electrode may cause driver malfunctions or place the cathode electrode and driver circuit in electrical contact. To deal with this problem, the present invention forms at least one layer of organic EL film, and preferably two or more layers, on the driver circuit 12 simultaneously with the formation of organic EL film on the pixel electrode. Since the organic EL film is an insulating material, it isolates the cathode and driver from each other when formed on the driver.
This solves the above problem.
If a short circuit occurs between terminals of one or more transistors 11 or between a transistor 11 and signal line in the pixel, the EL element 15 may become a bright spot which remains illuminated constantly. The bright spot is visually conspicuous and must be turned into a black spot (turned off). The pixel 16 which corresponds to the bright spot is detected and the capacitor 19 is irradiated with laser light to cause a short circuit across the capacitor. As a result, the capacitor 19 can no longer hold electric charges, and thus the transistor 11a can be stopped from passing current. Thus, the pixels irradiated with laser light remain non-illuminated in black display mode.
Incidentally, it is desirable to remove cathode film from those portions which will be irradiated with laser light. This will prevent the terminal electrodes of the capacitor 19 from short-circuiting to the cathode film when the pixels are irradiated with laser light. Thus, where laser repairs will be made, the cathode electrode is patterned with holes in advance.
Flaws in a transistor 11 in the pixel 16 will affect the driver IC 14. For example, if a source-drain (SD) short circuit 562 occurs in the driver transistor 11a in
As shown in
On the other hand, if an SD short circuit occurs in the transistor 11a and if the transistor 11c is on, the Vdd voltage is applied to the source signal line 18 and to the source driver circuit 14. If the power supply voltage of the source driver circuit 14 is not higher than Vdd, voltage resistance may be exceeded, causing the source driver circuit 14 to rupture.
An SD short circuit of the transistor 11a may go beyond a point defect and lead to rupture of the source driver circuit of the panel. Also, the bright spot is conspicuous, which makes the panel defective. Thus, it is necessary to turn the bright spot into a black spot by cutting the wiring which connects between the transistor 11 and EL element 15. For that, the source terminal (S) or drain terminal (D) of the transistor 11a are cut by optical means such as laser light or the channel of the transistor 11a is destroyed.
Incidentally, although it has been stated in the above example that wiring is cut, this is not restrictive in the case of black display. For example, as also can be seen from
Also, since Vdd wiring is actually laid under the pixel electrodes, the display condition of the pixels can be controlled (corrected) by irradiating the Vdd wiring and pixel electrodes with laser light.
For black display of the pixels 16, the EL elements 15 may be degraded. For example, the EL layer 15 is degraded physically or chemically by being irradiated with laser light so that it will not emit light (constant black display). The EL layer 15 can be heated and degraded easily by laser irradiation. The EL layer 15 can be chemically changed easily using an excimer laser.
Incidentally, although the pixel configuration in
A drive method regarding the pixel structure shown in
Parasitic capacitance (not shown) is present in the source signal line 18. The parasitic capacitance is caused by the capacitance at the junction of the source signal line 18 and gate signal line 17, channel capacitance of the transistors 11b and 11c, etc.
The time t required to change the current value of the source signal line 18 is given by t=C·V/I, where C is stray capacitance, V is a voltage of the source signal line, and I is a current flowing through the source signal line. Thus, if the current value can be increased tenfold, the time required to change the current value can be reduced nearly tenfold. This also means that the current value can be changed to a predetermined value even if the parasitic capacitance of the source signal line 18 is increased tenfold. Thus, to apply a predetermined current value during a short horizontal scanning period, it is useful to increase the current value.
For example, a tenfold increase in the output current from the source driver IC 14 results in a tenfold increase in the current programmed into the pixel 16. This results in a tenfold increase in the emission brightness of the EL element 15 as well. Thus, to obtain predetermined brightness, a light emission period is reduced tenfold by reducing the conduction period (ON time) of the transistor 11d in
Thus, in order to charge and discharge the parasitic capacitance of the source signal line 18 sufficiently and program a predetermined current value into the transistor 11a of the pixel 16, it is necessary to output a relatively large current from the source driver circuit 14. However, when such a large current is passed through the source signal line 18, its large current value is programmed into the pixel and a current larger than the predetermined current flows through the EL element 15. For example, if a 10 times larger current is programmed, naturally a 10 times larger current flows through the EL element 15 and the EL element 15 emits 10 times brighter light. To obtain predetermined emission brightness, the time during which the current flows through the EL element 15 can be reduced tenfold. This way, the parasitic capacitance can be charged/discharged sufficiently from the source signal line 18 and the predetermined emission brightness can be obtained.
Incidentally, although it has been stated that a 10 times larger current value is written into the pixel transistor 11a (more precisely, the terminal voltage of the capacitor 19 is set) and that the conduction period of the EL element 15 is reduced to 1/10, this is only exemplary. As another example, ten times larger current may be written into the pixel transistor 11a and the ON time of the EL element 15 may be reduced to ⅕. On the contrary, a 10 times larger current value may be written into the pixel transistor 11a and the conduction period of the EL element 15 may be reduced to ½.
It is also possible to set the ON time to 1/1 (keep the transistor 11d on) for bright image display and set the ON time to 1/10 (turn on the transistor 11d for 1/10 of a frame period) for dark image display. Also, the display may be changed in real time based on image display data.
The present invention is characterized in that the write current into a pixel is set at a value other than a predetermined value and that a current is passed through the EL element 15 intermittently. For ease of explanation, it has been stated herein that an N times larger current is written into the pixel transistor 11 and the conduction period of the EL element 15 is reduced to 1/N. However, this is not restrictive. Needless to say, N1 times larger current may be written into the pixel transistor 11 and the conduction period of the EL element 15 may be reduced to 1/N2 (N1 and N2 are different from each other).
Incidentally, the term “intermittently” does not mean that the panel drive method according to the present invention always uses intermit display. A 1/1 display (other than intermittent display) may be used depending on image display condition. That is, with the drive method according to the present invention, image display occasionally involves intermit display. Intermittent display is a display mode in which at least two horizontal scanning periods (2 Hs) occur in one frame period.
Incidentally, regarding intermittent display, intermittent periods are not necessarily spaced equally. For example, they may appear at random (provided that the display period or non-display period makes up a predetermined value (constant ratio) as a whole). Also, display periods may vary among R, G, and B. For example, R pixels may be driven in non-display mode for ⅓ of one frame period and G and B pixels may be driven in non-display mode for ¼ of one frame period. That is, during an intermittent period, display periods of R, G, and B or non-display period can be adjusted to a predetermined value (constant ratio) in such a way as to obtain an optimum white balance.
To facilitate explanation, it is assumed that “1/N” means reducing IF (one field or one frame) to 1/N. However, it takes time to select one pixel row and to program current values (normally, one horizontal scanning period (1 H)) and error may result depending on scanning conditions. Thus, what has been described above is strictly for ease of explanation and is not meant to be restrictive. Also, N is not limited to integers and may be non-integers such as 3.5. For ease of explanation, it is assumed herein that N represents integers unless otherwise stated.
The EL element 15 may be illuminated for ⅕ of a period by programming the pixel 16 with an N=10 times larger current. The EL element 15 illuminates 10/5=2 times more brightly. On the contrary, it is also possible to program an N=2 times larger current into the pixel 16 and illuminate the EL element 15 for ¼ of the period. The EL element 15 illuminates 2/4=0.5 time more brightly. In short, the present invention achieves display other than constant display (1/1, i.e., non-intermittent drive) by using a current other than an N=1 time current for current programming. Also, in a broad sense, the drive system turns off the current supplied to the EL element 15, at least once during one frame (or one field) period. Also, the drive system at least achieves intermittent display by programming the pixel 16 with a current larger than a predetermined value.
A problem with an organic (inorganic) EL display is that it uses a display method basically different from that of an CRT or other display which presents an image as a set of displayed lines using an electron gun. That is, the EL display holds the current (voltage) written into a pixel for 1F (one field or one frame) period. Thus, a problem is that displaying moving pictures will result in blurred edges.
According to the present invention, current is passed through the EL element 15 only for a period of 1F/N, but current is not passed during the remaining period (1F (N−1)/N). Let us consider a situation in which the drive system is implemented and one point on the screen is observed.
In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed intermittently (intermittent display) in the temporal sense. When moving picture data are displayed intermittently, a good display condition is achieved without edge blur. In short, movie display close to that of a CRT can be achieved. Although the present invention implements intermittent display, the main clock of the circuit does not differ from conventional ones. Thus, there is no increase in the power consumption of the circuit.
In the case of liquid crystal display panels, image data (voltage) to be subjected to light modulation is held in a liquid crystal layer. Therefore, for black insertion display, the data applied to the liquid crystal layer must be rewritten. For that, the operation clock of the source driver IC 14 must be speeded up and the image data and black display data must be applied alternately to the source signal lines 18.
Thus, to achieve black insertion (intermittent display such as black display), it is necessary to speed up the main clock of the circuit. Also, an image memory is needed in order to elongate a time axis.
In the pixel configurations of the EL display panel according to the present invention shown in
The present invention controls the current passed through the EL element 15 by simply turning on and off the switching transistor 11d, the transistor 11e, and the like. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held as it is in the capacitor 19. Thus, when the switching element 11d is turned on the next time, the current passed through the EL element 15 has the same value as the current flowing through the EL element 15 the previous time. Even to achieve black insertion (intermittent display such as black display), the present invention does not need to speed up the main clock of the circuit. Also, it does not need to elongate a time axis, and thus requires no image memory. Besides, the EL element 15 responds quickly, requiring a short time from application of current to light emission. Thus, the present invention is suitable for movie display, and by using intermittent display, it can solve a problem with conventional data-holding display panels (liquid crystal display panels, EL display panels, etc.) in displaying moving pictures.
Furthermore, in the case of a large display apparatus with a large source capacity, source current can be increased more than tenfold. Generally, if the source current value is increased N times, the conduction period of the gate signal line 17b (the transistor 11d) can be set to 1 F/N. This makes it possible to apply the present invention to television sets as well as to display apparatus for monitoring.
The drive method according to the present invention will be described with reference to drawings in more detail below. The parasitic capacitance of the source signal line 18 is generated by the coupling capacitance with adjacent source signal lines 18, buffer output capacitance of the source driver IC (circuit) 14, cross capacitance between the source signal line 18 and gate signal line 17, etc. This parasitic capacitance is normally 10 pF or larger. In the case of voltage driving, since voltage is applied to the source signal line 18 from the source driver IC 14 at low impedance, more or less large parasitic capacitance does not disturb driving.
However, in the case of current driving, especially image display at the black level, the pixel capacitor 19 needs to be programmed with a minute current of 20 nA or less. Thus, if parasitic capacitance larger than a predetermined value is generated, the parasitic capacitance cannot be charged and discharged during the time when one pixel row is programmed (normally within 1 H, but not limited to 1 H because two pixel rows may be programmed simultaneously). If the parasitic capacitance cannot be charged and discharged within a period of 1 H, sufficient current cannot be written into the pixel, resulting in inadequate resolution.
In the pixel configuration in
During a period when the current flows through the EL element 15, the transistors 11c and 11b turn off and the transistor 11d turns on as shown in
Suppose a current I1 is N times the current which should normally flow (a predetermined value), the current flowing through the EL element 15 in
If the transistor 11d is kept on for a period 1/N the period during which it is normally kept on (approximately 1 F) and is kept off during the remaining period (N−1)/N, the average brightness over the 1F equals predetermined brightness. This display condition closely resembles the display condition under which a CRT is scanning a screen with an electronic gun. The difference is that the area where images are displayed is 1/N of the entire screen which illuminates (where the entire screen is taken as 1) (in a CRT, what illuminates is one pixel row—more precisely, one pixel).
According to the present invention, 1F/N of the image display area 53 moves from top to bottom of the screen 50 as shown in
Incidentally, as shown in
In this display condition, image data display and black display (non-illumination) are repeated every 1F. That is, image data is displayed at intervals (intermittently) in the temporal sense. Liquid crystal display panels (EL display panels other than that of the present invention), which hold data in pixels for a period of 1F, cannot keep up with changes in image data during movie display, resulting is blurred moving pictures (edge blur of images). Since the present invention displays images intermittently, it can achieve a good display condition without edge blur of images. In short, movie display close to that of a CRT can be achieved.
A timing chart is illustrated in
As can be seen from
Incidentally, although the above description seemingly concerns white display, the brightness is reduced to 1/10 in black display as well. Thus, even if excessive brightness develops in image display, it is also reduced to 1/10, resulting in a proper image display.
In
The programming current is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10. Of course, since the predetermined value is a data current for use to display images, it is not a fixed value unless in the case of white raster display). The magnitude of the current programmed into each pixel 16 varies with the display condition of natural images. Therefore, the capacitor 19 is programmed so that a 10 times larger current will flow through the transistor 11a. When the pixel row (1) is selected, in the pixel configuration shown in
After 1 H, a gate signal line 17a(2) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row to the source driver circuit 14. The programming current is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10). Therefore, the capacitor 19 is programmed so that 10 times larger current will flow through the transistor 11a.
When the pixel row (2) is selected, in the pixel configuration shown in
After the next 1 H, a gate signal line 17a(3) is selected, a turn-off voltage (Vgh) is applied to the gate signal line 17b(3), and current does not flow through the EL element 15 in the pixel row (3). However, since a turn-off voltage (Vgh) is applied to the gate signal lines 17a(1) and (2) and a turn-on voltage (Vgl) is applied to the gate signal lines 17b(1) and (2) in the pixel rows (1) and (2), the EL element 15 illuminates.
Through the above operation, images are displayed in sync with a synchronization signal of 1 H. However, with the drive method in
However, a 10 times smaller current will cause a shortage of write current due to parasitic capacitance and the like.
To solve this problem, the basic idea of the present invention is to use an N times larger current for programming, insert a black screen 52 (intermittent display), and thereby obtain a predetermined brightness.
Incidentally, the drive method according to the present invention causes a current larger than a predetermined current to flow through the EL element 15, and thereby charges and discharges the parasitic capacitance of the source signal line 18 sufficiently. That is, there is no need to pass an N times larger current through the EL element 15. For example, it is conceivable to form a current path in parallel with the EL element 15 (form a dummy EL element and use a shield film to prevent the dummy EL element from emitting light) and divide the flow of current between the EL element 15 and the dummy EL element.
For example, when a signal current is 0.2 μA, a programming current is set to 2.2 μA and the current of 2.2 μA is passed through the transistor 11a. Then, the signal current of 0.2 μA may be passed through the EL element 15 and 2 μA may be passed through the dummy EL element, for example (see
With the above configuration, by increasing the current passed through the source signal line 18 N times, it is possible to pass an N times larger current through the driver transistor 11a and pass a current sufficiently smaller than the N times larger current through the EL element 15. As shown in
a) shows writing into the display image 50. In
Also, although it has been stated that a programming current is written into the source signal line 18, the present invention is not limited to current programming. The present invention may also use voltage programming (
In
Suppose an N times larger current is used for programming (it is assumed that N=10 as described above), the screen becomes 10 times brighter. Thus, 90% of the display area 50 can be constituted of the non-illuminated area 52. Thus, for example, if the number of horizontal scanning lines in the screen display area is 220 (S=220) in compliance with QCIF, 22 horizontal scanning lines can compose a display area 53 while 220−22=198 horizontal scanning lines can compose a non-display area 52. Generally speaking, if the number of horizontal scanning lines (number of pixel rows) is denoted by S, S/N of the entire area constitutes a display area 53, which is illuminated N times more brightly. Then, the display area 53 is scanned in the vertical direction of the screen. Thus, S(N−1)/N of the entire area is a non-illuminated area 52. The non-illuminated area presents a black display (is non-luminous). Also, the non-luminous area 52 is produced by turning off the transistor 11d. Incidentally, although it has been stated that the display area 53 is illuminated N times more brightly, naturally the display area 53 is adjusted to the value of N by brightness adjustment and gamma adjustment.
In the above example, if a 10 times larger current is used for programming, the screen becomes 10 times brighter and 90% of the display area 50 can be constituted of the non-illuminated area 52. However, this does not necessarily mean that R, G, and B pixels constitute the non-illuminated area 52 in the same proportion. For example, ⅛ of the R pixels, ⅙ of the G pixels, and 1/10 of the B pixels may constitute the non-illuminated area 52 with different colors making up different proportions.
It is possible to allow the non-illuminated area 52 (or illuminated area 53) to be adjusted separately among R, G, and B. For that, it is necessary to provide separate gate signal lines 17b for R, G, and B. However, allowing R, G, and B to be adjusted separately makes it possible to adjust white balance, making it easy to adjust color balance for each gradation (see
As shown in
In
To deal with this problem, the display area 53 can be divided into a plurality of parts as shown in
Needless to say, it is also possible to make the average size of the display area 53 over a few frames (fields) equal to a target size. For example, to make the size of the display area 53 equal to S/10, a possible drive method involves setting the size of the display area 53 to S/10 in the first frame (field), setting the size of the display area 53 to S/20 in the second frame (field), setting the size of the display area 53 to S/20 in the third frame (field), and setting the size of the display area 53 to S/5 in the fourth frame (field) to obtain the desired display area (display brightness) of S/10 when averaged over the four frames (fields). Also, the average display area over a few frames (fields) may be made equal among the RGB colors for a period of L. However, preferably, the few frames (fields) as referred to above do not exceed four frames (fields). Otherwise, flickering may occur depending on displayed images.
Incidentally, one frame or one field as referred to herein may be regarded to be synonymous with an image refresh period of the pixels 16 or the period required for the screen 50 to be scanned from top to bottom (from bottom to top).
Also, the average display area over a few frames (fields) may be made different among the RGB colors for a period of L to achieve an appropriate white balance. This drive method is effective especially when emission efficiency varies among R, G, and B. Also, the number K of divisions may be varied among R, G, and B. G, in particular, is visually conspicuous, and thus it is useful to increase the number of divisions of G over R and B.
Incidentally, it has been stated in the above example for ease of explanation that the display area 53 is divided.
However, dividing an area is tantamount to dividing a period (time). Thus, in
Dividing the display area 53 reduces flickering of the screen. Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. However, the more finely the display area 53 is divided, the poorer the movie display performance becomes. Also, the frame rate of image display can be lowered, resulting in reduced power consumption. For example, if the non-display area 52 is undivided, flickering occurs when the frame rate falls below 45 Hz. However, if the non-display area 52 is divided into six or more parts, flickering does not occur until the frame rate falls below 20 Hz.
Preferably, the number of divisions is variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K may be changed in response. Also, the user may be allowed to adjust brightness. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.
Also, the number of divisions may be changed according to condition of image data. If the image data is moving pictures, by leaving the non-illuminated area 52 undivided, it is possible to avoid blurred moving pictures. In the case of moving pictures, since images change constantly, flickering does not occur even if the frame rate is lowered. If the image data is still pictures, by dividing the non-illuminated area 52 into multiple parts, it is possible to avoid flickering even at a low frame rate. Thus, by judging in real time whether the image data is moving pictures or still pictures and controlling the number of divisions of the non-illuminated area 52 based on the result of judgment, it is possible to achieve high quality display without blurred moving pictures at low power consumption.
If the timing of a change from a state in which a turn-on voltage (Vgl) is applied to the gate signal line 17a to a state in which a turn-off voltage (Vgh) is applied coincides with the timing of a change from a state in which a turn-off voltage (Vgh) is applied to the gate signal line 17b to a state in which a turn-on voltage (Vgl) is applied, variations tend to occur in retained images. This is believed to be due to discharge or leakage of the voltage programmed in the capacitor 19, which in turn is caused by difference in on/off timing of the transistors 11b and 11d depending on their characteristics.
To deal with this problem, preferably a write pixel row 51 is sandwiched by non-display areas 52 as illustrated in
In
By continuing to apply a turn-off voltage to the gate signal line 17b while a turn-on voltage is applied to the gate signal line 17a and applying a turn-on voltage to the gate signal line 17b when a turn-off voltage is applied to the gate signal line 17a in place of the turn-on voltage and the transistors 11b and 11c of the pixel 16 in
In
By continuing to apply a turn-off voltage to the gate signal line 17b while a turn-on voltage is applied to the gate signal line 17a and applying a turn-on voltage to the gate signal line 17b when a turn-off voltage is applied to the gate signal line 17a in place of the turn-on voltage and the transistors 11b and 11c of the pixel 16 in
In
Furthermore, a turn-off voltage is applied to the gate signal line 17b for 1 H after a turn-on voltage (Vgl) is applied to the gate signal line 17a.
By continuing to apply a turn-off voltage to the gate signal line 17b while a turn-on voltage is applied to the gate signal line 17a and applying a turn-on voltage to the gate signal line 17b when a turn-off voltage is applied to the gate signal line 17a in place of the turn-on voltage and the transistors 11b and 11c of the pixel 16 in
Incidentally, although the above example has been described by citing the pixel configuration in
Also, although it has been stated with reference to
By varying the value of L, the brightness of the display screen 50 can be changed digitally. For example, there is a 50% change of brightness (contrast) between L=2 and L=3. By changing the period of L sequentially, it is possible to adjust the brightness of the screen 50 linearly in proportion to the period of L. Even if the brightness is adjusted, the number of gradations is maintained. Incidentally, the period of L is not limited to integral multiples of one horizontal scanning period (1 H). Needless to say, 5/2 Hs or a period shorter than 1 H such as ½ H or ⅛ H may be used for operations and control.
In the example described above, the display screen 50 is turned on and off (illuminated and non-illuminated) as the current delivered to the EL element 15 is switched on and off. That is, approximately equal current is passed through the transistor 11a multiple times using electric charges held in the capacitor 19. The present invention is not limited to this. For example, the display screen 50 may be turned on and off (illuminated and non-illuminated) by charging and discharging the capacitor 19 (See embodiments shown in
Since black display on EL display apparatus corresponds to complete non-illumination, contrast does not lower unlike in the case of intermittent display on liquid crystal display panels. Also, with the configurations in
The drive method described above is not limited to a current-driven type and can be applied to a voltage-driven type as well. That is, in a configuration in which the current passed through the EL element 15 is stored in each pixel, intermittent driving is implemented by switching on and off the current path between the driver transistor 11 and EL element 15. Needless to say, intermittent driving can be implemented, for example, through control of the transistor 11d in
It is important to maintain the terminal voltage of the capacitor 19 programmed with current or voltage. This is because any change (charge/discharge) the terminal voltage of the capacitor 19 during one field (frame) period causes changes in the screen brightness, resulting in flickering at lower frame rates. The current passed through the EL element 15 by the transistor 11a must be higher than 65%. More specifically, if the initial current written into the pixel 16 and passed through the EL element 15 is taken as 100%, the current passed through the EL element 15 just before it is written into the pixel 16 in the next frame (field) must not fall below 65%. The capacitance of the capacitor 19 and turn-off characteristics of the voltage-holding transistor 11b are determined in such a way as to satisfy the above conditions.
With the pixel configuration shown in
Also, since the operation clock of the gate driver circuit 12 is significantly slower than the operation clock of the source driver circuit 14, there is no need to upgrade the main clock of the circuit (the same clock can be applied to either of the cases where intermittent operation is done or not.) Besides, the value of N or K can be changed easily. This can be achieved simply through on/off control of the transistor 11b and the like.
Incidentally, the image display direction (image writing direction) may be from top to bottom of the screen in the first field (frame), and from bottom to top of the screen in the second field (frame). That is, an upward direction and downward direction may be repeated alternately. By switching the scanning direction in this way, it is possible to reduce flickering even at a low frame rate.
Alternatively, it is possible to use a downward direction in the first field (frame), turn the entire screen into black display (non-display) once, and use an upward direction in the second field (frame). It is also possible to turn the entire screen into black display (non-display) once. It is also possible to turn the entire screen into black display (non-display) once, and then rewrite images from top to bottom of the screen. That is, the entire screen is turned into black display after rewriting and displaying images. Turning the entire screen into black display in this way improves movie display performance.
In the description of the drive method according to the present invention, it is stated for ease of explanation that the writing direction on the screen is from top to bottom or from bottom to top. However, the present invention is not limited to this. It is also possible to fix the writing direction on the screen to a top-to-bottom direction or bottom-to-top direction and move the non-display area 52 from top to bottom in the first field (frame), and from bottom to top in the second field (frame). Alternatively, it is possible to divide a frame into three fields and assign the first field to R, the second field to G, and the third field to B so that three fields compose a single frame. It is also possible to display R, G, and B in turns by switching among them every horizontal scanning period (1 H) (see
The non-display area 52 need not be totally non-illuminated. Weak light emission or dim image display will not be a problem in practical use. That is, non-display area (non-illuminated area) 52 should be regarded to be an area which has a lower display brightness than the image display area 53. It has been shown analytically that if the brightness of the non-display area 52 is set at or below ⅓ the brightness of the display area 53, proper image display can be achieved without lowering movie display performance. In the pixel configuration in
If the brightness of the display area 53 is kept at a predetermined value, the larger the display area 53, the brighter the display screen 50. For example, when the brightness of the image display area 53 is 100 (nt), if the percentage of the display screen 50 accounted for by the display area 53 changes from 10% to 20%, the brightness of the screen is doubled. Thus, by varying the proportion of the display area 53 in the entire screen 50, it is possible to vary the display brightness of the screen. The present invention provides a system which controls image display by controlling the size of the display area 53 with respect to the display 50.
The size of the display area 53 can be specified freely by controlling data pulses (ST2) sent to the shift register circuit 61 (See
a) shows a brightness adjustment scheme used when the display area 53 is continuous as in
Also, in the process of change from
In brightness adjustment of a conventional screen, low brightness of the screen 50 results in poor gradation performance. That is, even if 64 gradations can be displayed in a high-brightness display, less than half the gradations can be displayed in a low-brightness display. In contrast, the drive method according to the present invention does not depend on the display brightness of the screen and can display up to 64 gradations, which is the highest.
b) shows a brightness adjustment scheme used when the display areas 53 are scattered as in
To eliminate flickering at an even lower frame rate, the display areas 53 can be scattered more finely as shown in
Although non-display areas 52 are formed at equal intervals in
Thus, it is possible to reduce the current flowing through the EL element 15. For ease of explanation, it is assumed, for example that N=10 and that the number M of pixel rows selected simultaneously is 5 (the current passed through the source signal line 18 is increased tenfold. Since five pixel rows are selected simultaneously, 1/5 of the programming current flows through each pixel).
According to the invention described with reference to
Incidentally, although in the description of the drive method according to the present invention, it is stated for ease of explanation that a current N times larger than a predetermined current is passed through the source signal line, this is not restrictive. The present invention is characterized in that a signal (current or voltage) outputted from the source driver circuit 14 is divided into multiple parts, which are applied to pixel rows selected simultaneously (it is all right if they are selected not exactly at the same time). If the driver transistors 11a in the pixels 16 selected simultaneously and connected to the same source signal line 18 have uniform characteristics, the current outputted from the source driver circuit 14 and divided by the number M of pixel rows selected simultaneously is programmed into the pixels 16.
That is, current is passed through the EL elements 15 only for a period equal to M/N of one frame (one field), but current is not passed during the remaining period (1 F (N−1)M/N). In this display condition, image data display and black display (non-illumination) are repeated every 1 F. That is, image data is displayed intermittently in the temporal sense (intermittent display). Thus, a good display condition is achieved without edge blur. Also, since the source signal line 18 is driven by an N times larger current, it is not affected by parasitic capacitance. Thus, this method can accommodate high-resolution display panels.
Incidentally, it has been stated in the above example for ease of explanation that M pixel rows are selected simultaneously and that an N times larger current is outputted from the source driver circuit 14. However, the present invention is not limited to this. It is also possible to select M pixel rows simultaneously and output the original current as it is from the source driver circuit 14. In that case, the present invention is implemented with the brightness of the display screen 50 reduced. Of course, the brightness of the screen 50 can be increased if 2 times, 2.5 times, or 5.25 times larger current is outputted from the source driver circuit 14.
Although it has been stated in the above example for ease of explanation that M pixel rows are selected simultaneously and that each pixel 16 is illuminated for a period of M/N, the present invention is not limited to this. It is also possible to select M pixel rows simultaneously and output M/10 times, M/5 times, or M/2.5 times larger current from the source driver circuit 14. That is, the display period can be set freely independent of N. Increasing the display period increases the brightness of the screen 50 and decreasing the display period decreases the brightness of the screen 50. That is, the present invention which selects M pixel rows simultaneously can also control or adjust the brightness of the screen 50 easily by controlling the display period.
In
The programming current flowing through the source signal line 18 is N times larger than a predetermined value (for ease of explanation, it is assumed that N=10. Of course, since the predetermined value is a data current for use to display images, it is not a fixed value unless in the case of white raster display or the like. The current value to be programmed in each pixel 16 by the image data varies. It is also assumed that five pixel rows are selected simultaneously (M=5). Therefore, ideally the capacitor 19 of one pixel is programmed so that a twice (N/M=10/5=2) larger current will flow through the transistor 11a.
When the write pixel row is the (1)-th pixel row, the gate signal lines 17a of pixel rows (1), (2), (3), (4), and (5) are selected as shown in
Incidentally, it has been stated for ease of explanation that when a selection voltage is applied to the gate signal lines 17a of pixel rows (pixel rows (1), (2), (3), (4), and (5) in the above description), a turn-off voltage is applied to the gate signal lines 17b and the transistors 11d of the pixel rows (pixel rows (1), (2), (3), (4), and (5)) are turned off. However, as illustrated in
According to the present invention, in the pixel configurations in
According to the present invention, it is important that one or all of the pixel rows selected simultaneously (with a turn-on voltage applied to the gate signal lines 17a) to write image data are put into non-display mode. This is because putting one or more pixel rows into display mode lowers the resolution of displayed images.
Ideally, the transistors 11a in the five pixels deliver a current of Iw×2 each to the source signal line 18 (i.e., a current of I×2×N=Iw×2×5=Iw×10 flows through the source signal line 18. Thus, if a predetermined voltage Iw flows when the N-fold pulse driving according to the present invention is not used, a current 10 times larger than Iw flows through the source signal line 18).
Through the above operation (drive method), the capacitor 19 of each pixel row (1), (2), (3), (4) and (5) is programmed with a twice larger programming current. For ease of understanding, it is assumed here that the transistors 11a have equal characteristics (Vt and S value).
Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 10/5=2 times larger current flows through the transistor 11a per pixel. The total programming current of the transistors 11a of the five pixels 16 flows through the source signal line 18.
For example, if a current written into the write pixel row 51a is Iw, a current equal to Iw×10 is passed through the source signal line 18. The write pixel rows 51b (the pixel rows (2), (3), (4), and (5) when the pixel row (1) is being programmed with current) into which image data is written later than the write pixel row (1) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18. However, there is no problem because regular image data is written into the write pixel rows 51b later (see
Thus, the four pixel rows 51b provide the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel rows 51b selected to increase current are put into non-display mode 52 (see
After 1 H, the gate signal line 17a(1) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b in
After the next 1 H, the gate signal line 17a(2) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b of the pixel row (2) (see the 7th H in
With the drive method in
As is the case with
As described above, dividing the display area 53 reduces flickering of the screen.
Thus, a flicker-free good image display can be achieved. Incidentally, the display area 53 may be divided more finely. The more finely the display area 53 is divided, the less flickering occurs. Since the EL element 15 is highly responsive, even if it is turned on and off at intervals shorter than 5 μsec, there is no lowering of the display brightness.
With the drive method according to the present invention, the EL element 15 can be turned on and off by turning on and off a signal applied to the gate signal line 17b. Thus, a clock frequency can be controlled using a low frequency on the order of KHz. Also, it does not need an image memory or the like in order to insert a black screen (insert a non-display area 52). Thus, the drive circuit or method according to the present invention can be implemented at low costs.
This is because that part of a semiconductor film which is annealed simultaneously has uniform characteristics. That is, the semiconductor film is created uniformly within an irradiation range of laser stripes and the Vt, mobility, and S value of the transistors which use the semiconductor film are almost uniform. Thus, if a striped laser shot is moved in parallel with the source signal line 18 (see
As described above, if the direction of a laser shot is made to coincide approximately with the direction of the source signal line 18, the characteristics of the pixel transistors 11a arranged vertically become almost uniform. This makes it possible to program pixels accurately with a target voltage, and thus achieve proper image display (even if the characteristics of the pixel transistors 11a arranged horizontally are not uniform). The above operation is performed in sync with 1 H (one horizontal scanning period) by shifting selected pixel rows one by one or by shifting two or more selected pixel rows at once.
Incidentally, according to the present invention, the direction of the laser shot does not always need to be parallel with the direction of the source signal line 18. This is because even if the laser shot is directed at angles to the source signal line 18, pixel transistors 11a placed along one source signal line 18 can be made to take on almost equal characteristics. Thus, directing a laser shot in parallel with the source signal line 18 means bringing a pixel vertically adjacent to an arbitrary pixel along the source signal line 18 into a laser irradiation range. Besides, a source signal line 18 generally constitutes wiring which transmits programming current or voltage used as a video signal.
Incidentally, in the examples of the present invention a write pixel row is shifted every 1 H, but this is not restrictive. Pixel rows may be shifted every 2 Hs. Also, more than two pixel rows may be shifted at a time. Also, pixel rows may be shifted at desired time intervals. The shifting interval may be varied according to locations on the screen. For example, the shifting interval may be decreased in the middle of the screen, and increased at the top and bottom of the screen. Also, the shifting interval may be varied on a frame-by-frame basis.
Also, it is not strictly necessary to select consecutive pixel rows. For example, every second pixel row may be selected. Specifically, a possible drive method involves selecting the first and third pixel rows in the first horizontal scanning period, the second and fourth pixel rows in the second horizontal scanning period, the third and fifth pixel rows in the third horizontal scanning period, and the fourth and sixth pixel rows in the fourth horizontal scanning period.
Of course, a drive method which involves selecting the first, third, and fifth pixel rows in the first horizontal scanning period also belongs to the technical category of the present invention. Also, one in every few pixel rows may be selected.
Incidentally, the combination of the direction of a laser shot and selection of multiple pixel rows is not limited to the pixel configurations in
As described above, the drive method according to the present invention in
Thus, in the 1st and 2nd Hs, the switching transistors 11d in the pixel rows (1) and (2) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52. Incidentally, in
Ideally, the transistors 11a in the two pixel rows deliver a current of Iw×5 each to the source signal line 18 (when N=10. Since K=2, a current of Iw×K×5=Iw×10 flows through the source signal line 18). Then, a 5 times larger current is programmed to the capacitor 19 of each pixel 16 and held.
Since two pixel rows are selected simultaneously (K=2), two driver transistors 11a operate. That is, 10/2=5 times larger current flows through the transistor 11a per pixel. The total programming current of the two transistors 11a flows through the source signal line 18.
For example, if the current written into the write pixel row 51a is Id, a current of Iw×10 is passed through the source signal line 18. There is no problem because regular image data is written into the write pixel row 51b later. The pixel row 51b provides the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel row 51b selected to increase current are in non-display mode 52.
After the next 1 H, the gate signal line 17a(1) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(3) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (3) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (1).
After the next 1 H, the gate signal line 17a(2) becomes deselected and a turn-on voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a(4) is selected (Vgl voltage) and a programming current flows through the source signal line 18 in the direction from the transistor 11a in the selected pixel row (4) to the source driver circuit 14. Through this operation, regular image data is held in the pixel row (2). The entire screen is redrawn as it is scanned by shifting pixel rows one by one through the above operations (of course, two or more pixel rows may be shifted simultaneously. For example, in the case of pseudo-interlaced driving, two pixel rows will be shifted at a time. Also, from the viewpoint of image display, the same image may be written into two or more pixel rows).
As in the case of
As shown in
To deal with this problem, the present invention forms (places) a dummy pixel row 281 at the bottom of the screen 50, as shown in
Although it has been stated with reference to
Two pixel rows are selected simultaneously in the example described above. The present invention is not limited to this. For example, five pixel rows may be selected simultaneously (see
In view of the above, the required number of dummy pixel rows 281 equals the number M of pixel rows selected simultaneously minus 1. For example, if five pixel rows are selected simultaneously, required number of dummy pixel rows is 5−1=4. If ten pixel rows are selected simultaneously, required number of dummy pixel rows is 10−1=9.
a) shows formation locations of dummy pixel rows 281 for driving with simultaneous selection of two pixel rows (M=2).
In the above example of a drive method, different image data is held for each pixel row. Needless to say, the required number of pixel rows is doubled if the same image data is held in two pixel rows. That is, if two pixel rows are selected at a time to scan, twice as many dummy pixel rows are required. Thus, the required number of dummy pixel rows is given by the number M of pixel rows selected simultaneously minus 1, all multiplied by the number of pixel rows into which the same image data is written.
In the above example of a drive method, adjacent pixel rows are selected simultaneously. However, the drive system according to the present invention is not limited to this.
In a drive method which involves selecting two pixel rows simultaneously, the dummy pixel row 281 formed at the bottom must always be selected. That is, the transistors 11b and 11c of the dummy pixel row 281 which select the dummy pixel row 281 always remain on.
a) shows a state in which the top of the screen 50 is scanned (programmed with current).
With the drive method in
Incidentally, in
The magnification of the current delivered by the dummy pixel row 281 to the source signal line 18 can be set by specifying the channel width W and channel length L of the driver transistor 11a of the dummy pixel row 281 in design. Increasing W increases the drive current passed through the source signal line 18 and decreasing W decreases the drive current passed through the source signal line 18. Thus, if W/L of the driver transistor 11a of the dummy pixel row 281 is made larger than W/L of the driver transistor 11a of the pixel 16 in the display area 50, the drive current of the dummy pixel row 281 can be made larger than the drive current of the display area 50. Needless to say, it is preferable to make the drive current of the dummy pixel row 281 larger.
Incidentally, although with the drive method in
With the pixel configuration in
In the above example, scanning begins with the same pixel row number in every field or frame. NTSC and the like supports interlaced driving. In interlaced driving, one frame consists of two fields and odd-numbered pixel rows are scanned in the first field and even-numbered pixel rows are scanned in the second field.
In an example in
In the first field, two pixel rows are selected simultaneously beginning with the first pixel row and subsequent pixel rows are selected by shifting position. This process is similar to the one described with reference to
In the second field, two pixel rows are selected simultaneously beginning with the second pixel row and subsequent pixel rows are selected by shifting position. The point is that the scanning begins with the second pixel row rather than the first pixel row. With interlaced driving, odd-numbered pixel rows are scanned in the first field and even-numbered pixel rows are scanned in the second field. That is, the start position of scanning differs between the first field and second field. Needless to say, a dummy pixel row 281 such as the one described with reference to
The drive method according to the present invention is not limited to simultaneous selection of multiple pixel rows. For example, the speed of writing into pixel rows may be doubled. That is, pixel rows are selected one by one and images on the selected pixel rows are rewritten (see
In the second field, the same image is written into the second and third pixel rows. Similarly, the same image is written into the fourth and fifth pixel rows and the same image is written into the sixth and seventh pixel rows. The above operation is repeated until the 478th and 479th pixel rows or the 480th and 481st pixel rows to finish writing images into the second field.
The simultaneous selection of multiple pixel rows is not limited to simultaneous selection of two pixel rows. Needless to say, for example, odd-numbered pixel rows (1, 3, 5, 7, 9, . . . , 479) may be scanned in the first field and even-numbered pixel rows (2, 4, 6, 8, 10, . . . , 480) may be scanned in the second field. The even-numbered pixel rows in the first field may be either non-illuminated or scanned in sequence as non-display areas 52, as illustrated in
In
Now, interlaced driving according to the present invention will be described below in more detail.
Thus, through operation (control) of the gate driver circuit 12a1, image data in the odd-numbered pixel rows are rewritten in sequence. In the odd-numbered pixel rows, illumination and non-illumination of the EL elements are controlled through operation (control) of the gate driver circuit 12b1. Also, through operation (control) of the gate driver circuit 12a2, image data in the even-numbered pixel rows are rewritten in sequence. In the even-numbered pixel rows, illumination and non-illumination of the EL elements are controlled through operation (control) of the gate driver circuit 12b2.
a) shows operating state in the first field of the display panel.
In this way, interlaced driving can be implemented easily on an EL display panel. Also, N-fold pulse driving eliminates shortages of write current and blurred moving pictures. Besides, current (voltage) programming and illumination of EL elements 15 can be controlled easily and circuits can be implemented easily.
Incidentally, the drive method according to the present invention is not limited to those shown in
The drive method in
Of course, this is not restrictive.
In the above example, pixel rows are programmed with current (voltage) one by one. However, the drive method according to the present invention is not limited to this. Needless to say, two pixel rows (a plurality of pixel rows) may be programmed with current (voltage) simultaneously as shown in
In the drive method which selects two or more pixel rows at a time, the larger the number of pixel rows selected simultaneously, the more difficult it becomes to absorb variations in the characteristics of the transistors 11a. However, the current programmed into one pixel increases with decreases in the number of pixel rows selected, resulting in a large current flowing through the EL element 15, which in turn makes the EL element 15 prone to degradation.
Referring to
Naturally, since the same image data is written into the five write pixel rows, the transistors 11d in the five write pixel rows are turned off in order not to display the image. Thus, the display condition is as shown in
In the next ½ H period, one pixel is selected for current (voltage) programming. The condition is as shown in
Specifically, in
Incidentally, scanning of the non-illuminated area 52 from top to bottom of the screen and scanning of the write pixel rows 51a from top to bottom of the screen are performed in the same manner as in examples in
First, the ISEL signal will be described. The driver circuit 14 which performs operations shown in
When the ISEL signal is low, the current output circuit A which outputs 25 times larger current is selected and current from the source signal line 18 is absorbed by the source driver IC 14 (more precisely, the current is absorbed by the current output circuit A formed in the source driver IC 14). The magnification (such as ×25 or ×5) of the current from the current output circuits can be adjusted easily using a plurality of resisters and an analog switch.
As shown in
Ideally, the transistors 11a in the five pixels deliver a current of Iw×2 each to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a five times larger current. For ease of understanding, it is assumed here that the transistors have equal characteristics (Vt and S value).
Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18. For example, if the current written into the write pixel row 51a by a conventional drive method is Iw, a current of Iw×25 is passed through the source signal line 18. The write pixel rows 51b into which image data is written later than the write pixel row (1) are auxiliary pixel rows used to increase the amount of current delivered to the source signal line 18. However, there is no problem because regular image data is written into the write pixel rows 51b later.
Thus, the pixel rows 51b provide the same display as the pixel row 51a during a period of 1 H. Consequently, at least the write pixel row 51a and the pixel rows 51b selected to increase current are in non-display mode 52.
In the next ½ H period (½ of the horizontal scanning period), only the write pixel row 51a is selected. That is, only the (1)-th pixel row is selected. As can be seen from
Thus, each transistor 11a in the pixel row (1) deliver a current of Iw×5 to the source signal line 18. Then, the capacitor 19 in pixel row (1) is programmed with a 5 times larger current.
In the next horizontal scanning period, the write pixel row shifts by one. That is, the pixel row (2) becomes the current write pixel row. During the first ½ H period, when the write pixel row is the (2)-th pixel row, the gate signal lines 17a(2), (3), (4), and (5) and (6) are selected. That is, the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Besides, since ISEL is low, the current output circuit A which outputs 25 times larger current is selected and connected to the source signal line 18. Also, a turn-off voltage (Vgh) is applied to the gate signal line 17b. Thus, the switching transistors 11d in the pixel rows (2), (3), (4), (5), and (6) are off and current does not flow through the EL elements 15 in the corresponding pixel rows. That is, the EL elements 15 are in non-illumination mode 52. On the other hand, since Vgl voltage is applied to the gate signal line 17b(1) of the pixel row (1), the transistor 11d is on and the EL element 15 in the pixel row (1) illuminates.
Since five pixel rows are selected simultaneously (K=5), five driver transistors 11a operate. That is, 25/5=5 times larger current flows through the transistor 11a per pixel. The total programming current of the five transistors 11a flows through the source signal line 18.
In the next ½ H period (½ of the horizontal scanning period), only the write pixel row 51a is selected. That is, only the (2)-th pixel row is selected. As can be seen from
Thus, each transistor 11a in the pixel row (1) deliver a current of Iw×5 to the source signal line 18. Then, the capacitor 19 in pixel row (1) is programmed with a 5 times larger current. The entire screen is drawn as the above operations are performed in sequence.
The drive method described with reference to
Another scheme is also available. It selects G pixel rows (G is 2 or larger) in the first period and does programming in such a way that the total current in all the pixel rows will be an N times larger current. In the second period, this scheme selects B pixel rows (B is smaller than G, but not smaller than 1) and does programming in such a way that the total current in the selected pixel rows (the current in the one pixel row if one pixel row is selected) will be an N times larger current. For example, in
Incidentally, although a plurality of pixel rows are selected simultaneously in a period of ½ H and a single pixel row is selected in a period of ½ H in
In
In
In the example described above, pixel rows are selected one by one and programmed with current, or two or more pixel rows are selected at a time and programmed with current. However, the present invention is not limited to this. It is also possible to use a combination of the two methods according to image data: the method of selecting pixel rows one by one and programming them with current and the method of selecting two or more pixel rows at a time and programming them with current.
Incidentally, for ease of understanding, it is assumed that the source driver IC 14 in
a
1) shows a typical drive method according to the present invention. If input video signals are non-interlaced (progressive) signals, the drive system in
A problem is that the drive system which selects two pixel rows at a time as shown in
The proportions of the non-display area 52 and display area 53 can be varied easily by controlling the start pulse supplied to the gate driver circuit 12. That is, the drive mode in
Incidentally,
The N-fold pulse driving method according to the present invention mentioned above uses the same waveform for the gate signal lines 17b of different pixel rows and applies current by shifting the pixel rows at 1 H intervals. The use of such scanning makes it possible to shift illuminating pixel rows in sequence with the illumination duration of the EL elements 15 fixed to 1F/N. It is easy to shift pixel rows in this way while using the same waveform for the gate signal lines 17b of the pixel rows. It can be done by simply controlling data ST1 and ST2 applied to the shift register circuits 61a and 61b in
Incidentally, the EL elements 15 must be turned on and off at intervals of 0.5 msec or longer. Short intervals will lead to insufficient black display due to persistence of vision, resulting in blurred images and making it look as if the resolution has lowered. This also represents a display state of a data holding display. However, increasing the on/off intervals to 100 msec will cause flickering. Thus, the on/off intervals of the EL elements must be not shorter than 0.5 msec and not longer than 100 msec. More preferably, the on/off intervals should be from 2 msec to 30 msec (both inclusive). Even more preferably, the on/off intervals should be from 3 msec to 20 msec (both inclusive).
As also described above, an undivided black screen 152 achieves good movie display, but makes flickering of the screen more noticeable. Thus, it is desirable to divide the black insert into multiple parts. However, too many divisions will cause moving pictures to blur. The number of divisions should be from 1 to 8 (both inclusive). More preferably, it should be from 1 to 5 (both inclusive).
Incidentally, it is preferable that the number of divisions of a black screen can be varied between still pictures and moving pictures. When N=4, 75% is occupied by a black screen (non-display area 52) and 25% is occupied by image display (display area 53). When the number of divisions is 1, a strip of black display (non-display area 52) which makes up 75% is scanned vertically. When the number of divisions is 3, three blocks are scanned, where each block consists of a black screen which makes up 25% and a display screen which makes up 25/3 percent. The number of divisions is increased for still pictures and decreased for moving pictures. The switching can be done either automatically according to input images (detection of moving pictures) or manually by the user. Alternatively, the switching can be done according to input contents such as video on the display apparatus.
For example, on cell phones, which use still pictures for wallpapers and input screens, the number of divisions should be 10 or more (in extreme cases, the display may be turned on and off every 1 H). When displaying moving pictures in NTSC format, the number of divisions should be from 1 to 5 (both inclusive). Preferably, the number of divisions can be switched in three or more steps; for example, 0, 2, 4, 8, 16 divisions, and so on. Preferably, the number of divisions can be varied from 0 to half the number of displayed scanning lines. Preferably, the number of divisions can be changed in real time according to contents of image data. It is also possible to allow the user to change the number of divisions with a changeover switch or the like. It is also possible to allow the number of divisions to be changed in real time according to the brightness of extraneous light.
Preferably, the ratio of the black screen to the entire display screen should be from 0.2 to 0.9 (from 1.2 to 9 in terms of N) both inclusive when the area of the entire screen is taken as 1. More preferably, the ratio should be from 0.25 to 0.6 (from 1.25 to 6 in terms of N) both inclusive. If the ratio is 0.20 or less, movie display is not improved much. When the ratio is 0.9 or more, the display part becomes bright and its vertical movements become liable to be recognized visually.
Also, preferably, the number of frames per second is from 10 to 100 (10 Hz to 100 Hz) both inclusive. More preferably, it is from 12 to 65 (12 Hz to 65 Hz) both inclusive. When the number of frames is small, flickering of the screen becomes conspicuous while too large a number of frames makes writing from the source driver circuit 14 and the like difficult, resulting in deterioration of resolution.
In any case, the present invention allows the brightness of images to be varied by controlling the gate signal lines 17. However, needless to say, the brightness of images may be varied by varying the current (voltage) applied to the source signal lines 18. It goes without saying that the two methods described above (
Needless to say, the above items also apply to the pixel configurations for current programming in
Also, the gate signal line 17b may be set to Vgl for a period of 1F/N anytime during the period of 1F (not limited to 1F. Any unit time will do). This is because a predetermined brightness is obtained by turning off the EL element 15 for a predetermined period out of a unit time. However, it is preferable to set the gate signal line 17b to Vgl and illuminate the EL element 15 immediately after the current programming period (1 H). This will reduce the effect of retention characteristics of the capacitor 19 in
Also, preferably the number of screen divisions is configured to be variable. For example, when the user presses a brightness adjustment switch or turns a brightness adjustment knob, the value of K, which is the number of divisions, may be changed in response. Alternatively, the value of K may be changed manually or automatically depending on images or data to be displayed.
In this way, the mechanism for changing the value of K (the number of divisions of the image display part 53) can be implemented easily. This can be achieved by simply making the time to change ST (when to set ST low during 1F) adjustable or variable.
Incidentally, although it has been stated with reference to
The above examples involve placing (forming) the transistor 11d serving as a switching element between the EL element 15 and driver transistor 11a and turning on and off the screen 50 by controlling the transistor 11d. This drive method eliminates shortages of write current in black display condition during current programming and thereby achieves proper resolution or black display. That is, in current programming, it is important to achieve proper black display. The drive method described next achieves proper black display by resetting the driver transistor 11a. This example will be described below with reference to
The pixel configuration in
To implement reset driving using the pixel configuration shown in
Preferably, the drive voltage should be varied between the gate signal line WR and the gate signal line EL. The amplitude value (difference between turn-on voltage and turn-off voltage) of the gate signal line WR should be smaller than the amplitude value of the gate signal line EL. Basically, too large an amplitude value of the gate signal line will increase penetration voltage between the gate signal line and pixel, resulting in an insufficient black level. The amplitude of the gate signal line WR can be controlled by controlling the time when the potential of the source signal line 18 is not applied (or is applied (during selection)) to the pixel 16. Since changes in the potential of the source signal line 18 are small, the amplitude value of the gate signal line WR can be made small. On the other hand, the gate signal line EL is used for on/off control of EL. Thus, its amplitude value becomes large. For this, output voltage is varied between the shift register circuits 61a and 61b. If the pixel is constructed of P-channel transistors, approximately equal Vgh (turn-off voltage) is used for the shift register circuits 61a and 61b while Vgl (turn-on voltage) of the shift register circuit 61a is made lower than Vgl (turn-on voltage) of the shift register circuit 61b.
Reset driving will be described below with reference to
The reset mode (in which no current flows) of the transistor 11a is equivalent to a state in which an offset voltage is held in voltage offset canceling mode described with reference to
Incidentally, before the operation in
As the operation time of
A state shown in
If the programming current Iw is 0 A, the transistor 11a is held in the state in
After the programming in
The drive system (reset driving) described with reference to
In image display mode (if instantaneous changes can be observed), the pixel row to be programmed with current is reset (black display mode) and is programmed with current after 1 H (also in black display mode because the transistor 11d is off). Next, current is supplied to the EL element 15 and the pixel row illuminates at a predetermined brightness (at the programmed current). That is, the pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by. Incidentally, although it has been stated that current programming is performed 1 H after a reset, this period may be approximately 5 Hs or shorter. This is because it takes a relatively long time for the reset in
Also, the number of pixel rows which are reset at a time is not limited to one, and two or more pixel rows may be reset at a time. It is also possible to reset and scan two or more pixel rows at a time by overlapping some of them. For example, if four pixel rows are reset at a time, pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (1 unit), pixel rows (3), (4), (5), and (6) are reset in the second horizontal scanning period, pixel rows (5), (6), (7), and (8) are reset in the third horizontal scanning period, and pixel rows (7), (8), (9), and (10) are reset in the fourth horizontal scanning period. Incidentally the drive operations in
Needless to say, the drive operation in (b) and (c) of
It has been stated that
First, description will be given of why variations occur in image data programmed with current in the pixel configuration in
If the transistor 11c turns off with the transistor 11b on, the state illustrated in
To solve this problem, a turn-off voltage is applied to the gate signal line 17a after a turn-on voltage (the transistor 11b turns off by the application of the turn-off voltage), and then a turn-off voltage is applied to the gate signal line 17c after a turn-on voltage (the transistor 11c turns off by the application of the turn-off voltage). That is, after programming the pixel 16 with current (during the programming, a turn-on voltage is applied to the gate signal lines 17a and 17c, keeping the transistors 11b and 11c on), a turn-off voltage is applied to the gate signal line 17a, and after a predetermined period of time, a turn-off voltage is applied to the gate signal line 17c. Through the above operation, appropriate current programming can be achieved, eliminating the state in
Incidentally, the predetermined period of time here is between 0.1 and 10 μsec (both inclusive). Alternatively, it is between 1/1000 and 1/10 of 1 H (both inclusive). If this period is too short, it is not possible to achieve proper current (voltage) programming, resulting in variations in the holding voltage of the capacitor 19. If it is too long, the duration of current (voltage) programming is reduced, resulting in insufficient writing. A drive method which controls the on/off timing of the voltage-holding transistor 11b and the on/off timing of the transistor 11c which writes current (voltage) into the driver transistor 11a is referred to as a time-controlled drive method.
The time-controlled method is not limited to the pixel configuration in
Incidentally, the reset driving in
Needless to say, more excellent image display can be achieved by combining with a reverse bias driving method, a precharge driving method, a penetration voltage driving method, or the like described later. Thus, it goes without saying that reset driving can be performed in combination with other examples according to the present invention. The matters concerning combinations of drive systems also apply to other examples of the present invention.
Thus, the gate signal line 17a is controlled by the gate driver circuit 12a while the gate signal line 17c is controlled by the gate driver circuit 12b. This makes it possible to freely specify the time to turn on the transistor 11b and reset the driver transistor 11a as well as the time to turn on the transistor 11c and program the driver transistor 11a with current. Other parts of the configuration are the same as or similar to those described in
For example, looking at the pixel row (1), in the 1st H, a turn-off voltage is applied to the gate signal line 17c, a turn-on voltage is applied to the gate signal line 17a, and a turn-off voltage is applied to the gate signal line 17b. Consequently, in the 1st H, the pixel row (1) is in reset mode with the transistor 11d off and with no current flowing through the EL element 15.
In the 2nd H, a turn-on voltage is applied to the gate signal line 17c, a turn-on voltage is applied to the gate signal line 17a, and a turn-off voltage is applied to the gate signal line 17b. Consequently, in the 2nd H, the pixel row (1) is in current programming mode with the transistor 11d off and with no current flowing through the EL element 15.
In the 3rd H, a turn-off voltage is applied to the gate signal line 17c, a turn-off voltage is applied to the gate signal line 17a, and a turn-on voltage is applied to the gate signal line 17b. Consequently, in the 3rd H, the pixel row (1) is in image display mode with the transistor 11d on and with current flowing through the EL element 15.
Thus, the capacitor 19 is reset for 1H (one horizontal scanning period). Consequently, the gate terminal G of the transistor 11a has a voltage close to the anode voltage Vdd. Consequently, the transistor 11a is cut off (reset mode). Since the capacitor 19 is reset once to program currents, it is possible to achieve accurate current programming. While the capacitor 19 is reset, the pixel is in non-display mode (even if the transistor 11d is on). This state is close to a state in which black screen is inserted. Thus, by continuing the reset state for a certain period or longer, it is possible to eliminate blurred moving pictures.
Although in the timing chart shown in
The duration of the reset period can be changed easily using a DATA (ST) pulse period inputted in the gate driver circuit 12. For example, if DATA inputted in an ST terminal is set high for a period of 2 Hs, the reset period outputted for each gate signal line 17a is 2 Hs. Similarly, if DATA inputted in the ST terminal is set high for a period of 5 Hs, the reset period outputted for each gate signal line 17a is 5 Hs.
After a reset period of 1 H, a turn-on voltage is applied to the gate signal line 17c(1) of the pixel row (1). As the transistor 11c turns on, the programming current Iw applied to the source signal line 18 is written into the driver transistor 11a via the transistor 11c.
After current programming, a turn-off voltage is applied to the gate signal line 17c of the pixel row (1), the transistor 11c is turned off, and the pixel disconnected from the source signal line. At the same time, a turn-off voltage is also applied to the gate signal line 17a and the driver transistor 11a exits the reset mode (incidentally, the use of the term “current-programming mode” is more appropriate than the term “reset mode” to refer to this period). On the other hand, a turn-on voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and the current programmed into the driver transistor 11a flows through the EL element 15. What has been said about the pixel row (1) similarly applies to the pixel row (2) and subsequent pixel rows. Also, their operation is obvious from
In
Display brightness is decreased commensurately with the length of the reset period. However, by using a programming current N times larger than a predetermined value as in the case of N-fold pulse driving, it is possible to prevent screen brightness from dropping. Thus, reset driving is an embodiment of N-fold pulse driving.
In
In the circuit configuration shown in
As can be seen from the fact that an OR circuit 371 in
Incidentally, the pixel configuration in
In
For example, if the shift register circuit 61a outputs a high-level signal second, a turn-on voltage is output to the gate signal lines 17c of the pixel 16(1), which now is in a state of being programmed with current (voltage). At the same time, a turn-on voltage is also output to the gate signal lines 17a of the pixel 16(2), turning on the transistor 11b of the pixel 16(2) and resetting the driver transistor 11a of the pixel 16(2).
Similarly, if the shift register circuit 61a outputs a high-level signal third, a turn-on voltage is output to the gate signal lines 17c of the pixel 16(2), which now is in a state of being programmed with current (voltage). At the same time, a turn-on voltage is also output to the gate signal lines 17a of the pixel 16(3), turning on the transistor 11b of the pixel 16(3) and resetting the driver transistor 11a of the pixel 16(3). Thus, the gate signal lines 17a outputs turn-on voltages for a period of 2 Hs, and the gate signal lines 17c receive a turn-on voltage for a period of 1 H.
In programming mode, since the transistors 11b and 11c turn on simultaneously (
The above example concerns the pixel configuration in
As shown in
The reset mode (in which no current flows) of the transistors 11a and 11b is equivalent to a state in which a offset voltage is held in voltage offset canceling mode described with reference to
In
As in the case of
After the state in
If the programming current Iw is 0 A (black display), the transistor 11b is held in the state in
After the current programming in
The drive system (reset driving) described with reference to
Incidentally, the operation of disconnecting the driver transistor 11a or 11b from the EL element 15 in the first operation is not absolutely necessary. The drain (D) terminal and gate (G) terminal of the driver transistor are short-circuited in the first operation without disconnecting the driver transistor 11a or 11b from the EL element 15, nothing more than some variations in reset mode may result. Whether to omit disconnection should be determined by considering the characteristics of the transistors in the constructed array.
The current-mirror pixel configuration in
With the current-mirror pixel configuration in
In image display mode (if instantaneous changes can be observed), the pixel row to be programmed with current is reset (black display mode) and is programmed with current after a predetermined H. The pixel row of black display moves from top to bottom of the screen and it should look as if the image were rewritten at the location where the pixel row passed by.
Although the above example has been described mainly in relation to pixel configuration for current programming, the reset driving according to the present invention can also be applied to pixel configuration for voltage programming.
In the configuration shown in
As illustrated in
The reset mode (in which no current flows) of the transistors 11a and 11b is equivalent to a state in which a offset voltage is held in voltage offset canceling mode described with reference to
Incidentally, in the pixel configuration for voltage programming, as the reset period becomes longer, a larger Ib current tends to flow, reducing the terminal voltage of the capacitor 19, as in the case of pixel configuration for current programming. Thus, the operation time in
Besides, it is preferable that the gate signal line 17e should be shared with the gate signal line 17a in a preceding stage. That is the gate signal line 17e should be shorted to the gate signal line 17a in the pixel row in the preceding stage. This configuration is referred to as a preceding-stage gate control system. Incidentally, the stage-stage gate control system uses waveforms of gate signal lines of a pixel row selected one or more Hs before the pixel row of interest. Thus, this system is not limited to the previous pixel row. For example, the driver transistor 11a of the pixel row of interest may be reset using the waveforms of gate signal lines two pixel rows ahead.
The stage-stage gate control system will be described more concretely. Suppose, the pixel row of interest is the (N)-th pixel row whose gate signal lines are 17e(N) and 17a(N). The preceding pixel row selected 1 H before is assumed to be the (N−1)-th pixel row whose gate signal lines are 17e(N−1) and 17a(N−1). The pixel row selected 1 H after the pixel row of interest is assumed to be the (N+1)-th pixel row whose gate signal lines are 17e(N+1) and 17a(N+1).
In the (N−1)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N−1) of the (N−1)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N) of the (N)-th pixel row. This is because the gate signal line 17e(N) and the gate signal line 17a(N−1) of the pixel row in the preceding stage are shorted. Consequently, the pixel transistor 11b(N−1) in the (N−1)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N−1). At the same time, the pixel transistor 11e(N) in the (N)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N) are shorted, and the driver transistor 11a(N) is reset.
In the (N)-th H-period which follows the (N−1)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N) of the (N)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N+1) of the (N+1)-th pixel row. Consequently, the pixel transistor 11b(N) in the (N)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N). At the same time, the pixel transistor 11e(N+1) in the (N+1)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N+1) are shorted, and the driver transistor 11a(N+1) is reset.
Similarly, in the (N+1)-th period which follows the (N)-th H-period, as a turn-on voltage is applied to the gate signal line 17a(N+1) of the (N+1)-th pixel row, a turn-on voltage is also applied to the gate signal line 17e(N+2) of the (N+2)-th pixel row. Consequently, the pixel transistor 11b(N+1) in the (N+1)-th pixel row is turned on and the voltage applied to the source signal line 18 is written into the gate (G) terminal of the driver transistor 11a(N+1). At the same time, the pixel transistor 11e(N+2) in the (N+2)-th pixel row is turned on, the gate (G) terminal and drain (D) terminal of the driver transistor 11a(N+2) are shorted, and the driver transistor 11a(N+2) is reset.
According to the above-described stage-stage gate control system of the present invention, the driver transistor 11a is reset for a period of 1 H, and then voltage (current) programming is performed.
As in the case of
After the state in
When performing voltage programming for white display using the configuration shown in
After the voltage programming in
As described above, the reset driving according to the present invention using the voltage programming shown in
In the above example, the transistor 11d is turned on and off to control the current delivered from the driver transistor 11a (in the case of configuration shown in
Incidentally, although the pixel configuration for current programming illustrated in
Also, the technical concept of turning on and off elements as a block can also be applied to the pixel configuration for voltage programming in
In
Incidentally, although four gate signal lines 17b are grouped into a block here, this is not restrictive and it goes without saying that more than four gate signal lines 17b may be grouped into a block. Generally, it is preferable to divide the display area 50 into five or more parts. More preferably, the screen 50 should be divided into ten or more parts. Even more preferably, the screen 50 should be divided into twenty or more parts. A small number of divisions will make flickering conspicuous. Too large a number of divisions will increase the number of illumination control lines 401, making it difficult to lay out the illumination control lines 401.
Thus, in the case of a QCIF display panel, which has 220 vertical scanning lines, at least 220/5=44 or more lines should be grouped into a block. More preferably, 220/10=22 or more lines should be grouped into a block. However, if odd-numbered rows and even-numbered rows are grouped into two different blocks, there is not much flickering even at a low frame rate, and thus the two blocks are sufficient.
In the example shown in
Incidentally, in the example in
The gate driver circuit 12 is connected with the gate signal lines 17a. When a turn-on voltage is applied to gate signal lines 17a, the appropriate pixel rows are selected and the transistors 11b and 11c in the selected pixel rows are turned on. Then, currents (voltage) applied to the source signal lines 18 are programmed into the capacitors 19 in the pixels. On the other hand, the gate signal lines 17b are connected with the gate (G) terminals of the transistors 11d in the pixels. Thus, when a turn-on voltage (Vgl) is applied to the illumination control lines 401, current paths are formed between the driver transistors 11a and EL elements 15. When a turn-off voltage (Vgh) is applied, the anode terminals of the EL elements 15 are opened.
Preferably, control timing of turn-on/turn-off voltages applied to the illumination control lines 401 and a pixel row selection voltage (Vgl) outputted to the gate signal lines 17a by the gate driver circuit 12 are synchronized with one horizontal scanning clock (1H). However, this is not restrictive.
The signals applied to the illumination control lines 401 simply turn on and off the current delivered to the EL elements 15. They do not need to be synchronized with image data outputted from the source driver circuits 14. This is because the signals applied to the illumination control lines 401 are intended to control the current programmed into the capacitors 19 in the pixels 16. Thus, they do not always need to be synchronized with the pixel row selection signal. Even when they are synchronized, the clock is not limited to a 1-H signal and may be a ½-H or ¼-H signal.
Even in the case of the current-mirror pixel configuration shown in
Incidentally, in
In the above example, one selection gate signal line is placed (formed) per pixel row. The present invention is not limited to this and a selection gate signal line may be placed (formed) for two or more pixel rows.
Thus, when the gate signal line 17a is selected, the pixels 16R, 16G, and 16B are selected and get ready to write data. The pixel 16R writes data into a capacitor 19R via a source signal line 18R, the pixel 16G writes data into a capacitor 19G via a source signal line 18G, and the pixel 16B writes data into a capacitor 19B via a source signal line 18B.
The transistor 11d of the pixel 16R is connected to a gate signal line 17bR, the transistor 11d of the pixel 16G is connected to a gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to a gate signal line 17bB. Thus, an EL element 15R of the pixel 16R, EL element 15G of the pixel 16G, and EL element 15B of the pixel 16B can be turned on and off separately. Illumination times and illumination periods of the EL element 15R, EL element 15G, and EL element 15B can be controlled separately by controlling the gate signal line 17bR, gate signal line 17bG, and gate signal line 17bB.
To implement this operation, in the configuration in
Incidentally, although it has been stated that a current N times larger than a predetermined current is passed through the source signal line 18 and that a current N times larger than a predetermined current is passed through the EL element 15 for a period of 1/N, this cannot be implemented in practice. Actually, signal pulses applied to the gate signal line 17 penetrate into the capacitor 19, making it impossible to set a desired voltage value (current value) on the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set on the capacitor 19. For example, even if 10 times larger current value is meant to be set, only approximately 5 times larger current value is set on the capacitor 19. For example, even if N=10 is specified, N=5 times larger current actually flows through the EL element 15. Thus, this method sets an N times larger current value to pass a current proportional or corresponding to the N-fold value through the EL element 15. Alternatively, this drive method applies a current larger than a desired value to the EL element 15 in a pulsed manner.
This method performs current (voltage) programming so as to obtain desired emission brightness of the EL element by passing a current larger than a desired value intermittently through the driver transistor 11a (in the case of
Incidentally, a compensation circuit which employs the penetration to the capacitor 19 is installed in the source driver circuit 14. This will be described later.
Preferably, N-channel transistors are used as the switching transistors 11b and 11c, etc. in
Depending on pixel configuration, if the penetration voltage tends to increase the current flowing through the EL element 15, white peak voltage will increase, increasing perceived contrast in image display. This provides for a good image display.
Conversely, it is also useful to use P-channel transistors as the switching transistors 11b and 11c in
Besides, it is useful to increase penetration voltage by intentionally forming a capacitor 19b between the gate signal line 17a and the gate (G) terminal of the transistor 11a (see
Let Cb (pF) denote the capacitance of the penetration-voltage generating capacitor 19b, let Ca (pF) denote the capacitance of the capacitor 19a, let Vw denote the gate (G) terminal voltage of the transistor 11a in the case of white peak current (during white raster display at the maximum display brightness), and let Vb denote the gate (G) terminal voltage in the case of black display current (basically when the current is 0, i.e., during black display), preferably the following relationship is satisfied.
Ca/(200Cb)≦|Vw−Vb|≦Ca/(8Cb)
Incidentally, |Vw−Vb| is the absolute value of the difference in the terminal voltage of the driver transistor between white display and black display (i.e., a variable voltage range).
More preferably the following relationship is satisfied.
Ca/(100Cb)≦|Vw−Vb|≦Ca/(10Cb)
The transistor 11b should be a p-channel transistor and should have at least two gates. Preferably, it has three or more gates. More preferably, it has four or more gates. Capacitors with a capacitance of 1 to 10 times the source-gate (SD or gate-drain (GD)) capacitance of the transistor 11b (when activated) are placed or formed in series.
Incidentally, the above items apply not only to the pixel configuration in
In the voltage-programming pixel configuration in 41, a penetration-voltage generating capacitor 19c is formed or placed between the gate signal line 17c and gate (G) terminal of the driver transistor 11a. The switching transistor 11c should have three or more gates. The penetration-voltage generating capacitor 19c may be formed or placed between the drain (D) terminal of the transistor 11c (on the side of the capacitor 19b) and the gate signal line 17a. Also, the penetration-voltage generating capacitor 19c may be formed or placed between the gate (G) terminal of the transistor 11a and the gate signal line 17a. The penetration-voltage generating capacitor 19c may be formed or placed between the drain (D) terminal of the transistor 11c (on the side of the capacitor 19b) and the gate signal line 17c.
Let Ca denote the capacitance of the charge-holding capacitor 19a, let Cc denote the source-gate capacitance (the capacitance of any penetration-voltage generating capacitor is added) of the switching transistor 11c or 11d, let Vgh denote a high voltage signal applied to the gate signal line, and let Vgl denote a low voltage signal applied to the gate signal line, proper black display can be achieved if the following relationship is satisfied.
0.05 (V)≦(Vgh−Vgl)×(Cc/Ca)≦0.8 (V)
More preferably the following relationship is satisfied.
0.1 (V)≦(Vgh−Vgl)×(Cc/Ca)≦0.5 (V)
The above items also apply to the pixel configurations in
Incidentally, the penetration-voltage generating capacitor 19b is formed by the source wiring and gate wiring of the transistor. However, since the capacitor 19b is formed by increasing the source width of the transistor 11 and lapping the source wiring over the gate signal line 17, there may be cases in which the capacitor 19b is not separated clearly from the transistor in a practical sense.
The approach of constructing a penetration-voltage generating capacitor 19b in appearance by making the switching transistors 11b and 11c (in the configuration in
The switching transistors 11b and 11c are often formed in such a way as to satisfy a relationship: channel width W/channel length L=6/6 μm. Increasing the W amounts to constructing a penetration-voltage generating capacitor 19b. For example, the ratio of W to L is configured to be between 2:1 and 20:1 (both inclusive). Preferably, the ratio of W to L is between 3:1 and 10:1 (both inclusive).
Preferably, the size (capacitance) of the penetration-voltage generating capacitors 19b is varied among R, G, and B, which make pixels modulated. This is because drive current varies among the EL elements 15 of R, G, and B as well as because cutoff voltage varies with the EL element 15, varying the voltage (current) programmed into the gate (G) terminal of the driver transistor 11a among the EL elements 15. For example, if a capacitor 19bR for the R pixel is 0.02 pF, capacitors 19bG and 19bB for the other colors (G and B pixels) should be 0.025 pF. Also, if the capacitor 19bR for the R pixel is 0.02 pF, the capacitor 19bG for the G pixel should be 0.03 pF and the capacitor 19bB for the B pixel should be 0.025 pF, for example. By varying the capacitance of the capacitors 19b among the R, G, and B pixels in this way, it is possible to adjust offset drive current separately for R, G, and B. This makes it possible to optimize black display levels for R, G, and B.
It has been described that the capacitance of the penetration-voltage generating capacitors 19b is varied, but the penetration voltage is determined relatively depending on relationship between the capacitance of the charge-holding capacitor 19a and capacitance of the penetration-voltage generating capacitor 19b. Thus, it is not strictly necessary to vary the capacitors 19b among the R, G, and B pixels.
That is, the capacitance of the charge-holding capacitors 19a may be varied. For example, if the capacitor 11aR for the R pixel is 1.0 pF, the capacitor 11aG for the G pixel may be 1.2 pF and the capacitor 11bB for the B pixel may be 0.9 pF. At this time, the capacitance of the penetration-voltage generating capacitors 19b should be common among R, G, and B. Thus, according to the present invention, the capacitance ratio between the charge-holding capacitors 19a and penetration-voltage generating capacitors 19b is varied at least for one of the RGB colors. Incidentally, both the capacitance of the charge-holding capacitors 19a and capacitance of the penetration-voltage generating capacitors 19b may be varied among the R, G, and B pixels.
Also, the capacitance of the penetration-voltage generating capacitors 19b may be varied between the left and right of the screen 50. In the case of pixels 16 located close to the gate drivers 12, since they are placed on the signal supply side, gate signals rise quickly (because of a high through-rate), resulting in a high penetration voltage. Pixels placed (formed) at the ends of the gate signal lines 17 have blunt waveforms (because the gate signal lines 17 have capacitance). This is because gate signals rise slowly (because of a low through-rate), resulting in a low penetration voltage. Thus, the penetration-voltage generating capacitors 19b of the pixels 16 close to the side of connection with the gate drivers 12 should be downsized. Also, capacitors 19b at the ends of the gate signal lines 17 should be enlarged.
For example, the capacitance of the capacitors is varied by approximately 10% between the left and right of the screen.
The penetration voltage generated depends on the capacitance ratio between the charge-holding capacitors 19a and penetration-voltage generating capacitors 19b. Thus, although it has been stated that the capacitance of the penetration-voltage generating capacitors 19b are varied between the left and right of the screen, this is not restrictive. It is also possible to keep the capacitance of the penetration-voltage generating capacitors 19b constant between the left and right of the screen and vary the capacitance of the charge-holding capacitors 19a between the left and right of the screen. Needless to say, it is also possible to vary both the capacitance of the penetration-voltage generating capacitors 19b and capacitance of the charge-holding capacitors 19a between the left and right of the screen.
One of the problems with the N-fold pulse driving according to the present invention is that the current applied to the EL elements 15 is N times larger than the current applied conventionally although instantaneously. Large current may shorten the life of EL elements. To solve this problem, it is useful to apply a reverse bias voltage Vm to the EL elements 15.
In the above example, RGB image data is rewritten within a field (frame). The RGB data may be rewritten sequentially. The term “sequentially” means rewriting R image data in the first field, G image data in the second field, and B image data in the third field assuming that one frame consists of three fields. This drive method is referred to as sequential driving.
Needless to say, sequential driving may be used in combination with another drive method according to the present invention such as N-fold pulse driving or reset driving. Display panels employing a combination of drive methods according to the present invention or display apparatus employing such a display panel are also included in the present invention.
Signals outputted from the source driver circuit 14 to the connection terminals 996 are allocated to 18R, 18G, and 18B by an output switching circuit 751. The output switching circuit 751 is formed directly on an array board 71 by polysilicon technology. Alternatively, it may be formed with silicon chips and mounted on the array board 71 by COG technology. Also, the output switching circuit 751 may be incorporated into the source driver circuit 14 as a sub-circuit of the source driver circuit 14.
If a changeover switch 752 is connected to an R terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18R. If the changeover switch 752 is connected to a G terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18G. If the changeover switch 752 is connected to a B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18B.
Incidentally, in the configuration in
When the changeover switch 752 is connected to the G terminal, the R terminal and B terminal of the changeover switch are open. Thus, the current entering the source signal lines 18R and 18B is 0 A. Consequently, the pixels 16 connected to the source signal lines 18R and 18B provide a black display.
In the configuration in
Basically, if one frame consists of three fields, R image data is written in sequence into the pixels 16 in the display area 50 in the first field. In the second field, G image data is written in sequence into the pixels 16 in the display area 50. In the third field, B image data is written in sequence into the pixels 16 in the display area 50.
Thus, R data→G data→B data→R data→ . . . are rewritten in sequence in the appropriate fields to implement sequential driving. Description of how N-fold pulse driving is performed by turning on and off the switching transistor 11d as shown in
In the above example, it has been stated that when image data is written into the R pixel 16, black data is written into the G pixel and B pixel, that when image data is written into the G pixel 16, black data is written into the R pixel and B pixel, and that when image data is written into the B pixel 16, black data is written into the R pixel and G pixel. The present invention is not limited to this.
For example, when image data is written into the R pixel 16, the G pixel and B pixel may retain the image data rewritten in the previous field. This can make the screen 50 brighter. When image data is written into the G pixel 16, the R pixel and B pixel may retain the image data rewritten in the previous field. When image data is written into the B pixel 16, the G pixel and R pixel may retain the image data rewritten in the previous field.
In order to retain image data in pixels other than the color pixel being rewritten, the gate signal line 17a can be controlled separately for the R, G, and B pixels. For example, as illustrated in
With the above configuration, when the source driver circuit 14 outputs R image data and the changeover switch 752 is set to an R contact, a turn-on voltage can be applied to the gate signal line 17aR and a turn-off voltage can be applied to the gate signal lines aG and aB. Thus, the R image data can be written into the R pixel 16 and the G pixel 16 and R pixel 16 can retain the image data of the previous field.
When the source driver circuit 14 outputs G image data in the second field and the changeover switch 752 is set to a G contact, a turn-on voltage can be applied to the gate signal line 17aG and a turn-off voltage can be applied to the gate signal lines aR and aB. Thus, the G image data can be written into the G pixel 16 and the R pixel 16 and B pixel 16 can retain the image data of the previous field.
When the source driver circuit 14 outputs B image data in the third field and the changeover switch 752 is set to a B contact, a turn-on voltage can be applied to the gate signal line 17aB and a turn-off voltage can be applied to the gate signal line aR and aG. Thus, the B image data can be written into the B pixel 16 and the R pixel 16 and G pixel 16 can retain the image data of the previous field.
In the example shown in
In relation to the configuration in
In the state shown in
In the above state, the B pixel is being rewritten and a black display voltage is applied to the R pixel and G pixel. As the changeover switches 752 are controlled in the above manner, an image composed of the pixels 16 are rewritten. Incidentally, control of the gate signal lines 17b is the same as in the examples described above, and thus detailed description thereof will be omitted.
In the above example, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field. The present invention is not limited to this. The color of the pixel rewritten may be changed every horizontal scanning period (1 H). For example, a possible drive method involves rewriting the R pixel in the first H, the G pixel in the second H, the B pixel in the third H, the R pixel in the fourth H, and so on. Of course, the color of the pixel rewritten may be changed every two horizontal scanning periods or every ⅓ field.
Needless to say, in the drive system in
One frame need not necessarily consist of three fields and may consist of two fields or four or more fields. In one example illustrated herein, one frame consists of two fields and the R and G pixels out of the three primary RGB colors are rewritten in the first field and the B pixel is rewritten in the second field. In another example illustrated herein, one frame consists of four fields and the R pixel out of the three primary RGB colors is rewritten in the first field, the G pixel is rewritten in the second field, and the B pixel is rewritten in the third and fourth field. In these sequences, white balance can be achieved more efficiently if the luminous efficiencies of the R, G, and B EL elements 15 are taken into consideration.
In the above example, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten changes every field.
According to the example shown in
According to the example shown in
Thus, by rewriting the R, G, and B pixels in each field arbitrarily or with some regularity, it is possible to prevent separation among the R, G, and B colors. Also, flickering is reduced.
In
In
Incidentally, even in the example in
As shown in
The panel in an example in
Needless to say, the drive method in
Incidentally, for ease of explanation, it is assumed that the display panel according to the present invention has the three primary colors RGB, but this is not restrictive. The display panel may have cyan, yellow, and magenta in addition to R, G, and B, or it may have any one of R, G, and B or any two of R, G, and B.
Also, although it has been stated that the sequential driving system handles R, G, and B in each field, it goes without saying that the present invention is not limited to this. Besides, the examples in
Also, the drive methods in
b) shows an example in which a plurality of RGB display areas 53 are generated during one field (one frame) period. This drive method is analogous to the one shown in
a) shows a case in which R, G, and B display areas 53 have different sizes (needless to say, the size of a display area 53 is proportional to its illumination period). In
b) shows an example in which there are a plurality of B display periods 53B (53B1 and 53B2) during one field (one frame) period. Whereas
The drive system according to the present invention is not limited to either
Incidentally, the drive method in
The above driving can be implemented by forming or placing a gate driver circuit 12bR which controls the gate signal line 17bR, a gate driver circuit 12bG which controls the gate signal line 17bG, and a gate driver circuit 12bB which controls the gate signal line 17bB, as illustrated in
Also, with the configuration shown in
In the EL element 15, electrons are injected into an electron transport layer from the negative pole (cathode) while at the same time positive holes are injected into a positive hole transport layer from the positive pole (anode). The injected electrons and positive holes move to the opposite pole under the influence of applied electric fields. In so doing, electrons and positive holes are trapped in an organic layer, and carriers are accumulated due to difference in energy levels on boundaries of a light-emitting layer.
It is known that accumulation of space charges in the organic layer causes molecules to be oxidized or reduced, producing unstable radical anion molecules or radical cation molecules, which in turn degrade membrane quality, resulting in reduced brightness and increased drive voltage during constant-current driving. To prevent this, device structure is changed and reverse voltage is applied, for example.
Application of a reverse bias voltage means application of a reverse current, and thus injected electrons and positive holes are drawn to the negative and positive poles, respectively. This makes it possible to cancel formation of space charge in the organic layer and reduce electro-chemical degradation, thereby prolonging the life.
The vertical axis represents the ratio of the terminal voltage after 2500 hours to the initial terminal voltage of the EL element 15. For example, if the terminal voltage is 8 V and 10 V, respectively, when a current with a current density of 100 A per square meter is applied at time 0 (zero) and after 2500 hours, the terminal voltage ratio is 10/8=1.25.
The horizontal axis represents the ratio of the product of the reverse bias voltage Vm and its application duration t1 in a period to a rated terminal voltage V0. For example, if the reverse bias voltage Vm is applied at 60 Hz (60 Hz has no particular meaning) for ½ (half) a period, then t1=0.5. Further, t2 is the application duration of the rated terminal voltage. Also, if the terminal voltage (rated terminal voltage) is 8 V when a current with a current density of 100 A per square meter is applied at time 0 (zero) and if the reverse bias voltage Vm is −8V, then |reverse bias voltage×t1|/(rated terminal voltage×t2)=|−8 (V)×0.5|/(8 (V)×0.5)=1.0.
In
However, for bias driving, the reverse bias Vm and rated current should be applied alternately. To equalize average brightness of samples A and B over a unit time as shown in
However, in
The above description assumes white raster display (maximum voltage is applied to all the EL elements 15 in the screen). However, video display on an EL display apparatus is provided as gradation display of natural images. Thus, it is not that a white peak current (a current which flows during maximum white display, or a current with an average current density of 100 A per square meter according to the examples described herein) always flows through the EL elements 15.
Generally, in the case of video display, the current applied to (passed through) each EL element 15 is approximately 0.2 of a white peak current (a current which flows at a rated terminal voltage, or a current with a current density of 100 A per square meter according to examples cited herein).
Therefore, for video display in the example in
That is, on the horizontal axis (|reverse bias voltage×t1|/(rated terminal voltage×t2)) in
Basically, according to the present invention, a reverse bias voltage Vm (current) is applied during periods in which current does not flow through the EL element 15. However, this is not restrictive. For example, a reverse bias voltage Vm (current) may be applied forcibly when current flows through the EL element 15. In that case, however, the current will stop flowing through the EL element 15 as a result, bringing about non-illumination mode (black display mode). Also, although description herein is focused on application of a reverse bias voltage Vm in a current-programming pixel configuration, this is not restrictive.
In a pixel configuration for reverse bias driving, an N-channel transistor 11g is used as shown in
In
In the pixel configuration in
Also, a gate driver circuit 12c may be formed or placed separately to control the reverse bias line 471 as illustrated in
The drive method described above makes it possible to apply the reverse bias voltage Vm to the EL element 15 by varying only the potential of the reverse bias line 471 with the gate (G) terminal of the transistor 11g set at a fixed potential. This makes it easy to control the application of the reverse bias voltage Vm. Also, the voltage applied between the source (S) terminal and gate (G) terminal of the transistor 11g can be decreased. This similarly applies when the transistor 11g is a p-channel transistor.
The reverse bias voltage Vm is applied when current is not passed through the EL element 15. This can be done by turning on the transistor 11g when the transistor 11d is off. That is, the reverse of on/off logic of the transistor 11d can be applied to the gate potential control line 473. For example, in
When a turn-on voltage (Vgl) is applied to the gate signal line 17a (1) in the first pixel row, a turn-off voltage (Vgh) is applied to the gate signal line 17b (1) in the first pixel row. Thus, the transistor 11d is off and current does not flow through the EL element 15.
A voltage Vsl (which turns on the transistor 11g) is applied to a reverse bias line 471(1). Thus, the transistor 11d is on and a reverse bias voltage is applied to the EL element 15. The reverse bias voltage is applied a predetermined period ( 1/200 of 1H or longer; or 0.5 μsec) after the turn-off voltage (Vgh) is applied to the gate signal line 17b. The reverse bias voltage is turned off a predetermined period ( 1/200 of 1 H or longer; or 0.5 μsec) before the turn-on voltage (Vgl) is applied to the gate signal line 17b. This is done in order to prevent the transistors 11d and 11g from turning on simultaneously.
In the next 1 H (horizontal scanning period), a turn-off voltage (Vgh) is applied to the gate signal line 17a, and the second pixel row is selected. That is, a turn-on voltage is applied to a gate signal line 17b(2). On the other hand, a turn-on voltage (Vgl) is applied to the gate signal line 17b, the transistor 11d is turned on, and a current from the transistor 11a flows through the EL element 15, causing the EL element 15 to emit light. Also, a turn-off voltage (Vgh) is applied to the reverse bias line 471(1) stopping the reverse bias voltage from being applied to the EL elements 15 in the first pixel row (1). The voltage Vsl (reverse bias voltage) is applied to a reverse bias line 471(2) in the second pixel row.
As the above operations are repeated in sequence the images on the entire screen is rewritten. In the above example, a reverse bias voltage is applied while the pixels are being programmed. However, the circuit configuration in
Reverse bias voltage can be applied not only during image display. The reverse bias voltage may be applied for a predetermined period after the EL display apparatus is turned off.
Although the above example has been described with reference to the pixel configuration in
The transistor 11d turns on 1 H (horizontal scanning period, i.e., one pixel row) or more before the given pixel is selected. Preferably, it turns on at least 3 Hs before. In that case, the transistor 11d turns on 3 Hs before selection of the pixel, short-circuiting the gate (G) terminal and drain (D) terminal of the transistor 11a. Consequently, the transistor 11a is turned off. Thus, the current stops flowing through the transistor 11b and the EL element 15 is turned off.
When the EL element 15 is not illuminated, the transistor 11g turns on, applying a reverse bias voltage to the EL element 15. Thus, the reverse bias voltage is applied while the transistor 11d is on. Consequently, the transistor 11d and transistor 11g turn on simultaneously in logical terms.
The voltage Vsg is applied continuously to the gate (G) terminal of the transistor 11g. The transistor 11g turns on when a reverse bias voltage sufficiently smaller than the voltage Vsg is applied to the reverse bias line 471.
Subsequently, when there comes a horizontal scanning period in which a video signal is applied to (written into) the pixel, a turn-on voltage is applied to a gate signal line 17a1, turning on the transistor 11c. Thus, a video signal voltage outputted from the source driver circuit 14 to the source signal line 18 is applied to the capacitor 19 (the transistor 11d remains on).
When the transistor 11d is turned on, the pixel is put into black display mode. The longer the conduction period of the transistor 11d in one field (one frame) period, the larger the proportion of the black display period. Thus, the brightness during a display period needs to be increased to obtain a desired average brightness over one field (one frame) in spite of the black display period. That is, the current to be passed through the EL element 15 during the display period needs to be increased. This operation is based on the N-fold pulse driving according to the present invention. Thus, an operation characteristic of the present invention is implemented by a combination of the N-fold pulse driving and driving which involves creating a black display by turning on the transistor 11d. Also, a configuration (method) characteristic of the present invention involves applying a reverse bias voltage to the EL element 15 when the EL element 15 is not illuminated.
Although in the above example, a reverse bias voltage is applied when pixels are not illuminated during image display, the configuration in which a reverse bias voltage is applied is not limited to this. There is no need to form a reverse-biasing transistor 11g in each pixel as long as a reverse bias voltage is applied when no image is displayed. The phrase “not illuminated” means a configuration in which a reverse bias voltage is applied after or before using the display panel.
For example, in the pixel configuration in
The N-fold pulse driving allows a predetermined current (programmed current (at a voltage held in the capacitor 19)) to be passed through the EL element 15 again during one field (one frame) period even after a black display is created once. With the configuration in
Incidentally, although the above example uses a pixel configuration for current programming, the present invention is not limited to this and is applicable to other current-based pixel configurations such as those shown in
With the pixel configuration in
To describe the configuration in
The initialization operation is performed after a horizontal synchronization signal (HD) is provided. A turn-on voltage is applied to the gate signal line 17b, turning on the transistor 11g. Besides, a turn-on voltage is also applied to the gate signal line 17a, turning on the transistor 11c. At this time, a voltage Vdd is applied to the source signal line 18. Thus, the voltage Vdd is applied to a terminal a of the capacitor 19b. In this state, the driver transistor 11a turns on and a small current flows through the EL element 15. This current makes the voltage on the drain (D) terminal of the driver transistor 11a larger in absolute value than at least the voltage at an operating point of the driver transistor 11a.
Next, the reset operation is performed. A turn-off voltage is applied to the gate signal line 17b, turning off the transistor 11e. On the other hand, a turn-on voltage is applied to the gate signal line 17c for a period of T1, turning on the transistor 11b. The period T1 corresponds to a reset period. A turn-on voltage is applied to the gate signal line 17a continuously for a period of 1 H. Preferably, the period T1 is between 20% and 90% (both inclusive) of 1 H or between 20 μsec and 160 μsec (both inclusive). Preferably, a capacitance ratio Ca/Cb between a capacitor 19b (Cb) and capacitor 19a (Ca) is between 1/6 and 2/1 (both inclusive).
During a reset period, the transistor 11b turns on, short-circuiting the gate (G) terminal and drain (D) terminal of the driver transistor 11a. Thus, the voltages at the gate (G) terminal and drain (D) terminal of the transistor 11a become equal, putting the transistor 11a in an offset mode (reset mode: a state in which no current flows). In the reset mode, the voltage at the gate (G) terminal of the transistor 11a approaches a starting voltage at which a current starts to flow. A gate voltage which maintains the reset mode is held at a terminal b of the capacitor 19b. Thus, the capacitor 19 holds an offset voltage (reset voltage).
In a next programming mode, a turn-off voltage is applied to the gate signal line 17c, turning off the transistor 11b. On the other hand, DATA voltage is applied to the source signal line 18 for a period of Td. Thus, the sum of the DATA voltage and offset voltage (reset voltage) is applied to the gate (G) terminal of the driver transistor 11a. This allows the driver transistor 11a to pass a programmed current.
After the programming period, a turn-off voltage is applied to the gate signal line 17a, turning off the transistor 11c and cutting off the driver transistor 11a from the source signal line 18. Besides, a turn-off voltage is also applied to the gate signal line 17c, turning off the transistor 11b, which remains off for a period of 1F. On the other hand, a turn-on voltage and turn-off voltage are applied to the gate signal line 17b periodically, as required. Thus, if combined with N-fold pulse driving in
With the drive system in
To apply the reverse bias voltage Vm to the EL element 15, it is necessary to turn off the transistor 11a. To turn off the transistor 11a, the drain terminal and gate (G) terminal of the transistor 11a can be short-circuited. This configuration will be described with reference to
Alternatively, it is possible to apply the Vdd voltage or a voltage which turns off the transistor 11a to the source signal line 18, turn on the transistor 11b, and apply the voltage to the gate (G) terminal of the transistor 11a. This voltage turns off the transistor 11a (or makes it pass almost no current (almost off: the transistor 11a is in a high-impedance state)). Subsequently, the transistor 11g is turned on and a reverse bias voltage is applied to the EL element 15. The reverse bias voltage Vm may be applied to all the pixels simultaneously. Specifically, a voltage which almost turns off the transistors 11a is applied to the source signal lines 18 and the transistors 11b in all the pixel rows are turned on. Consequently, the transistors 11a are turned off. Then, the transistors 11g are turned on and a reverse bias voltage is applied to the EL elements 15. Then, video signals are applied to one after another of the pixel rows to display images on the display apparatus.
Next, reset driving in the pixel configuration in
Thus, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16a, the pixel 16a enters voltage programming mode, the reset transistor 11b of the pixel 16b in the next stage turns on, and the driver transistor 11a of the pixel 16b is reset. Similarly, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11c in the pixel 16b, the pixel 16b enters current programming mode, the reset transistor 11b of the pixel 16c in the next stage turns on, and the driver transistor 11a of the pixel 16c is reset. Thus, reset driving by way of a preceding-stage gate control system can be implemented easily. Also, the number of leads from a gate signal line per pixel can be reduced.
More detailed description will be provided. Suppose voltage is applied to gate signal lines 17 as shown in
In this state, the pixel 16a is in voltage programming mode and is not illuminated, the pixel 16b is in reset mode and not illuminated, the pixel 16c is pending current programming and is illuminated, and the pixel 16d is pending current programming and is illuminated.
After 1 H, data in a shift register 61 circuit of the controlling gate driver circuit 12 is shifted one bit to enter a state shown in
Thus, it can be seen that the voltage applied to the gate signal line 17a of each pixel resets the driver transistor 11a of the pixel in the next stage to perform voltage programming in the next horizontal scanning period sequentially.
The pixel configuration for voltage programming in
In
Thus, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16a, the pixel 16a enters voltage programming mode, the reset transistor 11e of the pixel 16b in the next stage turns on, and the driver transistor 11a of the pixel 16b is reset. Similarly, when a turn-on voltage is applied to the gate signal line 17a connected to the gate (G) terminal of the transistor 11b in the pixel 16b, the pixel 16b enters current programming mode, the reset transistor 11e of the pixel 16c in the next stage turns on, and the driver transistor 11a of the pixel 16c is reset. Thus, reset driving by way of a preceding-stage gate control system can be implemented easily.
More detailed description will be provided. Suppose voltage is applied to gate signal lines 17 as shown in
In this state, the pixel 16a is in voltage programming mode, the pixel 16b is in reset mode, the pixel 16c is pending current programming, and the pixel 16d is pending current programming.
After 1 H, data in the shift register 61 circuit of the controlling gate driver circuit 12 is shifted one bit to enter a state shown in
Thus, it can be seen that the voltage applied to the previous stage for the gate signal line 17a of each pixel resets the driver transistor 11a of the pixel in the next stage to perform voltage programming in the next horizontal scanning period sequentially.
For completely black display in current driving, the driver transistors 11 of the pixels are programmed with 0 current. That is, the source driver circuit 14 delivers no current. When no current is delivered, parasitic capacitance caused in the source signal line 18 cannot be discharged and the potential of the source signal line 18 cannot be varied. Consequently, the gate potential of the driver transistors also remains unchanged and the potential in the previous frame (field) (1 F) remains accumulated in the capacitor 19. For example, if the previous frame contains white display, the white display is retained even if the current frame contains completely black display.
To solve this problem, according to the present invention, a black level voltage is written into the source signal line 18 at the beginning of one horizontal scanning period (1 H) before the current to be programmed is output to the source signal line 18. For example, if image data consists of the 0th to 7th gradations close to black level, a black level voltage is written only during a certain period at the beginning of one horizontal scanning period to reduce the load of current programming and make up for insufficient writing. Incidentally, completely black display corresponds to the 0th gradation and white display corresponds to the 63rd gradation (in the case of 64-gradation display).
Preferably, gradations for which precharging is performed should be limited to a black display region.
Specifically, precharging is performed by selecting gradations in a black region (low brightness region, in which only a small (weak) write current flows in the case of current driving) from write image data (selective precharging).
If precharging is performed over the entire range of gradations, brightness lowers (a target brightness is not reached) in a white display region.
Also, vertical streaks may be displayed in some cases.
Preferably, selective precharging is performed for ⅛ of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 7th gradations). More preferably, selective precharging is performed for 1/16 of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 3rd gradations).
A method which performs precharging by detecting only the 0th gradation is also effective in enhancing contrast, especially in black display. It achieves an extremely good black display. The problem is that the screen appears whitish in hue when the entire screen displays the 1st and second gradations. Thus, selective precharging is performed in a predetermined range: ⅛ of all the gradations beginning with the 0th gradation.
Incidentally, it is also useful to vary the precharge voltage and gradation range among R, G, and B because emission start voltage and emission brightness of EL display elements 15 vary among R, G, and B. For example, selective precharging is performed for ⅛ of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 7th gradations) in the case of R. In the case of other colors (G and B), selective precharging is performed for 1/16 of all the gradations beginning with the 0th gradation (e.g., in the case of 64 gradations, image data is written after precharging for the 0th to 3rd gradations). Regarding the precharge voltage, if 7 V is written into the source signal lines 18 for R, 7.5 V is written into the source signal lines 18 for the other colors (G and B). Optimum precharge voltage often varies with the production lot of the EL display panel. Thus, preferably precharge voltage is adjustable with an external regulator or the like. Such a regulator circuit can be also implemented easily using an electronic regulator circuit.
A charge-holding capacitor 19 has been formed in the pixel 16. If 10% or more of the electric charges held in the capacitor 19 is discharged during one field (one frame) period, black display mode cannot be maintained. Regarding image display condition, pixels which contain transistors 11 with poor turn-off characteristics produce bright spots (referred to as off-leakage bright spots). Thus, it is necessary to use transistors with good turn-off characteristics, especially in the case of the transistor 11b in
To solve this problem, the present invention turns off active transistors 11d for a short period of time by operating the gate signal lines 17b. This drive method can reduce off-leakage bright spots even if the voltage-holding transistors 11b have poor turn-off characteristics. Also, by varying the OFF period of the voltage-holding transistors 11b, it is possible to control the extent to which off-leakage bright spots are reduced.
As illustrated in
Also, the drive method for a display panel according to the present invention displays images by switching among the conditions in
When the transistor 11d turns off, the potential at point A rises at least once. Consequently, as illustrated in
That is, as the transistor 11d is turned on and off, the capacitor 19 is charged.
Incidentally, the above description is derived from theoretical considerations of a phenomenon. Thus, there might be mistaken understanding. However, it is true that the use of the drive method according to the present invention in an actual panel is effective in reducing off-leakage bright spots.
In the pixel configuration in
Now, a concept of “duty” will be introduced for ease of explanation. The term “duty” according to the present invention differs from a term “duty” used in relation to STN liquid crystal display panels. A duty ratio of 1/1 according to the present invention means a drive mode in which current flows through the EL elements 15 for a period of one field (one frame). That is, the duty ratio of 1/1 means a state in which the non-display area 52 takes up 0% of the display screen 50. Actually, however, since the pixel rows being programmed with current (voltage) are in non-display mode, the duty ratio of 1/1 in a strict sense cannot occur in the pixel configuration in
For example, a duty ratio of 220/220 is reduced to a duty ratio of 1/1. Also, a duty ratio of 55/220 is reduced to a duty ratio of 1/4. When the duty ratio is 1/4, 3/4 of the screen is taken up by a non-display area 52. Thus, in N-fold pulse driving, a target (predetermined) display brightness can be obtained when N=4. A duty ratio of 110/220 is reduced to a duty ratio of 1/2. When the duty ratio is 1/2, 50% of the screen is taken up by a non-display area 52. Thus, in N-fold pulse driving, a predetermined display brightness can be obtained when N=2.
In the description of the display panel according to the present invention, it is assumed that the pixel rows to be programmed with current are selected by the gate signal line 17a (in the case of
The gate driver circuits 12 are fed a start pulse, which is shifted as holding data in sequence within a shift register. Based on the holding data in the shift register of the gate driver circuit 12a, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the WR-side selection signal line. An OEV1 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12a. When the OEV1 circuit is low, a WR-side selection signal which is an output of the gate driver circuit 12a is outputted as it is to the gate signal line 17a. The above relationship is illustrated logically in
That is, when the gate driver circuit 12a outputs a turn-off voltage, the turn-off voltage is applied to the gate signal line 17a. When the gate driver circuit 12a outputs a turn-on voltage (logic low), it is ORed with the output of the OEV1 circuit by the OR circuit and the result is outputted to the gate signal line 17a. That is, when the OEV1 circuit is high, the turn-off voltage (Vgh) is outputted to the gate driver signal line 17a.
Based on holding data in a shift register of the gate driver circuit 12b, it is determined whether to output a turn-on voltage (Vgl) or turn-off voltage (Vgh) to the gate signal line 17B (EL-side selection signal line). An OEV2 circuit (not shown) which turns off output forcibly is formed or placed in an output stage of the gate driver circuit 12b. When the OEV2 circuit is low, an output of the gate driver circuit 12b is outputted as it is to the gate signal line 17b. The above relationship is illustrated logically in
That is, when the gate driver circuit 12b outputs a turn-off voltage (an EL-side selection signal is a turn-off voltage), the turn-off voltage is applied to the gate signal line 17b. When the gate driver circuit 12b outputs a turn-on voltage (logic low), it is ORed with the output of the OEV2 circuit by the OR circuit and the result is outputted to the gate signal line 17b. That is, when an input signal is high, the OEV2 circuit outputs the turn-off voltage (Vgh) to the gate driver signal line 17b. Thus, even if the EL-side selection signal from the OEV2 circuit is a turn-on voltage, the turn-off voltage (Vgh) is outputted forcibly to the gate signal line 17b. Incidentally, if an input to the OEV2 circuit is low, the EL-side selection signal is outputted directly to the gate signal line 17b.
In the example described below, to deal with off-leakage bright spots, the states in
The gate driver circuit 12b (EL-side selection signal line) applies logic high to the OEV2 circuit every horizontal scanning period (1 H) by operating the OEV2 circuit as illustrated in
By operating the OEV2 circuit, it is possible to control the illumination period of the EL elements 15. Thus, the brightness of the screen 50 can be varied through the control of the OEV2 circuit. That is, the OEV2 circuit has the effect of reducing off-leakage bright spots and controlling the screen brightness.
In
Driving with a duty ratio of 1/1 causes off-leakage bright spots. This is because the transistor 11b leaks due to a high inter-channel (SD) voltage of the transistor 11b. As illustrated in
Incidentally, although it has been stated with reference to
It has been stated with reference to
Thus, by applying a turn-off voltage to the gate signal line 17b, it is possible to reduce off-leakage bright spots. However, if the turn-off voltage applied to the gate signal line 17b is too short, it is not effective in reducing off-leakage bright spots.
Off-leakage bright spots occur in black display. Off-leakage bright spots increase black illuminance (illuminance obtained by measuring the display screen of the display panel with an illuminance meter) (excessive brightness resulting in a whitish screen).
In
Referring to
In the above example, the OEV2 circuit is controlled over an entire field (frame) period without using duty ratio control. However, the present invention is not limited to this. OEV2 circuit control may be performed based on image data only when the duty ratio is 1/1. Alternatively, OEV2 circuit control may be performed when a certain condition—e.g., a duty ratio of 1/1—continues for a certain period.
It has been shown analytically that preferably the OEV2 circuit is operated when the duty ratio is between 1/1 and 1/2 (both inclusive), and more preferably when the duty ratio is between 1/1 and 3/4 (both inclusive). It is also preferable to perform OEV2 circuit control when the duty ratio remains to be between 1/1 and 1/2 (both inclusive) for a period of 10 frames (fields).
Also, screen brightness can be adjusted by operating OEV2. Increasing the duration during which OEV2 is high decreases screen brightness. Decreasing the duration during which OEV2 is high increases screen brightness. The method of adjusting (changing) screen brightness through operation of OEV2 is a major feature of the drive method according to the present invention.
In the above example, off-leakage bright spots are reduced by the application of a turn-off voltage to the gate signal lines 17b. However, this is applicable only when pixels are composed of p-channel transistors as with the pixel configuration in
The methods in
In
Incidentally, in the example in
The above example prevents off-leakage bright spots by applying a turn-off voltage for a predetermined period through operation of the OEV2 circuit when a turn-on voltage continues to be applied to the gate signal line 17b (the gate signal line 17b in
As a measure against off-leakage bright spots in pixel 16 design, the turn-off characteristics of the transistor 11b can be improved. This can be done, for example, by placing a plurality of transistors 11b in series as illustrated in
Incidentally, although examples in
The pixel configuration in
The pixel configuration in
A problem with the pixel configuration in
Description will be given citing the pixel configuration in
Referring to
With the pixel configuration in
Noteworthy are changes in the pixel potential at points A and B. At point A, the gate signal line 17a(2) changes from Vgh to Vgl. At point B, the gate signal line 17a(2) changes from Vgl to Vgh (see Pixel Potential in
At point A, with a change in the potential of the gate signal line 17a from Vgh (turn-off voltage) to Vgl (turn-on voltage), the potential at the gate terminal G of the driver transistor 11a falls. However, since the transistors 11b and 11c are on, the potential (current) of the source signal line 18 is written into the pixel 16 and the capacitor 19 is charged (discharged). As the capacitor 19 is charged (discharged), the driver transistor 11a is programmed to pass a predetermined current (the pixel potential becomes equal to voltage Vb). Since pixel design is such that programming is completed within a period of 1 H, the driver transistor 11a passes the predetermined current at point C.
At point B, the potential of the gate signal line 17a changes from Vgl (turn-on voltage) to Vgh (turn-off voltage). With this voltage change, the potential at the gate terminal G of the driver transistor 11a rises (the pixel potential becomes equal to voltage Vc). When the potential of the gate signal line 17a changes to Vgh (turn-off voltage), the transistors 11b and 11c turn off, cutting off the capacitor 19 terminal from the source signal line 18 and consequently holding the voltage Vc.
Thus, although the pixel potential which causes programming current to flow equals the voltage Vb, the pixel potential actually held equals the voltage Vc.
Consequently, the programming current flowing through the EL element 15 has a value different from the desired one.
A drive method which solves this problem will be described with reference to
In relation to the driver transistor 11a, the potential of the gate signal line 17a changes from Vgl (turn-on voltage) to Vgh (turn-off voltage) and this state is maintained for one frame (field) period. As the gate signal line 17a changes from Vgl (turn-on voltage) to Vgh (turn-off voltage), the potential of the driver transistor 11a shifts to the anode voltage Vdd.
Since the driver transistor 11a is a p-channel transistor, the shift to the anode voltage Vdd works to prevent current flow. Current programming method has a problem of small programming current during black display as described earlier herein. To deal with this problem the present invention uses N-fold pulse driving and the like. In
The present invention can achieve the above effect through a synergy of the following: each pixel driver transistor 11a is a p-channel transistor, the anode voltage is higher than the cathode voltage, the current applied to the source signal line 18 is passed through the driver transistor 11a of the pixel 16 when the WR-side selection signal line (the gate signal line 17a) is low (Vgl), and the pixel 16 is cut off from the source signal line 18 when the WR-side selection signal line (the gate signal line 17a) is high (Vgh). Thus, it is important to use p-channel transistors as the transistors 11b and 11c (see
Also, for proper current programming, it is important to use p-channel transistors for the transistors 11d which cut off the paths to the EL elements 15. Furthermore, the synergy is further enhanced by the fact that the gate terminal G of the switching transistor 11d is held high (Vgh) for a certain period (at least 2 Hs) by N-fold pulse driving, maintaining the drain terminal D of the driver transistor 11a at a relatively high voltage because leakage from the transistor 11b is reduced. Thus, a combination of the configuration in
Next, the drive method in
Incidentally, as described earlier herein, the OEV1 circuit is formed in the output stage of the gate driver circuit 12a (see
The OEV1 circuit, to which the higher voltage is applied once in every 1 H, outputs Vgh (turn-off voltage) to the gate signal line 17a. However, non-selected gate signal lines 17a go through no output change because no turn-off voltage (Vgh) is outputted to them 17a from the beginning In the case of a selected gate signal line 17a, to which a turn-on voltage (Vgl) is applied, a Vgh (turn-off voltage) period is inserted by the application of the higher voltage to the OEV1 circuit.
As the higher voltage is applied to the OEV1 circuit, a turn-off voltage (Vgh) is applied to all the gate signal lines 17a. The source driver circuit 14 absorbs programming current from the source signal line (in the case of the pixel configuration in
A problem with the drive method in
It is possible to hold a voltage approximately equal to the predetermined voltage in the capacitor 19 by lowering the potential of the source signal line 18 through control of the OEV1 circuit, and thereby compensating for the penetration voltage due to the parasitic capacitance 1381. The drive method in
As can be seen from
Referring to
The pixel potential illustrates a capacitor potential of the pixel (3) (voltage waveform of the gate terminal G of the driver transistor 11a). The gate signal lines 17a are scanned in the order: (1)→(2)→(3)→(4)→(5)→ . . . (1)→(2)→ . . . .
Description will be given assuming that the pixel potential is the potential of the pixel (3) and citing the pixel configuration in
At point A in
At point B, the writing of the programming current into the pixel is completed and the pixel potential becomes equal to voltage Va (it is assumed that the voltage Va is a target voltage. See
During the gate-open period t1, the potential of the source signal line 18 falls because the source driver circuit 14 continues to absorb the programming current and after a lapse of the period t1, it becomes equal to the voltage Vc as shown under Source Signal Line Potential (see
At point E, the potential of the gate signal line 17a(3) changes from Vgl (turn-on voltage) to Vgh (turn-off voltage). With this voltage change, the potential at the gate terminal of the driver transistor 11a rises (the pixel potential becomes equal to the voltage Va). When the potential of the gate signal line 17a changes to Vgh (turn-off voltage), the transistors 11b and 11c turn off, cutting off the capacitor 19 terminal from the source signal line 18 and consequently holding the voltage Va. Thus, the pixel potential (3) which causes programming current to flow is held at the voltage Va (this means that penetration voltage has been compensated for).
The drive method in
On the other hand, the penetration voltage caused by the gate signal line 17a is a fixed value. Thus, when the programming current written into pixels carries black display data, only a small amount of compensation is made for penetration voltage through control of the OEV1 circuit. The penetration voltage caused by the gate signal line 17a becomes predominant. This provides more complete black display. In black display, which is characterized by a low luminosity factor, there is no problem even if penetration voltage causes a large deviation from a predetermined value.
When the programming current written into pixels carries white display data, a large amount of compensation is made for penetration voltage through control of the OEV1 circuit. This is because the potential of the source signal line 18 drops in a short time when the OEV1 circuit is high. Thus, by controlling the duration during which the OEV1 circuit is high so that the voltage drop caused through the control of the OEV1 circuit and the penetration voltage caused by the gate signal line 17a will be equal in magnitude, it is possible to eliminate the effect of the penetration voltage completely. Consequently, in white display, penetration voltage can be compensated for completely. For white display, which is characterized by a high luminosity factor, a drive method which cancels out penetration voltage works well.
Thus, the drive method according to the present invention can adjust the amount of compensation for penetration voltage according to image display data.
Incidentally, the duration during which the OEV1 circuit is high may be varied according to image display data. A possible method involves, for example, summing up image display data, determining screen brightness from the sum, and controlling the duration during which the OEV1 circuit is high based on the determined screen brightness.
Incidentally, the amount of compensation for penetration voltage can be changed if the gate-open period t1 and period t2 are made adjustable. This makes it possible to optimize the amount of compensation for penetration voltage according to characteristics of the panel. However, the period t2 does not need to be established exactly.
Although it has been stated in the example in
For example, a conceivable drive method involves not providing a gate-open period when the image data of a pixel row consists almost entirely of black display data, providing a gate-open period when the image data of a pixel row consists almost entirely of white display data, and providing a gate-open period longer than usual when the image data of a pixel row consists entirely of white display data.
There is a correlation between the gate-open period t1 (B in
By switching among modes of B/A, it is possible to adjust the effect of panel penetration voltage (where B is the duration during which the OEV1 circuit is high, that is, the duration during which a selected gate signal line 17a is off while A is 1 H (one horizontal scanning period)). Preferably, B/A is varied according to gradations (see
Also, the mode may be switched by selecting the value of B according to the average gradation level of image data in each pixel row. Also, OEV1 control may be changed above a certain gradation. It is also possible to stop using OEV1 below a certain gradation level.
The above example involves controlling the OEV1 circuit of the gate driver circuit 12, thereby changing the potential of the source signal line 18, and thereby dealing with effects of penetration voltage and the like.
In
For ease of explanation, description will be given with a focus on pixel potential (2). In the 3rd H, a turn-on voltage is applied to the gate signal line 17a(2). Upon the application of the turn-on voltage, the transistors 11b and 11c of the pixel (2) turn on and the current applied to the source signal line 18 is applied to the driver transistor 11a (point A). At point B, the source coupling signal applied to the capacitor signal line 1433 changes from Vsl to Vsh.
Consequently, the source coupling signal couples (penetrates) to the source signal line 18, causing the pixel potential (2) to leap to the voltage Va. However, this leap is cancelled out by the programming current in a short period of time and the pixel potential (2) reaches a target potential Vb at point C at the latest.
At point C, the source coupling signal applied to the capacitor signal line 1433 changes from Vsh to Vsl. Consequently, the source coupling signal couples (penetrates) to the source signal line 18, causing the pixel potential (2) to fall to the voltage Vc. At point C, since a turn-on voltage is applied to the gate signal line 17a(2), the voltage Vc is changed by the programming current. However, the voltage Vc changes little if the time between point C and point D is short.
At point D, since the voltage applied to the gate signal line 17a(2) changes from turn-on voltage to turn-off voltage, the pixel (2) potential shifts to the voltage Vb due to penetration voltage. Consequently, the target voltage Vb is held in the pixel 16. Thus, by coupling the source coupling signal to the source signal line 18, it is possible to compensate for penetration voltage. Needless to say, by varying the amplitude of the source coupling signal, it is possible to adjust a compensation ratio of the penetration voltage.
With the switch 752 closed, the programming current Iw flows into the current output circuit 1461 as illustrated in
In
As illustrated in
Referring to
Common Signal Line (1) represents a voltage waveform of the common signal line 1511 of the pixel (1). Similarly, Common Signal Line (2) represents a voltage waveform of the common signal line 1511 of the pixel (2) and Common Signal Line (3) represents a voltage waveform of the common signal line 1511 of the pixel (3).
Source Signal Line 18 represents a voltage (current) waveform applied to the source signal line. The pixel potential (2) illustrates a capacitor potential of the pixel (2) (voltage waveform of the gate terminal G of the driver transistor 11a). The gate signal lines 17a are scanned in the order: (1)→(2)→(3)→(4)→(5)→ . . . (1)→(2)→ . . . . The common signal lines 1511 are also scanned in the order: (1)→(2)→(3)→(4)→(5)→ . . . (1)→(2)→ . . . . For ease of explanation, description will be given with a focus on the pixel potential of the pixel (2) (the potential at the gate terminal G of the driver transistor 11a). First, image data of all the fields is held in the pixel 16.
At point A, with a change in the potential of the gate signal line 17a from Vgh (turn-off voltage) to Vgl (turn-on voltage), the potential at the gate terminal G of the driver transistor 11a falls (Va→Vc). Since the transistors 11b and 11c are on, the potential (current) of the source signal line 18 is written into the pixel 16 and the capacitor 19 begins to charge (discharge). Incidentally, the potential of the common signal line 1511 is assumed to be Vcl at the start of 1 H (Vcl<Vch).
After a period of Ta from the start of 1 H, the potential of the common signal line 1511 changes from Vcl to Vch (see point B in
At point C, the potential of the gate signal line 17a changes from Vgl (turn-on voltage) to Vgh (turn-off voltage). This voltage change acts as penetration voltage and changes the pixel potential (2) via parasitic capacitance 1381.
With this change in the potential, the pixel potential (2) becomes equal to voltage Vd. At point C, when the potential of the gate signal line 17a changes to Vgh (turn-off voltage), the transistors 11b and 11c turn off, cutting off the capacitor 19 terminal from the source signal line 18 and consequently holding the voltage Vd.
After a lapse of Tb from the completion of 1 H (selection period of pixel (2)), the potential of the common signal line 1511 changes from Vch to Vcl (see point D in
The change in the potential of the common signal line 1511 causes the potential (pixel potential(2)) of the capacitor 19 to shift to the target voltage Vb. Through the above operation, the capacitor 19 holds the voltage Vb so that a predetermined current based on image data flows through the driver transistor 11a.
As can be seen from the above operation, the penetration voltage caused by the parasitic capacitance 1381 and the like is compensated for by the application of a signal to the common signal line 1511. This compensation allows accurate current programming of the pixels 16. Incidentally, it has been stated that the potential of the common signal line 1511 changes from Vch to Vcl after a lapse of Tb from the completion of 1 H.
However, Tb may be either 0 sec. (immediately upon termination of 1 H) or 1 H or longer.
In this way, the drive method according to the present invention changes the potential of the common signal line from Vcl to Vch within a pixel selection period (if the potential is changed before the selection period, there is no problem because current programming is performed within the selection period). Thus, the potential of the common signal line can be changed from Vcl to Vch before the current programming of the given pixel is finished. After the pixel selection period (or immediately upon termination of the selection period), the drive method changes the potential of the common signal line from Vch to Vcl.
Incidentally, the amplitudes (Vch and Vcl) of the common signal line 1511 are configured to be changeable by a regulator of a voltage generator circuit (not shown). The configuration and operation of the common driver circuit 1512 is the same as or similar to those of the gate driver circuit 12, and thus description thereof will be omitted. Also, the other part of the operation is the same as that shown in
In
Referring to
Source Signal Line 18 represents a voltage (current) waveform applied to the source signal line. The pixel potential (2) illustrates a capacitor potential of the pixel (2) (voltage waveform of the gate terminal G of the driver transistor 11a). The gate signal lines 17a are scanned in the order: (1)→(2)→(3)→(4)→(5)→ . . . (1)→(2)→ . . . .
For ease of explanation, description will be given with a focus on the pixel potential of the pixel (2) (the potential at the gate terminal G of the driver transistor 11a). First, image data of all the fields is held in the pixel 16. In the example in
At point A, with a change in the potential of the gate signal line 17a(1) in the preceding stage from Vgh1 (turn-off voltage) to Vgl (turn-on voltage), the potential of the capacitor 19 of the pixel (2) changes (the pixel potential changes from Ve to Vd). Consequently, the potential at the gate terminal G of the driver transistor 11a falls.
At point B, with a change in the potential of the gate signal line 17a of the pixel (2) from Vgh1 (turn-off voltage) to Vgl (turn-on voltage), the pixel potential changes. Since the transistors 11b and 11c are on, the potential (current) of the source signal line 18 is written into the pixel 16 and the capacitor 19 begins to charge (discharge). Within a selection period of 1 H, the target voltage Vb is reached.
Through the above operation, the capacitor 19 is set such that a predetermined current based on image data flows through the driver transistor 11a.
At point C, the potential of the gate signal line 17a(2) changes from Vgl (turn-on voltage) to Vgh2 (turn-off voltage). This voltage change acts as penetration voltage and changes the pixel potential (2) via parasitic capacitance 1381. With this change in the potential, the pixel potential (2) becomes equal to voltage Vc. At point C, when the potential of the gate signal line 17a changes to Vgh (turn-off voltage), the transistors 11b and 11c turn off, cutting off the capacitor 19 terminal from the source signal line 18 and consequently holding the voltage Vc.
After a lapse of 1 H (point D in
As can be seen from the above operation, the penetration voltage caused by the parasitic capacitance 1381 and the like is compensated for by the application of three voltages (Vgh1, Vgh2, and Vgl) to the gate signal lines 17a. This compensation allows accurate current programming of the pixels 16. Incidentally, although it has been stated that the potential of the gate signal line 17a(2) changes from Vgh2 to Vgh1 after a lapse of 1 H (point D in
Although in
At point A, with a change in the potential of the gate signal line 17a(1) in the stage before the preceding stage from Vgh1 (turn-off voltage) to Vgl (turn-on voltage), the potential of the capacitor 19 of the pixel (3) changes (the pixel potential changes from Va to Ve). Consequently, the potential at the gate terminal G of the driver transistor 11a falls.
At point B, with a change in the potential of the gate signal line 17a(1) in the stage before the preceding stage from Vgl (turn-on voltage) to Vgh2 (turn-off voltage), the potential of the capacitor 19 of the pixel (3) changes (the pixel potential changes from Ve to Va). Consequently, the potential at the gate terminal G of the driver transistor 11a rises.
At point C, with a change in the potential of the gate signal line 17a(3) from Vgh1 (turn-off voltage) to Vgl (turn-on voltage), the potential of the capacitor 19 of the pixel (3) changes. Since the transistors 11b and 11c are on, the potential (current) of the source signal line 18 is written into the pixel 16 and the capacitor 19 begins to charge (discharge). Within a selection period of 1 H, the target voltage Vc is reached.
Through the above operation, the capacitor 19 is set such that a predetermined current based on image data flows through the driver transistor 11a.
At point D, the potential of the gate signal line 17a(3) changes from Vgl (turn-on voltage) to Vgh2 (turn-off voltage). This voltage change acts as penetration voltage and changes the pixel potential (3) via parasitic capacitance 1381. With this change in the potential, the pixel potential (3) becomes equal to voltage Vb. At point C, when the potential of the gate signal line 17a changes to Vgh (turn-off voltage), the transistors 11b and 11c turn off, cutting off the capacitor 19 terminal from the source signal line 18 and consequently holding the voltage Vb.
After a lapse of 1 H (point D in
As can be seen from the above operation, the penetration voltage caused by the parasitic capacitance 1381 and the like is compensated for by the application of three voltages (Vgh1, Vgh2, and Vgl) to the gate signal lines 17a. This compensation allows accurate current programming of the pixels 16.
The above example compensates for the effect of penetration voltage through improvement or invention of a drive system. Penetration voltage can also be suppressed using pixel 16 configuration. In
As the transistor 11b is composed of the p-channel transistor and n-channel transistor as illustrated in
Thus, by using the pixel configuration shown in
The above example has been described with a focus on the gate signal lines 17a (WR-side selection signal lines). Now, a drive method of gate signal lines 17b (EL-side selection signal lines) will be described additionally. The gate signal lines 17b (EL-side selection signal lines) are signal lines which control the current passed through EL elements 15. In
Thus, the control method of the gate signal lines 17b (EL-side selection signal lines) described below additionally can be restated as a method of controlling the timing or time to pass current through the EL elements 15. For ease of explanation, a gate signal line 17b (EL-side selection signal line) will be cited as an example in the following description. Needless to say, the items described below apply to all the drive systems according to the present invention.
It has been stated with reference to
However, the present invention is not limited to this. The duration of the conduction period may be less than 1 H (½ H in
In
In the second field which follows the first field, a turn-on voltage little shorter than 1 H is applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows. A turn-on voltage is applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows for a very short period. The duration T1 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in even-numbered pixel rows plus the duration T2 of the turn-on voltage applied to the gate signal lines 17b (EL-side selection signal lines) in odd-numbered pixel rows is designed to be 1 H.
The sum duration of turn-on voltage applications to gate signal lines 17b in a plurality of pixel rows may be designed to be constant. Alternatively, the illumination time of each EL element 15 in each pixel row in each field may be designed to be constant.
Referring to
Incidentally, in the example in
By adjusting the duration of application of the turn-on voltage to the gate signal line 17B (EL-side selection signal line), it is possible to adjust the brightness of the display screen 50 linearly. This can be done easily through control of the OEV2 circuit. Referring to
As shown in
Also, it is possible to allow selection from different drive modes: a drive mode for controlling non-display areas 52 and display areas 53 regularly as illustrated in
In
For example, when driving the source signal lines 18 with one source driver IC 14, there are 176 outputs (because the source signal lines require a total of 176 outputs for R, G, and B). Here it is assumed that N=16 and M=11. Thus, 16×11=176 and the 176 outputs can be covered. In this way, by using a multiple of 8 or 16 for N or M, it becomes easier to lay out and design the current sources of the driver IC.
The current-driven source driver IC (circuit) 14 employing the multi-stage current mirror circuit according to the present invention can absorb variations in transistor characteristics because it has the second-stage current sources 1842 in between instead of copying the current value of the first-stage current source 1841 directly to N×M third-stage current sources 1843 using the current mirror circuit.
In particular, the present invention is characterized in that a first-stage current mirror circuit (current source 1841) and second-stage current mirror circuits (current sources 1842) are placed close to each other. If a first-stage current source 1841 are connected with third-stage current sources 1843 (i.e., in the case of two-stage current mirror circuit), the second-stage current sources 1843 connected to the first-stage current source are large in number, making it impossible to place the first-stage current source 1841 and third-stage current sources 1843 close to each other.
The source driver circuit 14 according to the present invention copies the current value of the first-stage current mirror circuit (current source 1841) to the second-stage current mirror circuits (current sources 1842), and the current values of the second-stage current mirror circuits (current sources 1842) to the third-stage current mirror circuits (current sources 1842). With this configuration, the second-stage current mirror circuits (current sources 1842) connected to the first-stage current mirror circuit (current source 1841) are small in number. Thus, the first-stage current mirror circuit (current source 1841) and second-stage current mirror circuits (current sources 1842) can be placed close to each other.
If transistors composing the current mirror circuits can be placed close to each other, naturally variations in the transistors are reduced, and so are variations in current values.
The number of the third-stage current mirror circuits (current sources 1843) connected to the second-stage current mirror circuits (current sources 1842) are reduced as well. Consequently, the second-stage current mirror circuits (current sources 1842) and third-stage current mirror circuits (current sources 1843) can be placed close to each other.
That is, transistors in current receiving parts of the first-stage current mirror circuit (current source 1841), second-stage current mirror circuits (current sources 1842), and third-stage current mirror circuits (current sources 1843) can be placed close to each other on the whole. In this way, transistors composing the current mirror circuits can be placed close to each other, reducing variations in the transistors and greatly reducing variations in current signals from output terminals (high precision).
In the present invention, the terms “current sources 1841, 1842, and 1843” and “current mirror circuits” are used interchangeably. That is, current sources are a basic construct of the present invention and the current sources are embodied into current mirror circuits.
Incidentally, the transistors composing the source driver IC (circuit) 14 according to the present invention are not limited to a MOS type and may be a bipolar type. Also, they are not limited to silicon semiconductors and may be gallium arsenide semiconductors. Also, they may be germanium semiconductors. Alternatively, they may be formed directly on a substrate using low-temperature polysilicon technology, other polysilicon technology, or amorphous silicon technology.
Sixty-four (64) gradations require 1 D0-bit unit transistor 1854, two D1-bit unit transistors 1854, four D2-bit unit transistors 1854, eight D3-bit unit transistors 1854, sixteen D4-bit unit transistors 1854, and thirty-two D5-bit unit transistors 1854 for a total of 63 unit transistors 1854. Thus, the present invention produces one output using as many unit transistors 1854 as the number of gradations (64 gradations in this example) minus 1. Incidentally, even if one unit transistor is divided into a plurality of sub-unit transistors, this simply means that a unit transistor is divided into sub-unit transistors, and makes no difference in the fact that the present invention uses as many unit transistors as the number of gradations minus 1.
In
For example, when a D1 input terminal is high (positive logic), a switch 1851b is closed. Then, current flows to two current sources (single-unit) 1854 composing a current mirror. The current flows through the internal wiring 1853 in the IC 14. Since the internal wiring 1853 is connected to the source signal line 18 via a terminal electrode of the IC 14, the current flowing through internal wiring 1853 provides a programming current for the pixels 16.
The same applies to the other switches 1851. When a D2 input terminal is high (positive logic), a switch 1851c is closed. Then, current flows to four current sources (single-unit) 1854 composing a current mirror. When a D5 input terminal is high (positive logic), a switch 1851f is closed. Then, current flows to 32 (thirty-two) current sources (single-unit) 1854 composing a current mirror.
In this way, based on external data (D0 to D5), current flows to the corresponding current sources (single-unit). That is, current flows to 0 to 63 current sources (single-unit) depending on the data.
Incidentally, for ease of explanation, it is assumed that there are 63 current sources for a 6-bit configuration, but this is not restrictive. In the case of 8-bit configuration, 255 unit transistors 1854 can be formed (placed). For a 4-bit configuration, 15 unit transistors 1854 can be formed (placed). The transistors 1854 constituting the unit current sources have a channel width W and channel length L. The use of equal transistors makes it possible to construct output stages with small variations.
Besides, not all the unit transistors 1854 need to pass equal current. For example, individual unit transistors 1854 may be weighted. For example a current output circuit may be constructed using a mixture of single-unit unit transistors 1854, double-sized unit transistors 1854, quadruple-sized unit transistors 1854, etc. However, if unit transistors 1854 are weighted, the weighted current sources may not provide the right proportions, resulting in variations. Thus, even when using weighting, it is preferable to construct each current source from transistors each of which corresponds to a single-unit current source.
The unit transistor 1854 should be equal to or larger than a certain size. The smaller the transistor size, the larger the variations in output current. The size of a transistor 1854 is given by the channel length L multiplied by the channel width W. For example, if W=3 μm and L=4 μm, the size of the unit transistor 1854 constituting a unit current source is W×L=12 square μm. It is believed that crystal boundary conditions of silicon wafers have something to do with the fact that a smaller transistor size results in larger variations. Thus, variations in output current of transistors are small when each transistor is formed across a plurality of crystal boundaries.
Preferably, the unit transistor 1854 is an n-channel transistor. P-channel unit transistors have 1.5 times as large variations in output current as n-channel unit transistors.
Since it is preferable that the unit transistors 1854 of the source driver IC 14 are n-channel transistors, the source driver IC 14 draws programming current from the pixels 16. Thus, the driver transistors 11a of the pixels 16 are p-channel transistors. The switching transistor 11d in
Thus, the configuration in which the unit transistor 1854 in the output stage of the source driver IC (circuit) 14 is an n-channel transistor and the driver transistor 11a of the pixel 16 is a p-channel transistor is characteristic of the present invention. Incidentally, it is preferable that all the transistors 11 (transistors 11a, 11b, 11c, and 11d) composing the pixel 16 are p-channel transistors. Since this can eliminate the process of forming n-channel transistors, it is possible to achieve low costs and high yields.
Incidentally, although it has been stated that the unit transistor 1854 is formed in the IC 14, this is not restrictive. The source driver circuit 14 may be formed by low-temperature polysilicon technology. In that case again, it is preferable that the unit transistors 1854 in the source driver circuit 14 are n-channel transistors.
P-channel transistors are used as the transistors 11 of pixels 16 and for the gate driver circuits 12. This makes it possible to reduce the cost of the board 71. However, in the source driver circuit 14, the unit transistors 1854 must be n-channel transistors. Thus, the source driver circuit 14 cannot be formed directly on a board 71. Thus, the source driver circuit 14 is made of a silicon chip and the like separately and mounted on the board 71. In short, the present invention is configured to mount the source driver IC 14 (means of outputting programming current as video signals) externally.
If the gate driver circuits 12 are constructed from p-channel transistors, it becomes easy to hold (maintain) the turn-off voltage (Vgh). As the driver transistors 11a, 11b, and 11c of the pixels 16 can be held readily at the turn-off potential, the gate driver circuits 12 match well, and achieve synergy, with the pixel configuration according to the present invention consisting of p-channel transistors. Incidentally, although it has been stated that the source driver circuit 14 is made of a silicon chip, this is not restrictive. For example, a large number of source driver circuits may be formed on a glass substrate simultaneously using low-temperature polysilicon technology or the like, cut off into chips, and mounted on a board 71. Incidentally, although it has been stated that a source driver circuit is mounted on a board 71, this is not restrictive. Any form may be adopted as long as the output terminals of the source driver circuit 14 are connected to the source signal lines 18 on the board 71. For example, the source driver circuit 14 may be connected to the source signal lines 18 using TAB technology. By forming a source driver circuit 14 on a silicon chip separately, it is possible to reduce variations in output current and achieve proper image display as well as to reduce costs.
The configuration in which p-channel transistors are used as selection transistors of pixels 16 and for gate driver circuits is not limited to organic EL or other self-luminous devices (display panels or display apparatus). For example, it is also applicable to liquid crystal display devices and FEDs (field emission displays).
If the switching transistors 11b and 11c of a pixel 16 are p-channel transistors, the pixel 16 becomes selected at Vgh, and becomes deselected at Vgl. As described earlier, when the gate signal line 17a changes from on (Vgl) to off (Vgh), voltage penetrates (penetration voltage). If the driver transistor 11a of the pixel 16 is a p-channel transistor, the penetration voltage more tightly restricts the flow of current through the transistor 11a in black display mode. This makes it possible to achieve a proper black display. The problem with the current-driven system is that it is difficult to achieve a black display.
According to the present invention, if p-channel transistors are used for the gate driver circuits 12, the turn-on voltage corresponds to Vgh. Thus, the gate driver circuits 12 match well with the pixels 16 constructed from p-channel transistors. Also, to improve black display, it is important that the programming current Iw flows from the anode voltage Vdd to the unit transistors 1854 of the source driver circuit 14 via the driver transistors 11a and source signal lines 18, as is the case with the pixel 16 configuration shown in
Incidentally, dense placement means placing the first current source 1841 and the second current sources 1842 (the current or voltage output and current or voltage input) at least within a distance of 8 mm. More preferably, they are placed within 5 mm. It has been shown analytically that when placed at this density, the current sources can fit into a silicon chip with little difference in transistor characteristics (Vt and mobility (μ)). Similarly, the second current sources 1842 and third current sources 1843 (the current output and current input) are placed at least within a distance of 8 mm. More preferably, they are placed within 5 mm. Needless to say, the above items also apply to other examples of the present invention.
The current or voltage output and current or voltage input mean the following relationships. In the case of voltage-based delivery shown in
Incidentally, although it is assumed in
Similarly, although it is assumed that there is one transistor 1842a, this is not restrictive. For example, it is also possible to form a plurality of small sub-transistors 1842a and connect the gate terminals of the transistors 1842a with the gate terminal of the transistor 1841. By connecting the plurality of small transistors 1842a in parallel, it is possible to reduce variations of the transistor 1842a.
Thus, according to the present invention, the following configurations can be illustrated: a configuration in which one transistor 1841 is connected with a plurality of transistors 1842a, a configuration in which a plurality of transistors 1841 are connected with one transistor 1842a, and a configuration in which a plurality of transistors 1841 are connected with a plurality of transistors 1842a. These examples will be described in more detail below.
The above items also apply to a configuration of transistors 1843a and 1843b in
The above items also apply to relationship between transistors 1842a and 1842b in
Although it has been stated that the source driver IC 14 consists of a silicon chip, this is not restrictive. The source driver IC 14 may be constructed of another semiconductor chip formed on a gallium substrate or germanium substrate. Also, the unit transistor 1854 may be a bipolar transistor, CMOS transistor, FET, Bi-CMOS transistor, or DMOS transistor. However, in terms of reducing variations in the output of the unit transistor 1854, preferably a CMOS transistor is used for the unit transistor 1854.
Preferably, the unit transistor 1854 is an N-channel transistor. The unit transistor consisting of a P-channel transistor has 1.5 times larger output variations than the unit transistor consisting of an N-channel transistor.
Since it is preferable that the unit transistor 1854 of the source driver IC 14 is an N-channel transistor, the programming current of the source driver IC 14 is a current drawn from the pixel 16. Thus, the driver transistor 11a of the pixel 16 is a P-channel transistor. The switching transistor 11d in
0657-d
Thus, the configuration in which the unit transistor 1854 in the output stage of the source driver IC (circuit) 14 is an N-channel transistor and the driver transistor 11a of the pixel 16 is a P-channel transistor is characteristic of the present invention. Incidentally, it is preferable that all the transistors (transistors 11a, 11b, 11c, and 11d) composing the pixel 16 are P-channel transistors. This eliminates the process of forming N-channel transistors, resulting in low costs and high yields.
Incidentally, although it has been stated that the unit transistor 1854 is formed in the IC 14, this is not restrictive. The source driver circuit 14 may be formed by low-temperature polysilicon technology. In that case again, it is preferable that the unit transistors 1854 in the source driver circuit 14 are N-channel transistors.
In
In
In
Incidentally, although this example of the present invention focuses on relationship between the first current source and second current source for ease of explanation or understanding, this is not restrictive and it goes without saying that this example also applies (can be applied) to relationship between the second current source and third current source as well as relationship between other current sources.
In the layout configuration of the current mirror circuit of the voltage-based delivery type shown in
In contrast, in the layout configuration of the current mirror circuit of the current-based delivery type shown in
In view of the above circumstances, it is preferable to use a layout configuration of the current-based delivery type instead of the voltage-based delivery type for the circuit configuration of the multi-stage current mirror circuit according to the present invention (the source driver IC (circuit) 14 of the current-based delivery type according to the present invention) in terms of reduced variations. Needless to say the above example can be applied to other examples of the present invention.
Incidentally, although delivery from the first-stage current source to the second-stage current source has been cited for the sake of explanation, the same applies to delivery from the second-stage current source to the third-stage current source, delivery from the third-stage current source to the fourth-stage current source, and so on. Also, it goes without saying that the present invention may adopt a single-stage current source configuration.
In
The gate voltage of the first-stage current source constituted of the transistor 1841 is applied to the gate of the N-channel transistor 1842a of the adjacent second-stage current source, and the current consequently flowing through the transistor is delivered to the P-channel transistor 1842b of the second-stage current source. Also, the gate voltage of the P-channel transistor 1842b of the second-stage current source is applied to the gate of the N-channel transistor 1843a of the adjacent third-stage current source, and the current consequently flowing through the transistor is delivered to the N-channel transistor 1843b of the third-stage current source. A large number of N-channel unit transistors 1854 are formed (placed) at the gate of the N-channel transistor 1843b of the third-stage current source according to the required bit count as illustrated in
The display panel according to the present invention will be described below. In the display panel according to the present invention, pixels and the gate driver circuits 12 are formed using polysilicon technology. The source driver circuit 14 is constructed from an IC chip fabricated from a silicon wafer. Thus, the source driver circuit 14 is a source driver IC. The source driver IC 14 is mounted on the array board 71 using COG technology. Thus, there is a space under the source driver IC 14. Anode wiring is formed in this space (on a surface of the array board).
As illustrated in
A common anode line 833 is formed or placed on the output side of the IC 14. Anode wires 834 branch off from the common anode line 833. There are 528 (=176×RGB) anode wires 834 in a QCIF panel. The voltage Vdd (anode voltage) illustrated in
A current of up to 200 μA flows through one anode wire 834 if the EL elements 15 are made of low molecular weight-material. Therefore, a current of approximately 100 mA (200 μA×528) flows through the common anode line 833.
To reduce voltage drops in the common anode line 833 to within 0.2 V, it is necessary to reduce the resistance value of the largest current path to 2Ω or less (assuming that a current of 100 mA flows).
The anode coupling line 835 is formed (placed) under the IC chip 14. Needless to say, its line width should be as thick as possible to reduce resistance. Besides, preferably the anode coupling line 835 is provided with a light shielding function. This is intended to prevent malfunctions caused by a photoconductive phenomenon in the source driver IC 14, which in turn would be caused by light emitted by EL elements 15. Needless to say, if the anode coupling line 835 is formed of a metal material to a required film thickness, it will have a light shielding function.
If the anode coupling line 835 cannot be made thick enough or is made of transparent material such as ITO, light-absorbing film or light-reflecting film is stacked in a single or multiple layers under the IC chip 14 and on the anode coupling line 835 (basically, on the surface of the array board 71). The anode coupling line 835 does not need to shield light perfectly.
It may have openings. Also, it may have diffraction effect or scattering effect. Also, light-shielding film consisting of multilayer optical interference film may be formed or placed by stacking on the anode coupling line 835.
Of course, a reflector plate (sheet) or light-absorbing plate (sheet) made of a metal foil, plate, or sheet may be placed, inserted or formed in the space between the array board 71 and IC chip 14. Needless to say, it is also possible to place, insert or form a reflector plate (sheet) or light-absorbing plate (sheet) made of a foil, plate or sheet of organic or inorganic material rather than a metal foil.
Alternatively, light-absorbing material or light-reflecting material in a gel or liquid state may be inserted or formed in the space between the array board 71 and IC chip 14.
Preferably, light-absorbing material or light-reflecting material in the gel or liquid state are solidified by heating or by exposure to light. Incidentally, it is assumed for ease of explanation that the anode coupling line 835 is made of a light-shielding film (light-reflecting film).
The anode coupling line 835 is formed on the surface of the array board 71 (not limited to the surface). The idea of a light-shielding film or light-reflecting film can be satisfied if light does not reach the rear surface of the IC chip 14. Thus, needless to say, the anode coupling line 835 and the like may be formed on an inner surface or inner layer of the array board 71. Alternatively, the anode coupling line 835 (an arrangement or structure which functions as a reflecting film or light-shielding film) may be formed on the rear surface of the array board 71 as long as it can prevent or reduce entrance of light into the IC 14.
Although it has been stated with reference to
When forming the source driver circuit 14 directly on the array board 71 (driver construction by low-temperature polysilicon technology, high-temperature polysilicon technology, solid-phase growth technology, or amorphous silicon technology), the source driver circuit 14 can be formed (placed) on the light-shielding film, light-absorbing film, or reflecting film which is formed on the array board 71.
A large number of transistor elements, such as current output circuit 1461, which pass minute current are formed on the IC chip 14 (in
To deal with this problem, the present invention constructs the anode coupling line 835 on the array board 71 and uses it as a light-shielding film. The formation area of the anode coupling line 835 covers the circuit forming section 1461 as illustrated in
To reduce voltage drops in the common anode lines 833 and anode wires 834, it is recommended to form a common anode line 833a on the upper side of the display screen 50, form a common anode line 833b on the lower side of the display screen 50, and short-circuit the anode wires 834 at the top and bottom, as illustrated in
It is also preferable to place source driver circuits 14 at the top and bottom of the screen 50 as illustrated in
In the case of organic EL or other self-luminous elements, light produced by the EL elements 15 is reflected diffusely within the array board 71, causing intense light to be radiated from places other than the display area 50. To prevent or reduce the diffusely reflected light, it is preferable that light-absorbing films 1011 are formed in ineffective areas which do not pass light effective for image display. The light-absorbing films are formed on an outer surface of a sealing lid 85, inner surface of the sealing lid 85, side face of the array board 71, area on the board other than the image display area (light-absorbing film 1011b), etc. Incidentally, instead of light-absorbing films, light-absorbing sheets or light-absorbing walls may be installed. Besides, the concept of light absorption also includes schemes or structures which diverge light by scattering it. In a broader sense, it also includes schemes or structures which confine light through reflection.
Possible materials for light-absorbing films include, for example, organic material such as acrylic resin containing carbon, organic resin with a black pigment dispersed in it, and gelatin or casein colored with a black acidic dye as with a color filter. Besides, they also include a fluorine-based pigment which singly develops a black color as well as green and red pigments which develop a black color when mixed. Furthermore, they also include PrMnO3 film formed by sputtering, phthalocyanine film formed by plasma polymerization, etc.
Anode voltage Vdd has its output voltage adjusted to a resistor 945b. Vss denotes cathode voltage. One of two voltages can be output selectively as the cathode voltage Vss as illustrated in
The switch 951 is operated according to output from a temperature sensor 952. When panel temperature is low, −9(V) is selected as the voltage Vss. When the panel temperature is equal to or higher than a certain level, −6(V) is selected.
This is because EL elements 15 have temperature dependence and terminal voltage of the EL elements 15 becomes higher on a low temperature side. Incidentally, although it has been stated with reference to
By allowing a voltage to be selected from a plurality of voltages based on panel temperature as shown in
The turn-off voltage Vgh of the gate driver circuit 12 is set to equal to or higher than the voltage Vdd. Preferably, Vdd+0.5 (V)<Vgh<Vdd+2.5 (V) is satisfied. The turn-on voltage Vgl may be brought to coincide with Vss, but preferably Vss (V)<Vgl<−0.5 (V) is satisfied. The voltage settings above are important when the pixel configuration in
Although organic EL display apparatus are described herein, the display panels used for the organic EL display apparatus are not limited to organic EL display panels. For example, as illustrated in
Reference numeral 1001 denotes connector resin such as ACF. A signal from source driver circuit 14 is transmitted to the source signal line 18 on the array board 71b via the source signal line 18 on the array board 71a and the connector resin 1001.
Reference numeral 1004 denotes a polarizing plate or circular polarizing plate. A dispersing agent 1003 is placed or formed between the polarizing plates 1004 and array boards 71. The dispersing agent 1003 also functions as an adhesive which bonds the polarizing plates 1004 and array boards 71 together. The dispersing agent 1003 may be, for example, an acrylic adhesive containing fine-powdered titanium oxide or an acrylic adhesive containing fine-powdered calcium carbonate The dispersing agent 1003 improves the efficiency of extracting light produced by the EL elements 15.
The control IC 1022 converts serial video data into parallel data and inputs the resulting data in the source driver ICs 14. Also, it has the function of decoding panel control data and controlling the source driver circuits 14 and the like.
Serial data 1031 is inputted in the control IC 1022 via wiring on the flexible board 1021. The control IC 1022 performs serial/parallel data conversion to produce parallel video data 1032 and gate driver circuit control data 1033.
As illustrated in
Cushioning members (cushioning bumps) 1063 are formed on the printed board 1062 to prevent the printed board 1062 from coming into contact with the board 71, damaging the thin encapsulation film 111 (
Next, description will be given of examples of display devices according to the present invention which run the drive systems according to the present invention.
The key 572 may be configured to switch among color modes as follows: pressing it once enters 8-color display mode, pressing it again enters 256-color display mode, and pressing it again enters 4,096-color display mode. The key is a toggle switch which switch among color display modes each time it is pressed. Incidentally, a display color change key may be provided separately. In that case, three (or more) keys 572 are needed.
In addition to a push switch, the key 572 may be a slide switch or other mechanical switch. Speech recognition may also be used for switching. For example, the switch may be configured such that display colors on the display screen 50 of the display panel will change as the user enters a color change command by speaking such as “high-definition display,” “256-color mode,” or “low-color display mode” into the phone. This can be implemented easily using existing speech recognition technology.
Also, display colors may be switched electrically. It is also possible to employ a touch panel which allows the user to make a selection by touching a menu presented on the display part 21 of the display panel. Besides, display colors may be switched based on the number of times the switch is pressed or based on a rotation or direction as is the case with a click ball.
A key which changes frame rate or a key which switches between moving pictures and still pictures many be used in place of the display color switch key 572. A key may switch two or more items at the same time: for example, among frame rates and between moving pictures and still pictures. Also, the key may be configured to change the frame rate gradually (continuously) when pressed and held. For that, among a capacitor C and a resistor R of an oscillator, the resistor R can be made variable or replaced with an electronic regulator. Alternatively, a trimmer capacitor may be used as a capacitor C of the oscillator. Such a key can also be implemented by forming a plurality of capacitors in a semiconductor chip, selecting one or more capacitors, and connecting the capacitors in parallel.
Incidentally, the technical idea of changing frame rates according to display color and the like is not limited to cell phones, but is widely applicable to devices with a display screen such as palmtop computers, notebook personal computers, desktop personal computers, and portable watches.
The cell phone according to the present invention described with reference to
Data picked up by the CCD camera can be displayed on the display screen 50. The image data of the CCD camera can be switched among 24-bit (16,700,000 colors), 18-bit (260,000 colors), 16-bit (65,000 colors), 12-bit (4,096 colors), and 8-bit (256 colors) using input from keys 572.
Inner surfaces of a body 573 are dark- or black-colored. This is to prevent stray light emitted from an EL display panel (EL display apparatus) 574 from being reflected diffusely inside the body 573 and lowering display contrast. A phase plate (λ/4) 108, polarizing plate 109, and the like are placed on an exit side of the display panel. This has also been described with reference to
An eye ring 581 is fitted with a magnifying lens 582. The observer focuses on a display image 50 on the display panel 574 by adjusting the position of the eye ring 581 in the body 573.
If a convex lens 583 is placed on the exit side of the display panel 574 as required, principal rays entering the magnifying lens 582 can be made to converge. This makes it possible to reduce the diameter of the magnifying lens 582, and thus reduce the size of the viewfinder.
The EL display panel according to the present invention is also used as a display monitor. The display part 50 can pivot freely on a point of support 591. The display part 50 is stored in a storage compartment 593 when not in use.
A switch 594 is a changeover switch or control switch and performs the following functions. The switch 594 is a display mode changeover switch. The switch 594 is also suitable for cell phones and the like. Now the display mode changeover switch 594 will be described.
The drive methods according to the present invention include the one that passes an N times larger current through EL elements 15 to illuminate them for a period equal to 1/M of 1F. By varying this illumination period, it is possible to change brightness digitally. For example, designating that N=4, a four times larger current is passed through the EL elements 15. If the illumination period is 1/M, by switching M among 1, 2, 3, and 4, it is possible to vary brightness from 1 to 4 times. Incidentally, M may be switched among 1, 1.5, 2, 3, 4, 5, 6, and so on.
The switching operation described above is used for cell phones, which display the display screen 50 very brightly at power-on and reduce display brightness after a certain period to save power. It can also be used to allow the user to set a desired brightness. For example, the brightness of the screen is increased greatly outdoors. This is because the screen cannot be seen at all outdoors due to bright surroundings. However, the EL elements 15 deteriorate quickly under conditions of continuous display at high brightness. Thus, the screen 50 is designed to return to normal brightness in a short period of time if it is displayed very brightly. A button which can be pressed to increase display brightness should be provided, in case the user wants to display the screen 50 at high brightness again.
Thus, it is preferable that the user can change display brightness with the button switch 1594, that the display brightness can be changed automatically according to mode settings, or that the display brightness can be changed automatically by detecting the brightness of extraneous light. Preferably, display brightness settings such as 50%, 60%, 80%, etc. are available to the user.
Preferably, the display screen 50 employs Gaussian display. That is, the center of the display screen 50 is bright and the perimeter is relatively dark. Visually, if the center is bright, the display screen 50 seems to be bright even if the perimeter is dark. According to subjective evaluation, as long as the perimeter is at least 70% as bright as the center, there is not much difference. Even if the brightness of the perimeter is reduced to 50%, there is almost no problem. The self-luminous display panel according to the present invention generates a Gaussian distribution from top to bottom of the screen using the N-fold pulse driving described above (a method which passes an N times larger current through EL elements 15 to illuminate them for a period equal to 1/M of 1F).
Specifically, the value of M is increased in upper and lower parts of the screen and decreased in the center of the screen. This is accomplished by modulating the operating speed of a shift register of the gate driver circuits 12. The brightness at the left and right of the screen is modulated by multiplying video data by table data. By reducing peripheral brightness (at an angle of view of 0.9) to 50% through the above operation, it is possible to reduce power consumption by 20% compared to brightness of 100%. By reducing peripheral brightness (at an angle of view of 0.9) to 70%, it is possible to reduce power consumption by 15% compared to brightness of 100%.
Preferably a changeover switch is provided to enable and disable the Gaussian display. This is because the perimeter of the screen cannot be seen at all outdoors if the Gaussian display is used. Thus, it is preferable that the user can change display brightness with the button switch, that the display brightness can be changed automatically according to mode settings, or that the display brightness can be changed automatically by detecting the brightness of extraneous light. Preferably, display brightness settings such as 50%, 60%, 80%, etc. are available to the user.
Liquid crystal display panels generate a fixed Gaussian distribution using a backlight. Thus, they cannot enable and disable the Gaussian distribution. The capability to enable and disable Gaussian distribution is peculiar to self-luminous display devices.
A fixed frame rate may cause interference with illumination of an indoor fluorescent lamp or the like, resulting in flickering. Specifically, if the EL elements 15 operate on 60-Hz alternating current, a fluorescent lamp illuminating on 60-Hz alternating current may cause subtle interference, making it look as if the screen were flickering slowly. To avoid this situation, the frame rate can be changed. The present invention has a capability to change frame rates. Also, it allows the value of N or M to be changed in N-fold pulse driving (a method which passes an N times larger current through EL elements 15 to illuminate them for a period equal to 1/M of 1F).
The above capabilities are implemented by way of the switch 594. The switch 594 switches among the above capabilities when pressed more than once, following a menu on the screen 50.
Incidentally, the above items are not limited to cell phones. Needless to say, they are applicable to television sets, monitors, etc. Also, it is preferable to provide icons on the display screen to allow the user to know at a glance what display mode he/she is in. The above items similarly apply to the following.
The EL display apparatus and the like according to this embodiment can be applied not only to video cameras, but also to digital cameras such as the one shown in
The display panel described above has a relatively small display area. However, with a display area of 30 inches or larger, the display screen 50 tends to flex. To deal with this situation, the present invention puts the display panel in a frame 611 and attaches a fitting 614 so that the frame 611 can be suspended as shown in
A large screen size increases the weight of the display panel. As a measure against this situation, the display panel is mounted on a stand 613, to which a plurality of legs 612 are attached to support the weight of the display panel.
The legs 612 can be moved from side to side as indicated by A. Also, they can be contracted as indicated by B. Thus, the display apparatus can be installed even in a small space.
A television set in
A space is formed between the protective film and display panel by spraying beads or the like. Fine projections are formed on the rear face of the protective film to maintain the space between the protective film and display panel. The space prevents impacts from being transmitted from the protective film to the display panel.
Also, it is useful to inject an optical coupling agent into the space between the protective film and display panel. The optical coupling agent may be a liquid such as alcohol or ethylene glycol, a gel such as acrylic resin, or a solid resin such as epoxy. The optical coupling agent can prevent interfacial reflection and function as a cushioning material.
The protective film may be, for example, a polycarbonate film (plate), polypropylene film (plate), acrylic film (plate), polyester film (plate), PVA film (plate), etc. Besides, it goes without saying that an engineering resin film (ABS, etc.) may be used. Also, it may be made of an inorganic material such as tempered glass. Instead of using a protective film, the surface of the display panel may be coated with epoxy resin, phenolic resin, and acrylic resin 0.5 mm to 2.0 mm thick (both inclusive) to produce a similar effect. Also, it is useful to emboss surfaces of the resin.
It is also useful to coat surfaces of the protective film or coating material with fluorine. This will make it easy to wipe dirt from the surfaces with a detergent. Also, the protective film may be made thick and used for a front light as well as for the screen surface.
The display panel according to the example of the present invention may be used in combination with the three-side free configuration. The three-side free configuration is useful especially when pixels are built using amorphous silicon technology. Also, in the case of panels formed using amorphous silicon technology, since it is difficult to control variations in the characteristics of transistor elements during production processes, it is preferable to use the N-pulse driving, reset driving, dummy pixel driving, or the like according to the present invention. That is, the transistors according to the present invention are not limited to those produced by polysilicon technology, and they may be produced by amorphous silicon technology.
Incidentally, the N-fold pulse driving (
The technical idea described in the example of the present invention can be applied to video cameras, projectors, 3D television sets, projection television sets, etc. It can also be applied to viewfinders, cell phone monitors, PHS, personal digital assistants and their monitors, and digital cameras and their monitors.
Also, the technical idea is applicable to electrophotographic systems, head-mounted displays, direct view monitors, notebook personal computers, video cameras, electronic still cameras. Also, it is applicable to ATM monitors, public phones, videophones, personal computers, and wristwatches and its displays.
Furthermore, it goes without saying that the technical idea can be applied to display monitors of household appliances, pocket game machines and their monitors, backlights for display panels, or illuminating devices for home or commercial use. Preferably, illuminating devices are configured such that color temperature can be varied. Color temperature can be changed by forming RGB pixels in stripes or in dot matrix and adjusting currents passed through them. Also, the technical idea can be applied to display apparatus for advertisements or posters, RGB traffic lights, alarm lights, etc.
Also, organic EL display panels are useful as light sources for scanners. An image is read with light directed to an object using an RGB dot matrix as a light source. Needless to say, the light may be monochromatic. Besides, the matrix is not limited to an active matrix and may be a simple matrix. The use of adjustable color temperature will improve imaging accuracy.
Also, organic EL display panels are useful as backlights of liquid crystal display panels. Color temperature can be changed and brightness can be adjusted easily by forming RGB pixels of an EL display panel (backlight) in stripes or in dot matrix and adjusting currents passed through them. Besides, the organic EL display panel, which provides a surface light source, makes it easy to generate Gaussian distribution that makes the center of the screen brighter and perimeter of the screen darker. Also, organic EL display panels are useful as backlights of field-sequential liquid crystal display panels which scan with R, G, and B lights in turns. Also, they can be used as backlights of liquid crystal display panels for movie display by inserting black even if the backlights are turned on and off.
According to the present invention, the display panels, display apparatus, etc. offer distinctive effects, including high quality, high movie display performance, low power consumption, low costs, high brightness, etc., according to their respective configurations. Incidentally, the present invention does not consume much power because it can provide power-saving information display apparatus. Also, it does not waste resources because it can reduce size and weight. Furthermore, it can adequately support high-resolution display panels. Thus, the present invention is friendly to both global environmental and space environment.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2002-127532 | Apr 2002 | JP | national |
| 2002-127637 | Apr 2002 | JP | national |
| 2002-284393 | Sep 2002 | JP | national |
This application is a divisional of U.S. application Ser. No. 10/511,447, filed Mar. 6, 2003 and is based upon and claims priority from prior Japanese Patent Applications 2002-127532, filed Apr. 26, 2002; 2002-127637, filed Apr. 26, 2002 and 2002-284393, filed Sep. 27, 2002, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10511447 | Oct 2004 | US |
| Child | 12835083 | US |
