Claims
- 1. An EEPROM cell comprising:
- silicon substrate;
- an first active area on the substrate defined by gate oxide regions which contact and lie in substantially the same plane as the first active area;
- a second active area on the substrate defining transistor circuitry;
- means for providing a cell breakdown voltage which is greater than a cell programming voltage;
- wherein the means for providing includes a combined layer of silicon oxide on the first active region and a single layer of silicon oxide on the second active area, the combined layer of silicon oxide, the combined layer having a thickness greater than the single layer.
- 2. An EEPROM cell as claimed in claim 1 wherein the combined layer of silicon oxide includes two layers of silicon oxide on one another having a total combined layer thickness substantially within the range of 30 to 35 nanometers.
- 3. An EEPROM cell as claimed in claim 2 wherein the combined silicon oxide layer is lightly doped with phosphorus.
Priority Claims (1)
Number |
Date |
Country |
Kind |
MI91A3196 |
Nov 1991 |
ITX |
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Parent Case Info
This application is a division of application Ser. No. 07/983,799 filed Nov. 24, 1992, U.S. Pat. No. 5,367,483.
US Referenced Citations (3)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0244367 |
Nov 1987 |
EPX |
0268315 |
May 1988 |
EPX |
3107543 |
Dec 1981 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Patent Abstracts of Japan, vol. 6, No. 259 (E-149)(1137) Dec. 17, 1982 & JP-A-57155769 (Fujistu K.K.) Sep. 25, 1982. |
Patent Abstracts of Japan, vol. 12, No. 403 (e-674)(3250) Oct. 26, 1988 & JP-A-63144559 (Toshiba Corp) Jun. 16, 1988. |
Divisions (1)
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Number |
Date |
Country |
Parent |
983799 |
Nov 1992 |
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