ELECTRONIC CIRCUITS AND CIRCUIT ELEMENTS

FIELD

The present invention relates to electronic circuits (and in particular, although not exclusively, to flexible integrated circuits, i.e. flexible ICs), and components (i.e. elements) of such circuits. Certain embodiments are concerned with electronic circuits in which two or more of the following types of circuit elements are integrated: transistor; resistor; and Schottky diode. Thus, certain embodiments of the present invention relate to electronic circuits comprising at least one transistor and at least one resistor, and in particular, although not exclusively, to flexible integrated circuits comprising at least one transistor and at least one resistor. Certain embodiments relate to electronic circuits (e.g. flexible ICs) comprising: at least one transistor and at least one Schottky diode; at least one resistor and at least one Schottky diode; and at least one transistor, at least one Schottky diode, and at least one resistor. Certain embodiments relate to dual gate transistors and electronic circuits comprising such transistors, for example circuits integrating such transistors with at least one Schottky diode and/or at least one resistor.

BACKGROUND

Whilst flexible integrated circuits (FlexICs) are known, there remain few technologies capable of producing low cost FlexICs. Most FlexIC technologies have been developed for application to displays, rather than to digital or analogue processing, sensing and communication. One of the most promising FlexIC technologies is based on thin film transistors (TFTs) incorporating metal oxide semiconductors. The high optical transmission of these devices has contributed to their development for displays, however the commercially feasible materials are presently all n-type semiconductors. This means that metal oxide-based FlexIC architectures cannot incorporate silicon-based circuit designs of the past three decades, which are almost exclusively based on complementary semiconductors (i.e. the circuits contain both n-type and p-type transistors). These CMOS circuits have enabled a degree of integration, efficiency and complexity that has so far been unachievable in any commercial unipolar (n-type or p-type) technologies. Certain aspects and embodiments of the present invention are concerned with the development of metal oxide-based FlexICs to enable low cost applications in processing, sensing, communication and other fields, and have therefore required a different approach.

In the past, unipolar integrated circuits (ICs) based on silicon have featured integrated resistors. However, typically these resistors had relatively low resistivity of up to ˜50 k Ω/□ (50 kOhm per square). This limited the economically viable (i.e. sufficiently small in IC footprint) resistor range. In turn, this limitation drove the development of circuit architectures using diode- or transistor-load transistors, which suffered from high power consumption and slow switching speeds in comparison to contemporary circuits based on bipolar transistors. Furthermore, these resistor technologies were applicable only to bulk crystalline semiconductors. Later IC processes featured thin film metal- or polysilicon-based resistors in ‘back end of line’ (BEOL) layers above the active devices. These resistors have even lower resistivity of up to around 100 Ω/□ (100 Ohm per square), however.

Schottky diodes are well-known electronic components, typically providing very fast switching from their conducting to non-conducting states and hence they are particularly good for rectifying high frequency signals. Schottky diodes are also well-known for use in numerous other electronic applications and circuit configurations. WO 2019/116020A1 (the contents of which are incorporated herein by reference) discloses a variety of Schottky diodes suitable for use in thin and/or flexible electronic circuits, and which may be integrated in embodiments of the present invention. These Schottky diodes typically comprise: a first electrode; a second electrode; and a body (e.g. a layer) of semiconductive material connected to the first electrode at (by) a first interface (junction) and connected to the second electrode at (by) a second interface (junction), wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset (separated, spaced) from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky (rectifying) contact. However, certain embodiments of the present invention may incorporate Schottky diodes of other configurations, for example purely lateral or purely vertical devices, known in the art.

SUMMARY

Aspects and embodiments of the present invention aim to address at least one of the problems associated with the prior art. Furthermore, certain aspects and embodiments of the present invention address the problems of how to integrate resistors and/or transistors and/or Schottky diodes in electronic circuits, especially, but not exclusively, electronic circuits which are at least one of: capable of being produced in high volumes; capable of being produced at low cost; flexible; transparent; and have a small footprint. Certain aspects and embodiments of the present invention also aim to provide resistor geometries, technologies, materials, and methods of their manufacture, which are compatible with incorporation or integration with electronic circuits of any one or more of the above-mentioned types. Furthermore, certain aspects and embodiments of the present invention address the problem of how to manufacture circuits, especially flexible ICs, incorporating resistors, where the resistors have resistances in the desired ranges for their intended applications in the circuits, and yet the circuits have small footprints. Certain aspects and embodiments of the present invention also aim to provide dual gate transistor geometries, technologies, materials, and methods of their manufacture, which are compatible with incorporation or integration with electronic circuits of any one or more of the above-mentioned types. Furthermore, certain aspects and embodiments of the present invention address the problem of how to manufacture circuits, especially flexible ICs, incorporating resistors (and optionally transistors and/or Schottky diodes), where the resistors have resistances in the desired ranges for their intended applications in the circuits, and yet the circuits have small footprints.

In accordance with a first aspect of the present invention there is provided an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a resistor (2),

the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semiconductive channel between the source and drain terminals,

the resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal,

wherein said first body (10) of material comprises a metal oxide (e.g. comprises a first quantity of said metal oxide) and said second body (20) of material comprises said metal oxide (e.g. comprises a second quantity of said metal oxide).

Advantageously, as the semiconductive first body (channel body) 10 and the resistor body 20 are each formed from the same metal oxide, they may be formed, for example by deposition, in the same machine, for example without having to remove the circuit structure between forming the first quantity of metal oxide and the second. They may be formed sequentially, but under different conditions, the conditions being selected/arranged such that the first body is semiconductive and the second body is resistive, or vice versa. Alternatively, the metal oxide material of the first and second bodies may be formed at the same time as each other, for example in a single deposition step, with the difference in electrical properties being achieved by different doping and/or by different subsequent processing. Furthermore, a combination of different deposition conditions, different doping, and/or different subsequent processing may be used to achieve different electrical properties of the bodies based on the same metal oxide material.

In certain embodiments, the circuit comprises first and second voltage (supply) rails (61, 62), the resistor is a load resistor connected in series between one of the source and drain terminals (11, 12 and one of said voltage (supply) rails.

In certain embodiments, the second body (20) of material comprises a dopant. In certain such embodiments, the first body (10) of material does not comprise said dopant, and this difference contributes at least in part to the different electrical properties of the two bodies.

In certain alternative embodiments, first body (10) of material comprises a dopant in a first range of concentrations, and said second body (20) of material comprises said dopant in a second range of concentrations. In certain such embodiments the second range is higher than said first range, and in others the second range is lower than said first range.

In certain embodiments, at least a portion of the second body (20) has been processed (e.g. annealed, laser annealed, thermally annealed, exposed to electromagnetic radiation, doped, implanted, exposed to a flux of ions) to increase (or decrease) its conductivity.

In certain embodiments, each of the first and second bodies (10, 20) comprises a respective layer, film, or sheet of said metal oxide. In certain such embodiments, each said layer, film, or sheet has a thickness in the range 1 to 200 nm (for example in the range 5 to 50 nm).

In certain embodiments, each said layer, film, or sheet has the same thickness.

In certain embodiments, each said layer, film, or sheet is flat (planar). In certain such embodiments, the first and second bodies are coplanar, although in certain alternative embodiments the first body lies in a first plane and the second body lies in a second plane, the second plane being parallel to said first plane.

In certain embodiments, the second body has a sheet resistance value in the range 25 kOhm/sq to 20 MOhm/sq (e.g. in the range 50 kOhm/sq to 10 MOhm/sq). Advantageously, this enables resistors having resistances in the ranges desired for a wide variety of applications to be manufactured, whilst having relatively small/compact footprints. In other words, the areas of resistive material required may be suitably small.

In certain embodiments, each of the first and second bodies is substantially transparent to electromagnetic radiation in the range visible to the naked human eye.

In certain embodiments, the circuit (or circuit module) comprises a substrate (5) arranged to support, directly or indirectly, each of the transistor (1) and the resistor (2). In certain embodiments the substrate is flexible, as indeed may be the circuit itself.

In certain embodiments, the metal oxide is Indium Gallium Zinc Oxide, IGZO.

In certain embodiments the resistor (2) exhibits a resistance between its terminals (21, 22) in the range 10 ohm to 10 MOhm (for example 100 ohm or 1 kOhm to 1 or 10 MOhm) at room temperature.

In certain embodiments, the circuit further comprises a second resistor (3) comprising first and second terminals (31, 32) and a third body (30) of material providing a resistive current path between said terminals, wherein said third body of material comprises said metal oxide (e.g. comprises a third quantity of said metal oxide). In certain such embodiments, each of the second and third bodies is flat (planar), wherein the second body lies in a second plane and the third body lies in a third plane, said third plane being parallel to said second plane.

In certain embodiments, the first and second resistors exhibit different resistances at room temperature. For example, the second body of material may comprise a dopant in a second range of concentrations, and said third body of material may comprise said dopant in a third range of concentrations, said second range being different from said third range. Additionally, or alternatively, the third body (30) may have been processed differently from said second body to achieve the different resistances.

In certain embodiments, the transistor comprises a second gate terminal (132). This second gate terminal (132) may be arranged on an opposite side of the first body (10) to the first gate terminal (13, 131), and may be separated from the semiconductive material of the first body (10) by a further layer, or other body, of dielectric material (42).

Another aspect of the present invention provides a method of manufacturing an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a resistor (2), the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semiconductive channel between the source and drain terminals, and the resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising: forming the first body (10); and forming the second body (20), wherein the first body comprises a first quantity (100) of a metal oxide and the second body comprises a second quantity (200) of said metal oxide.

In certain embodiments forming the first body comprises forming said first quantity of said metal oxide, and forming the second body comprises forming said second quantity of said metal oxide.

In certain embodiments forming said first quantity comprises forming said first quantity (100) directly or indirectly on a first region (51) of a substrate, and forming said second quantity comprises forming said second quantity (200) directly or indirectly on a second region (52) of the substrate.

In certain embodiments, said forming of said first quantity comprises forming said first quantity (100) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.

In certain embodiments, said forming of said second quantity comprises forming said second quantity (200) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.

In certain embodiments, forming said first quantity comprises depositing said first quantity of said metal oxide.

In certain embodiments forming said second quantity comprises depositing said second quantity of said metal oxide.

In certain embodiments, said forming of said first quantity is performed before said forming of said second quantity.

In certain embodiments, said forming of said first quantity is performed after said forming of said second quantity.

In certain embodiments, said forming of said first quantity comprises forming (e.g. by depositing or otherwise forming) a first layer, film, or sheet (1001) of said metal oxide, said first layer, film, or sheet comprising said first quantity (100).

In certain embodiments, forming the first body (10) comprises patterning the first layer, film, or sheet (1001).

In certain embodiments, forming of said second quantity comprises forming (e.g. by depositing or otherwise forming) a second layer, film, or sheet (2001) of said metal oxide, said second layer, film, or sheet comprising said second quantity (200).

In certain embodiments, forming the second body (2) comprises patterning the second layer, film, or sheet (2001).

In certain embodiments, said forming of said first quantity (100) is performed at the same time as forming said second quantity (200).

In certain embodiments, said forming of said first quantity at the same time as forming said second quantity comprises forming (e.g. by depositing or otherwise forming) a layer, film, or sheet (1200) of said metal oxide, said layer, film, or sheet (1200) comprising said first and second quantities (100, 200).

In certain embodiments, forming the first and second bodies (10, 20) comprises patterning said sheet (1200).

In certain embodiments, the method further comprises doping said first body (10) of material with a first dopant to decrease (or increase) an electrical conductivity of said first body.

In certain embodiments, doping said first body of material comprises forming said first quantity (100) on a source (71) of said first dopant.

In certain embodiments, the method comprises providing said source (71) of said first dopant directly or indirectly on said first region (51) of the substrate.

In certain embodiments, doping said first body of material comprises forming a source of said first dopant on said first body of material.

In certain embodiments, the method further comprises doping said second body (20) of material with a second dopant to increase (or decrease) an electrical conductivity of said second body.

In certain embodiments, doping said second body of material comprises forming said second quantity (200) on a source (72) of said second dopant.

In certain embodiments, the method further comprises providing said source (72) of said second dopant directly or indirectly on said second region (52) of the substrate.

In certain embodiments, doping said second body of material comprises forming a source of said second dopant on said second body of material.

In certain embodiments, the method further comprises processing said second quantity (200) of said metal oxide to increase or decrease an electrical conductivity of the second body.

In certain embodiments, processing said second quantity comprises annealing (or otherwise processing) at least a portion of said second quantity to increase or decrease its conductivity.

In certain embodiments, said processing of the second body (e.g. by annealing, or other means) comprises exposing said at least a portion to electromagnetic radiation.

In certain embodiments, the method further comprises providing said electromagnetic radiation from a lamp. In certain other embodiments, the electromagnetic radiation may be provided from a laser.

In certain embodiments, the method further comprises shielding at least a portion of the first quantity (100) of said metal oxide from said electromagnetic radiation.

In certain embodiments, said shielding comprises using said gate terminal (13) to shield said at least a portion of the first quantity (100) from said electromagnetic radiation.

In certain embodiments, each of the first and second bodies (10, 20) comprises a respective layer, film, or sheet of said metal oxide, and each said respective layer, film, or sheet may have a thickness in the range 1 to 200 nm (for example 5 to 50 nm).

In certain embodiments, each said respective layer, film, or sheet has the same thickness. In certain embodiments, each said respective layer, film, or sheet is flat (planar).

In certain embodiments, the method comprises forming the first and second bodies (10, 20) in a common plane.

In certain embodiments, the method comprises forming the first body in a first plane and forming the second body in a second plane, said second plane being parallel to said first plane.

In certain embodiments, the second body has a sheet resistance value in the range 25 kOhm/sq to 20 MOhm/sq (e.g. in the range 50 kOhm/sq to 10 MOhm/sq).

In certain embodiments, each of the first and second bodies is substantially transparent to electromagnetic radiation in the range visible to the naked human eye.

In certain embodiments, the method further comprises providing a substrate (5) arranged to support, directly or indirectly, each of the transistor and the resistor, and said forming of the first and second bodies comprises forming the first body (10) on or over a first region (51) of the substrate and forming the second body (20) on or over a second region (52) of the substrate.

In certain embodiments, said substrate (5) is flexible.

In certain embodiments, the method further comprises forming the source terminal, drain terminal, first resistor terminal, and second resistor terminal after forming the first and second bodies. In certain alternative embodiments, the method further comprises forming the source terminal, drain terminal, first resistor terminal, and second resistor terminal before forming the first and second bodies, for example to form bottom contact devices.

In certain embodiments, said metal oxide is Indium Gallium Zinc Oxide, IGZO.

In certain embodiments, said resistor exhibits a resistance between its terminals in the range 10 ohm to 10 MOhm (for example 100 ohm or 1 kOhm to 1 or 10 MOhm) at room temperature.

In certain embodiments, the circuit further comprises a second resistor (3) having first and second terminals (31, 32) and a third body (30) of material providing a resistive current path between said terminals, the method comprising forming said third body (30) of material, said third body comprising a third quantity (300) of said metal oxide. The second resistor may, for example, be in a different layer of the circuit from the first resistor.

In certain embodiments, the method further comprises doping or processing said third body differently from said second body, such that the first and second resistors exhibit different resistances at room temperature. For example, one of the resistor bodies may be shielded from exposure to irradiation (e.g. UV irradiation), whilst the other is unshielded and hence receives UV irradiation and as a result has its conductivity increased or decreased.

In certain embodiments, said resistor is a load resistor connected in series between one of the source and drain terminals and a voltage (supply) rail.

In certain embodiments, the electronic circuit is flexible.

Another aspect of the present invention provides a resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal, wherein the body (20) covers at least part of an upper surface of the first resistor terminal (21), and the second resistor terminal (22) covers at least a portion of a top surface of the second body (20). In other words, the body (20) may at least partially overlap the first resistor terminal (21), and the second resistor terminal (22) may at least partially overlap the second body. The resistor may be formed on a substrate, or some other supporting body or structure, and the body (20) may comprise a quantity of a metal oxide material.

Another aspect of the present invention provides a method of manufacturing a resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising: forming the body, then forming the first resistor terminal, and then forming the second resistor terminal. In an alternative aspect, the method comprises: forming the first resistor terminal (21), then forming the body (20), and then forming the second resistor terminal (22). In a further aspect, the method comprises: forming the first resistor terminal (21), then forming the second resistor terminal (22), and then forming the body (20). Thus, the resistor terminals are not formed at the same time (or in the same processing step or sequence of steps) as each other.

Further aspects of the invention provide a resistor as defined in connection with any one of the above-mentioned aspects or embodiments, and a method of manufacturing such a resistor.

Another aspect of the present invention provides an electronic circuit (or circuit module) (10000) comprising a Schottky diode (3000) and a resistor (2),

the Schottky diode comprising a first electrode (3001), a second electrode (3002), and a first body (3010) (e.g. a layer) of semiconductive material connected to the first electrode at (by) a first interface (junction) and connected to the second electrode at (by) a second interface (junction),

wherein said first body (3010) of semiconductive material comprises a metal oxide (e.g. comprises a first quantity of said metal oxide) and said second body (20) of material comprises said metal oxide (e.g. comprises a second quantity of said metal oxide).

Advantageously, as the semiconductive first body (Schottky diode body) 3010 and the resistor body 20 are each formed from the same metal oxide, they may be formed, for example by deposition, in the same machine, for example without having to remove the circuit structure between forming the first quantity of metal oxide and the second. They may be formed sequentially, but under different conditions, the conditions being selected/arranged such that the first body is semiconductive and the second body is resistive. Alternatively, the metal oxide material of the first and second bodies may be formed at the same time as each other, for example in a single deposition step, with the difference in electrical properties being achieved by different doping and/or by different subsequent processing. Furthermore, a combination of different deposition conditions, different doping, and/or different subsequent processing may be used to achieve different electrical properties of the bodies based on the same metal oxide material.

Features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect (incorporating at least one Schottky diode and at least one resistor) with corresponding advantage.

For example, in certain embodiments, the second body (20) of material comprises a dopant. In certain such embodiments, the first body (3010) of semiconductive material does not comprise said dopant, and this difference contributes at least in part to the different electrical properties of the two bodies.

In certain alternative embodiments, first body (3010) of semiconductive material comprises a dopant in a first range of concentrations, and said second body (20) of material comprises said dopant in a second range of concentrations. In certain such embodiments the second range is higher than said first range, and in others the second range is lower than said first range.

In certain embodiments, each of the first and second bodies (3010, 20) comprises a respective layer, film, or sheet of said metal oxide. In certain such embodiments, each said layer, film, or sheet has a thickness in the range 1 to 200nm (for example in the range 5 to 50 nm).

In certain embodiments, the circuit (or circuit module) comprises a substrate (5) (which may also be referred to as a supporting layer, underlayer, or structure) arranged to support, directly or indirectly, each of the Schottky diode (3000) and the resistor (2). In certain embodiments the substrate is flexible, as indeed may be the circuit itself.

A further aspect of the present invention provides a method of manufacturing an electronic circuit (or circuit module)(10000) comprising a Schottky diode (3000) and a resistor (2), the Schottky diode comprising a first electrode (3001), a second electrode (3002), and a first body (3010) (e.g. a layer) of semiconductive material connected to the first electrode at (by) a first interface (junction) and connected to the second electrode at (by) a second interface (junction), the resistor comprising a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal, the method comprising: forming the first body (3010); and forming the second body (20), wherein the first body comprises a first quantity (3100) of a metal oxide and the second body comprises a second quantity (200) of said metal oxide.

Again, features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect with corresponding advantage.

For example, in certain embodiments forming the first body comprises forming said first quantity (3100) of said metal oxide, and forming the second body comprises forming said second quantity (200) of said metal oxide.

In certain embodiments forming said first quantity comprises forming said first quantity (3100) directly or indirectly on a first region (51) of a substrate, and forming said second quantity comprises forming said second quantity (200) directly or indirectly on a second region (52) of the substrate.

In certain embodiments, said forming of said first quantity (3100) comprises forming said first quantity (3100) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.

In certain embodiments, said forming of said first quantity (3100) is performed before said forming of said second quantity (200).

In certain embodiments, said forming of said first quantity (3100) is performed after said forming of said second quantity (200).

In certain embodiments, said forming of said first quantity (3100) comprises forming (e.g. by depositing or otherwise forming) a layer, film, or sheet (1001) of said metal oxide, said layer, film, or sheet comprising said first quantity (3100).

In certain embodiments, forming the first body (3010) comprises patterning the layer, film, or sheet.

In certain embodiments, said forming of said first quantity (3100) is performed at the same time as forming said second quantity (200).

In certain embodiments, said forming of said first quantity (3100) at the same time as forming said second quantity comprises forming (e.g. by depositing or otherwise forming) a layer, film, or sheet of said metal oxide, said layer, film, or sheet comprising said first and second quantities (3100, 200). In certain embodiments, forming the first and second bodies (3010, 20) comprises patterning that sheet.

In certain embodiments, the method further comprises doping said first body (3010) of material with a first dopant to decrease (or increase) an electrical conductivity of said first body.

In certain embodiments, doping said first body of material comprises forming said first quantity (3100) on a source (71) of said first dopant.

In certain embodiments, the method comprises providing said source (71) of said first dopant directly or indirectly on said first region (51) of the substrate.

In certain embodiments, doping said first body of material comprises forming a source of said first dopant on said first body of material.

In certain embodiments, the method further comprises doping said second body (20) of material with a second dopant to increase (or decrease) an electrical conductivity of said second body.

In certain embodiments, doping said second body of material comprises forming said second quantity (200) on a source (72) of said second dopant.

In certain embodiments, the method further comprises providing said source (72) of said second dopant directly or indirectly on said second region (52) of the substrate.

In certain embodiments, doping said second body of material comprises forming a source of said second dopant on said second body of material.

In certain embodiments, the method further comprises processing said second quantity (200) of said metal oxide to increase or decrease an electrical conductivity of the second body.

In certain embodiments, processing said second quantity comprises annealing at least a portion of said second quantity to increase or decrease its conductivity.

In certain embodiments, said annealing comprises exposing said at least a portion to electromagnetic radiation.

In certain embodiments, the method further comprises providing said electromagnetic radiation from a lamp.

In certain embodiments, the method further comprises shielding at least a portion of the first quantity (3100) of said metal oxide from said electromagnetic radiation.

In certain embodiments, each of the first and second bodies (3010, 20) is substantially transparent to electromagnetic radiation in the range visible to the naked human eye.

In certain embodiments, the method further comprises providing a substrate (5) (which may also be referred to as a supporting layer, underlayer, or structure) arranged to support, directly or indirectly, each of the Schottky diode and the resistor, and said forming of the first and second bodies comprises forming the first body (3010) on or over a first region (51) of the substrate and forming the second body (20) on or over a second region (52) of the substrate.

In certain embodiments, the method further comprises forming the first electrode, second electrode, first resistor terminal, and second resistor terminal after forming the first and second bodies (3010, 20). In certain alternative embodiments, the method further comprises forming the first electrode, second electrode, first resistor terminal, and second resistor terminal before forming the first and second bodies, for example to form bottom contact devices.

A further aspect of the invention provides an electronic circuit (or circuit module) (10000) comprising a transistor (1) and a Schottky diode (3000),

the Schottky diode comprising a first electrode (3001), a second electrode (3002), and a second body (3010) (e.g. a layer) of semiconductive material connected to the first electrode at (by) a first interface (junction) and connected to the second electrode at (by) a second interface (junction), wherein said first body (10) of material comprises a metal oxide (e.g. comprises a first quantity of said metal oxide) and said second body (3010) of material comprises said metal oxide (e.g. comprises a second quantity of said metal oxide).

Advantageously, as the semiconductive first body (channel body) 10 and the Schottky body 3010 are each formed from the same metal oxide, they may be formed, for example by deposition, in the same machine, for example without having to remove the circuit structure between forming the first quantity of metal oxide and the second. They may be formed sequentially (under the same or different conditions, the conditions being selected/arranged to produce semiconductive paths having the desired characteristics). Alternatively, they may be formed at the same time as each other, for example in a single deposition step. If different semiconductive properties are required for the transistor channel and Schottky body, then the difference in electrical properties may be achieved by different doping and/or by different subsequent processing. Furthermore, a combination of different deposition conditions, different doping, and/or different subsequent processing may be used to achieve different electrical properties of the bodies based on the same metal oxide material.

In certain embodiments, the circuit comprises first and second voltage (supply) rails (61, 62), the Schottky diode is a load connected in series between one of the source and drain terminals (11, 12 and one of said voltage (supply) rails.

Again, features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect (comprising at least one transistor and at least one Schottky diode) with corresponding advantage.

For example, in certain embodiments, the second body (3010) of material comprises a dopant. In certain such embodiments, the first body (10) of material does not comprise said dopant, and this difference contributes at least in part to the different electrical properties of the two bodies.

In certain alternative embodiments, first body (10) of material comprises a dopant in a first range of concentrations, and said second body (3010) of material comprises said dopant in a second range of concentrations. In certain such embodiments the second range is higher than said first range, and in others the second range is lower than said first range.

In certain embodiments, at least a portion of the second body (3010) has been processed (e.g. annealed, laser annealed, thermally annealed, exposed to electromagnetic radiation, doped, implanted, exposed to a flux of ions) to increase or decrease its conductivity.

In certain embodiments, each of the first and second bodies (10, 3010) comprises a respective layer, film, or sheet of said metal oxide.

In certain embodiments, the circuit (or circuit module) comprises a substrate (5) arranged to support, directly or indirectly, each of the transistor (1) and the Schottky diode (3000). In certain embodiments the substrate is flexible, as indeed may be the circuit itself.

In certain embodiments, the circuit further comprises at least one resistor (2) comprising first and second terminals (21, 22) and a resistor body (20) of material providing a resistive current path between said terminals (21, 22), wherein said resistor body of material comprises said metal oxide (e.g. comprises a third quantity of said metal oxide).

In certain embodiments, the circuit comprises at least two such resistors, which may be arranged to exhibit different resistances at room temperature, this difference being achieved using any of the techniques described above.

A further aspect of the present invention provides a method of manufacturing an electronic circuit (or circuit module)(10000) comprising a transistor (1) and a Schottky diode, the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semiconductive channel between the source and drain terminals, and the Schottky diode comprising a first electrode (3001), a second electrode (3002), and a second body (3010) (e.g. a layer) of semiconductive material connected to the first electrode at (by) a first interface (junction) and connected to the second electrode at (by) a second interface (junction), the method comprising: forming the first body (10); and forming the second body (30210), wherein the first body comprises a first quantity (100) of a metal oxide and the second body comprises a second quantity (3100) of said metal oxide.

Again, features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect with corresponding advantage.

For example, in certain embodiments forming the first body comprises forming said first quantity (100) of said metal oxide, and forming the second body (3010) comprises forming said second quantity (3100) of said metal oxide.

In certain embodiments forming said first quantity comprises forming said first quantity (100) directly or indirectly on a first region (51) of a substrate, and forming said second quantity comprises forming said second quantity (3100) directly or indirectly on a second region (52) of the substrate.

In certain embodiments, said forming of said first quantity (100) comprises forming said first quantity (100) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.

In certain embodiments, said forming of said second quantity (3100) comprises forming said second quantity (200) using a technique selected from a list comprising: physical deposition; physical vapour deposition (PVD); chemical deposition; chemical vapour deposition (CVD); atomic layer deposition (ALD); physical-chemical deposition; evaporation; sputtering; sol-gel techniques; chemical bath deposition; spray pyrolysis; plating techniques; pulsed laser deposition (PLD); solution processing; and spin coating.

In certain embodiments, said forming of said first quantity (100) is performed before said forming of said second quantity (3100).

In certain embodiments, said forming of said first quantity (100) is performed after said forming of said second quantity (3100).

In certain embodiments, said forming of said first quantity (100) is performed at the same time as forming said second quantity (3100).

In certain embodiments, said forming of said first quantity at the same time as forming said second quantity comprises forming (e.g. by depositing or otherwise forming) a layer, film, or sheet of said metal oxide comprising said first and second quantities (100, 3100).

In certain embodiments, the method comprises forming a second gate terminal on an opposite side of the first body (10) to the first gate terminal (13, 131),

In certain embodiments, the method further comprises providing a substrate (5) arranged to support, directly or indirectly, each of the transistor and the Schottky diode (3000).

Another aspect of the invention provides a transistor (1) comprising: a source terminal (11), a drain terminal (12), a first body (10) of material providing a controllable semiconductive channel between the source and drain terminals, a first gate terminal (131) arranged on one side of (e.g. under) the first body (10), and a second gate terminal (132) arranged on an opposite side (e.g. above) the first body (10).

Again, features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect with corresponding advantage.

In certain embodiments, the first gate terminal (131), first body (10), and the second gate terminal (132) are arranged as a stack in a first (i.e. nominally vertical) direction, with the first body (10) being arranged above the first gate terminal (131) and separated from the first gate terminal (in said first direction) by a first layer or body of dielectric material (41), the second gate terminal (132) being arranged above the first body (10) and separated from the first body (10) (in said first direction) by a second layer or body of dielectric material (42), and the source and drain terminals being arranged such that there is no overlap between projections of either gate terminal with projections of either the source or drain terminals onto a plane normal to said first direction (i.e. a horizontal plane, normal to the vertical direction.

In certain embodiments, the first and second gate terminals are aligned and arranged to have the same projections as each other onto said plane. In certain embodiments, edges of the source and drain terminals are arranged to coincide with edges of the aligned gate terminals.

In certain embodiments, the first body (10) is provided by a first portion of a layer of metal oxide material, said first portion being arranged over said first gate terminal, and said source and drain terminals (11, 12) are provided by respective portions of said layer of metal oxide material extending beyond edges of the first gate terminal. In certain embodiments, said respective portions have higher electrical conductivity than said first body.

In certain alternative embodiments, said source and drain terminals are each formed from a metal.

Another aspect of the present invention provides an integrated circuit comprising a dual gate transistor in accordance with the preceding aspect, and at least one resistor and/or at least one Schottky diode (for example as described above).

A further aspect of the invention provides a method of manufacturing a dual-gate transistor, the method comprising: providing a lower gate terminal supported on a substrate; and using the lower gate terminal as a mask in the formation of an upper gate terminal aligned to the lower gate terminal.

In certain embodiments, the method further comprises: using the lower gate terminal as a mask in the formation of source and drain terminals aligned to the lower gate terminal.

In certain alternative embodiments, the method further comprises: using the upper gate terminal as a mask in the formation of source and drain terminals aligned to the lower gate terminal.

A further aspect of the present invention provides: an electronic circuit (or circuit module) (10000) comprising a first device (1, 3000) and a second device (2, 3000),

the first device comprising a first terminal (11, 3001), a second terminal (12, 3002), and a first body (10, 3010) of semiconductive material providing a semiconductive path between the first and second terminals,

the second device (2, 3000) comprising a third terminal (21, 3001), a fourth terminal (22, 3002), and a second body (20, 3010)) of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal,

wherein said first body (10, 3010) of material comprises a metal oxide (e.g. comprises a first quantity (100, 3100) of said metal oxide) and said second body (20, 3010) of material comprises said metal oxide (e.g. comprises a second quantity (200, 3100) of said metal oxide).

Advantageously, as the first body 10, 3010 and the second body 20, 3010 are each formed from the same metal oxide, they may be formed, for example by deposition, in the same machine, for example without having to remove the circuit structure between forming the first quantity of metal oxide and the second. They may be formed sequentially, under the same or different conditions, the conditions being selected/arranged such that the first body is semiconductive and the second body is semiconductive or resistive. Alternatively, the metal oxide material of the first and second bodies may be formed at the same time as each other, for example in a single deposition step, with a difference in electrical properties (if desired) being achieved by different doping and/or by different subsequent processing. Furthermore, a combination of different deposition conditions, different doping, and/or different subsequent processing may be used to achieve different electrical properties of the bodies based on the same metal oxide material.

The first device may, for example, be a transistor (e.g. bottom gate, top gate, or dual gate) or a Schottky diode. The second device may, for example, be a resistor or a Schottky diode. The circuit may further comprise at least one further device (e.g. a third device), having a body also formed from the same metal oxide material. That further device may, for example, be a transistor, resistor, or Schottky diode. Again, features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect with corresponding advantage.

A further aspect of the present invention provides a method of manufacturing an electronic circuit (or circuit module)(10000) comprising a first device (1, 3000) and a second device (2, 3000), the first device comprising a first terminal (11, 3001), a second terminal (12, 3002), and a first body (10, 3010) of semiconductive material providing a semiconductive path between the first and second terminals, the second device (2, 3000) comprising a third terminal (21, 3001), a fourth terminal (22, 3002), and a second body (20, 3010)) of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal, the method comprising: forming the first body (10, 3010); and forming the second body (20, 3010), wherein the first body comprises a first quantity (100, 3100) of a metal oxide and the second body comprises a second quantity (200, 3100) of said metal oxide.

Again, features of any of the above-mentioned aspects and embodiments of the invention may be incorporated in embodiments of this further aspect with corresponding advantage.

In certain embodiments of any aspect of the present invention, at least one of the quantities of metal oxide may be formed so as to be initially semi-conductive material, in a “normally off” condition (e.g. enhancement mode, n-type or p-type). For such materials, since their conductivities are initially very low (because they are in the normally off state), processing arranged to increase their conductivities may be employed in order to change their electrical characteristics to resistive.

In certain embodiments of any aspect of the present invention, at least one of the quantities of metal oxide may be formed so as to be initially semi-conductive material, in a “normally on” condition (e.g. depletion mode, n-type or p-type). For such materials, since their conductivities are initially relatively high (because they are in the normally on state), processing arranged to decrease their conductivities may be employed in order to change their electrical characteristics to resistive.

In certain embodiments, exposure to electromagnetic (e.g. optical) radiation may be employed to increase the conductivity of at least part of at least one of the quantities of metal oxide. For example, “normally off” semiconductive material (e.g. SnO with a negative threshold voltage) may be exposed to radiation to change its characteristics to being substantially resistive. NiO can be tuned from p-type to n-type with an increase in conductivity.

In certain embodiments, exposure to electromagnetic (e.g. optical) radiation may be employed to decrease (reduce) the conductivity of at least part of at least one of the quantities of metal oxide. For example, one may change from n-type material (e.g. SnO2) to p-type material (e.g. SnO) using H2 annealing to reduce the Sn(IV). Exposure to optical radiation may be used on a semiconductor that is “normally on”, e.g. for devices that are p-type with a positive threshold voltage. That semiconductor will have a relative high conductivity initially, and the radiation may be arranged to reduce that conductivity, making the material substantially resistive (thus providing a route to integrating resistors in a p-type process in certain embodiments. This reduction in conductivity (to produce a resistor) may also be achieved by reducing the number of holes, e.g. with hydrogen.

In certain embodiments, exposure to electromagnetic radiation (optical excitation) may generate carriers (typically to increase conductivity rather than reduce it). Beside optical excitation, and for example with a dielectric layer present, laser ablation of a semi-conductive film (or other body comprising a quantity of metal oxide material) may be possible to reduce thickness of the semi-conductive material and therefore reduce its conductivity.

Other than optical processes, in certain embodiments, opening a window in a dielectric layer covering a semi-conductive body (e.g. layer) allows introduction of extrinsic dopants and/or modification to the metal oxide material by various means, to change its conductivity. In certain embodiments, without opening a window, the dielectric layer itself can be engineered (e.g. by reducing thickness, arranging/altering composition, etc.) to promote species diffusion to an underlying or overlying body of semi-conductive material to reduce (or increase) the conductivity of that body.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects and embodiments of the present invention will now be described with reference to the accompanying drawings, of which;

FIG. 1 is a schematic cross-section of part of an electronic circuit embodying the invention;

FIG. 2 is a diagram of an inverter circuit embodying the invention;

FIG. 3 is a diagram of another inverter circuit embodying the present invention;

FIGS. 4 and 5 are schematic cross-sections of parts of two other electronic circuits embodying the invention;

FIG. 6 illustrates a step in the manufacture of another electronic circuit embodying the invention;

FIGS. 7A-7B and 8A-8B illustrate steps in two other methods embodying the invention;

FIG. 9 is a schematic cross-section of part of another electronic circuit embodying the present invention, incorporating a transistor and two resistors;

FIG. 10 illustrates a step in the manufacture of another electronic circuit embodying the invention;

FIG. 11 is a schematic cross-section of another embodiment of the invention;

FIGS. 12A-12H illustrate steps in the method of manufacturing another electronic circuit embodying the invention;

FIGS. 13A-13C, 14A-14B, and 15A-15F illustrate steps in three other methods embodying the invention;

FIGS. 16-23 illustrate parts of other electronic circuits embodying the invention;

FIGS. 24A-24H illustrate steps in another method of manufacturing an electronic circuit in accordance with the present invention;

FIG. 25 is a schematic cross-section of another electronic circuit module embodying the invention;

FIGS. 26A-26F illustrate steps in another method embodying the invention;

FIG. 27 is a schematic cross-section of another electronic circuit module embodying the invention and incorporating a resistor an a bottom gate transistor;

FIGS. 28A-28C illustrate steps in another method embodying the invention;

FIG. 29 is a schematic cross-section of another electronic circuit module embodying the invention and incorporating a resistor, bottom gate transistor, and Schottky diode;

FIGS. 30A-30E illustrate steps in another method embodying the invention;

FIG. 31 is a schematic cross-section of another electronic circuit module embodying the invention and incorporating a resistor, dual-gate transistor, and Schottky diode;

FIG. 32 is a schematic cross-section of another electronic circuit module embodying the invention and incorporating n-type and p-type transistors, and a Schottky diode;

FIG. 33 illustrates a diode OR gate embodying an aspect of the invention, and incorporating Schottky diodes and a resistor;

FIG. 34 illustrates a diode AND gate embodying an aspect of the invention, and incorporating Schottky diodes and a resistor;

FIG. 35 illustrates a diode load inverter embodying an aspect of the invention, and incorporating a Schottky diode and a transistor;

FIG. 36 illustrates a CMOS inverter circuit module embodying an aspect of the invention, and incorporating an n-channel transistor and a p-channel transistor;

FIG. 37 is a schematic cross section of a dual-gate transistor embodying the invention, and suitable for incorporation/integration in circuits and circuit modules embodying the invention;

FIG. 38 is a schematic cross section of another dual-gate transistor embodying the invention, and suitable for incorporation/integration in circuits and circuit modules embodying the invention;

FIGS. 39A-39F, 40A-40D, 41A-41C, 42A-42E, and 43A-43C illustrate a variety of methods embodying the invention, for manufacturing self-aligned dual-gate transistors;

FIG. 44 illustrates another dual-gate transistor embodying the invention, and suitable for incorporation/integration in circuits and circuit modules embodying the invention;

FIG. 45 illustrates another circuit module embodying the invention and incorporating a dual gate transistor and a resistor; and

FIG. 46 illustrates another circuit module embodying the invention.

DETAILED DESCRIPTION

Referring now to FIG. 1, this illustrates part of an electronic circuit embodying the present invention. Typically, of course, the electronic circuit will comprise numerous other components, and the interconnections between those components. However, for clarity and simplicity the figure only illustrates one transistor (1) and one resistor (2) of the circuit (which may also be referred to as a circuit module). The transistor (1) is a field effect transistor, FET, comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semi-conductive channel between the source and drain terminals. As will be well appreciated, the conductivity of the channel is controlled by application of suitable voltages to the gate terminal (13). The resistor (2) comprises a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal. Although the source and drain terminals (11, 12) and resistor terminals (21, 22) are shown in the ‘top contact’ architecture in this embodiment, i.e. partly overlying the end portions of the first body (10) and second body (20), other embodiments of the invention include circuits employing alternative terminal architectures. Furthermore, although the FET shown is of the ‘top gate’ architecture, with the gate terminal (13) positioned above the first body (10), other embodiments of the invention include circuits employing alternative FET architectures. The first body (10) of material comprises a first quantity of a metal oxide, and the second body (20) comprises a second quantity of the same metal oxide. Thus, unlike circuits known from the prior art, the circuit comprises a semiconductor channel and a resistor each formed from the same metal oxide. This enables considerable cost and/or time savings during manufacture, as the number of materials and methods used to form, pattern and define the circuit may be minimised. The first quantity (100) of metal oxide, forming the first body (10), has been formed on a first region (51) of a substrate (5) which supports at least the transistor and resistor of the circuit. The first body (10) can thus be regarded as having been formed on or over a first region of a surface of the substrate (5). The second quantity (200) of the metal oxide has been formed over a second region (52) of the substrate surface. The figure also illustrates a layer or body of dielectric material (4) which has been formed over the first and second bodies (10, 20), the source and drain terminals and the resistor terminals, and which provides the gate dielectric of the transistor (1). The gate terminal (13) has then been formed over the layer of dielectric material (4).

Although the embodiment of FIG. 1 shows the first and second bodies (10, 20) each comprising the same metal oxide, the two quantities (100, 200) of metal oxide material have been deposited under different conditions such that the first body (10) exhibits substantially semi-conductive behaviour, whereas the second body (20) exhibits substantially resistive behaviour. It will be appreciated that this difference in electrical/electronic properties can be achieved in a number of ways. For example, one of the quantities (100, 200) of metal oxide material may be deposited using a PVD technique in the presence of oxygen, whereas the other may be deposited by PVD not in an oxygen-containing environment. Alternatively, the different electrical/electronic properties of the first and second bodies (10, 20) may be achieved by processing the first and second quantities (100, 200) differently, after their initial formation/deposition stage, and such processing techniques will be described below. However, the embodiments of the invention are linked by the novel concept of the transistor channel and resistor body both comprising the same metal oxide material. In certain embodiments the transistor may be N-type (enhancement or depletion mode), whilst in others it may be P-type (enhancement or depletion mode). In certain embodiments the transistor channel and resistor body both comprise, in place of the metal oxide material, an organic material such as a polymer, a compound semiconductor, a 2D material such as graphene, or a perovskite.

In certain embodiments, the resistor (2) may be a load resistor, connected in series between one of the source and drain terminals and a voltage rail. FIG. 2 shows one such arrangement. Here the circuit module (10000) is a PMOS inverter (which may also be described as a NOT gate) with a resistive load. The resistor (2) is connected in series between the transistor source (11) and a lower voltage rail (62), which is connected to ground. The drain terminal of the transistor (12) is connected to the high voltage rail (61) (Vdd).

FIG. 3 illustrates another circuit module embodying the invention, where the resistor (2) is connected on the high side of the transistor, in series between voltage rail (61) and the drain terminal (12) of the transistor (1). This circuit can be described as an NMOS inverter circuit or circuit module, or equivalently a NOT gate with resistive load.

Referring now to FIG. 4, this illustrates a circuit module in accordance with another embodiment, where the difference in electrical/electronic properties of the first and second bodies (10, 20) has been achieved, at least in part, by depositing the first quantity (100) of metal oxide material on a source of a first dopant (71) which has been formed on a first region (51) of the substrate (5) the source of dopant (71) is arranged such that the first quantity (100) of metal oxide material may be deposited as a resistive layer, with the pre-patterned dopant selectively causing the resistive layer deposited on top of it to become semi-conductive. The second quantity of metal oxide material (200) has been deposited as a resistive layer on a second region (52) of the substrate (5) where no dopant source is present. Thus, this second quantity (200) remains resistive, rather than being converted to semi-conductive.

Referring now to FIG. 5, this shows an alternative embodiment in which a source of a second dopant (72) has been selectively provided over a second region (52) of the substrate (5). The first and second quantities (100, 200) of metal oxide material have each been deposited initially as semi-conductive layers. However, the source of the second dopant (72) has been selected such that the dopant interacts with the second quantity (200) to change its electrical properties from substantially semi-conductive to substantially resistive, and so results in the second body (20) being resistive, whereas the first body (10) remains semi-conductive, and forms the channel of the transistor (1).

Although the examples discussed above in reference to FIGS. 4 and 5 comprise a source of dopant (71, 52) beneath the semiconducting and/or resistive bodies (10, 20), a source of dopant may instead, or additionally, be provided above or to the side of one or both of those bodies. For example, a dielectric layer (4) may be a source of dopant, and/or the source and drain terminals (11, 12) and/or resistor terminals (21, 22) may be a source of dopant. The source of dopant may remain in the final circuit structure or it may be removed during processing. For example a conductive layer used to form the source and drain terminals (11, 12) and/or resistor terminals (21, 22) may be a source of dopant, and doping of the semiconducting and/or resistive bodies (10, 20) may be achieved prior to partial removal of the conductive layer during formation of the terminals, for example by patterning and etching.

It will be appreciated that whilst selective doping of the deposited quantities of metal oxide material may be used to achieve their different electrical properties, this technique may also be used in conjunction with depositing the first and second quantities (100, 200) under different conditions in certain embodiments. However, in other embodiments, the first and second quantities (100, 200) may be deposited under the same conditions, and their different electrical properties may be achieved wholly by their different subsequent processing.

Referring now to FIG. 6, this illustrates a step in the manufacture of another electronic circuit module embodying the invention. Here, the structures of the transistor (1) and resistor (2) have been formed, initially by depositing the first and second quantities (100, 200) of metal oxide material on respective portions of a surface of the substrate (5). These first and second quantities (100, 200) are initially semi-conductive. They may, for example, be formed such that they are initially in a semiconductive “normally off” state (i.e. having low conductivity). However, the step illustrated in FIG. 6 is one in which the second quantity (200) of material is being selectively exposed to electro-magnetic radiation to change its conductivity. For example, the electro-magnetic radiation may be arranged so as to anneal at least a portion of the second quantity of material and increase its electrical conductivity (e.g. relative to the low conductivity “off” state) such that it provides a resistive, rather than semi-conductive, path between its terminals. It will be appreciated that this selective exposure of just one of the bodies of metal oxide material (100, 200) may be achieved in a variety of ways. For example, radiation may be directed on to a wide portion of the circuit, with the gate terminal (13) acting as a mask to shield the first quantity of metal oxide material (100) (or at least a substantial part of it) from the effects of the radiation. Alternatively, a separate mask may be used, and/or a source of electro-magnetic radiation may be used which is able to illuminate just a small part of the circuit (for example a laser beam may be used to perform the selective annealing/processing). Techniques suitable for use in certain embodiments, to increase the conductivity of one or more of the bodies, are described in U.S. Pat. No. 10,204,683B2.

Referring now to FIG. 7, this shows two steps in another method embodying the invention. In this method, the first (100) and second (200) quantities of the metal oxide material have been deposited on separate regions of the substrate (5), and initially both are semi-conductive. For example, the first and second quantities may be formed so as to be semi-conductive, in a “normally off” condition (e.g. for IGZO devices that are n-type enhancement mode/positive threshold voltage). For such materials, since their conductivities are initially very low (because they are in the “off” state), processing arranged to increase their conductivities would be needed in order to change their electrical characteristics to resistive). The quantities of metal oxide material may, in certain embodiments, be formed as p-type “normally off” material, e.g. in SnO with a negative threshold voltage. NiO can also be tuned from p-type to n-type with an increase in conductivity. In alternative embodiments, the quantities of metal oxide material may be formed so as to be semi-conductive, in a “normally on” state (e.g. for devices that are p-type with a positive threshold voltage). For such materials, since their conductivities are initially relatively high (because they are in the “on” state), processing arranged to decrease their conductivities would be needed in order to change their electrical characteristics to resistive). Returning to the current embodiment, it will be appreciated that the separate quantities (100, 200) shown in FIG. 7a may be produced by first depositing a uniform layer, sheet, or other structure of metal oxide material, and then patterning it by any suitable means. Alternatively, the separate quantities (100, 200) may be selectively formed by any suitable technique on the substrates surface (for example by selective deposition, coating, printing, or otherwise). In the step illustrated in FIG. 7a, the second quantity (200) of metal oxide material is being selectively exposed to electro-magnetic radiation so as to increase its conductivity, and change its electrical characteristics from being substantially semi-conductive (“normally off” semi-conductive material) to being resistive. After this exposure, which can generally be regarded as processing the second quantity (200) of metal oxide material differently from the first quantity (100), we have the structure shown in FIG. 7b, where a semi-conductive body (10) of the metal oxide occupies one portion of the substrate surface, and the second body (20) of the substantially resistive metal oxide material occupies another portion. It will be appreciated that the terminal/contacts of the transistor and resistor may then be built up by suitable processing techniques, and the gate dielectric and gate terminal can also be formed. Thus, the method illustrated in FIG. 7 is one in which the first and second quantities (100, 200) of metal oxide material are processed differently before the remainder of the transistor and resistor are formed (in contrast to the method illustrated in FIG. 6, where that different processing is performed after the formation of the transistor and resistor structures).

Referring now to FIG. 8, this shows two steps in an alternative method embodying the invention. Here, in FIG. 8a, an initially uniform layer of semi-conductive material (1200) has been formed to cover an open surface of the substrate (5). Separate portions of that layer (1200) provide the first and second quantities (100, 200) of metal oxide material. FIG. 8a also illustrates that the second quantity (200) of metal oxide is being selectively exposed to electro-magnetic radiation to change its conductivity (for example to increase its conductivity, and hence decrease its resistivity, or decrease its conductivity and increase its resistivity). It will be appreciated that this selective exposure may be performed by a variety of suitable techniques, as will be apparent to the skilled person from their general knowledge in this field, as well as from the remainder of this specification. Thus, in this example the selective processing of the second quantity (200) of metal oxide is performed before the layer (1200) is patterned. FIG. 8b shows the structure resulting from patterning the layer (1200), by selectively removing portions of it to expose underlying portions of the substrate (5) surface. In particular, metal oxide material has been removed to leave just the first and second bodies (10, 20). The first body (10) corresponds to the first quantity (100) of metal oxide, as deposited as part of the initial layer (1200). The second body (20) comprises the second quantity (1200), which has also been exposed to electro-magnetic radiation, and is now resistive rather than semi-conductive. Again, after the two steps shown in FIG. 8, the further features of the transistor and resistor will be built up by suitable techniques.

Referring now to FIG. 9, this illustrates another circuit module embodying the invention. This circuit module comprises a transistor (1), a first resistor (2), and a second resistor (3). The transistor channel is provided by a first body of metal oxide material (10) formed on the first region (51) of the substrate (5). The first resistor (2) comprises a resistive body (20), formed on a second region (52) of the substrate, and the second resistor (3) comprises a third body (30) of the same metal oxide material as that forming the first and second bodies (10, 20), this third body (30) being formed on a third portion of the substrate (53). The second resistor also includes resistor terminals (31 and 32). In this embodiment, each of the first, second, and third bodies (10, 20, 30) is formed from the same metal oxide material. However, the first body (10) has been deposited under different conditions than the second body (20), so that the first body (10) is substantially semi-conductive, and the second body (20) is substantially resistive. In certain embodiments, the third body (30) may have been deposited under the same conditions as the second body (20), and may thus have the same sheet resistance. However, the geometries of the first and second resistors (2, 3) may be different such that the first and second resistors exhibit different resistances from each other. In alternative embodiments, however, the second and third bodies (20, 30) may be deposited under different conditions such that the sheet resistances of their resistive bodies (20, 30) may be different. Thus, different resistances may be achieved even though the geometries of the first and second resistors are not necessarily different from each other. Clearly, in yet further embodiments, a combination of different resistor geometries (e.g. different resistive path lengths and widths) may be employed in addition to different deposition techniques to yield resistors having different values in the electronic circuit.

Referring now to FIG. 10, this illustrates the step in the formation of another circuit module embodying the invention. In this embodiment, the circuit module again comprises a transistor (1) and first and second resistors (2, 3) formed on a common substrate (5). The transistor (1) comprises a semi-conductive channel provided by a first quantity (100) of metal oxide material. This first quantity (100) has been deposited at the same time as depositing second and third quantities (200, 300) of the metal oxide material under the same conditions. The conditions have been selected such that these first, second, and third quantities (100, 200, 300) are each initially semi-conductive. FIG. 10 illustrates a step in which conductivities of the second and third quantities (200, 300) are changed, whereas the conductivity of the first quantity (100) remains as initially deposited. In particular, electro-magnetic radiation (labelled R) is being directed at the illustrated structure, and the gate terminal (13) acts as a mask to shield the first quantity (100) of metal oxide material from that radiation and its effects. In contrast, the third quantity (300) is fully exposed to the radiation R, is annealed (or otherwise affected) by exposure to that radiation, and hence the initially semi-conductive (e.g. normally off) material of that third quantity (300) is converted to resistive material (by having its conductivity increased). The figure also shows a partial mask being used to absorb just a portion of the radiation directed towards the second quantity (200) of metal oxide material. In other words, the partial mask partially shields the second quantity of material (200) from the radiation R. Thus, the second quantity (200) of metal oxide is annealed (or otherwise affected) to a lesser extent than the third quantity (300), and hence sees a correspondingly smaller, but still significant, increase in its conductivity. Thus, the techniques illustrated in FIG. 10 are able to yield a circuit module with a semi-conductive transistor channel, and first and second resistors having different resistances, all being formed from the same metal oxide material, but processed differently to yield different electrical properties.

Referring now to FIG. 11, this shows another embodiment incorporating a transistor (1) and first and second resistors (2, 3). In this example, the semi-conductor channel (10) and the second and third resistor bodies (20, 30) have all been deposited at the same time from the same metal oxide material under the same deposition conditions, such that the first, second, and third quantities (100, 200, 300) of metal oxide material are each initially semi-conductive. However, the second quantity (200) has been formed on a second dopant source (72), and the third quantity (300) has been formed on a third dopant source (73). The dopant materials and/or their concentrations have been selected such that they result in the second and third bodies (20, 30) being differently doped, and hence exhibiting different resistances. No dopant is provided to the first quantity of metal oxide material, which accordingly simply provides the first body (10) of the transistor (1).

Referring now to FIG. 12, this shows steps in another method embodying the invention in which the first and second quantities (100) of metal oxide material are deposited at different stages in the manufacturing method, and under different conditions to achieve different conductivities of the bodies (10, 20) formed from the same metal oxide material. FIG. 12a shows how an initial layer (1001) of metal oxide material has been formed over a substrate (5), which in certain embodiments is flexible, and in alternative embodiments is rigid. The substantially uniform layer (1001) comprises the first quantity (100) of metal oxide material that will form the basis of the channel of the transistor. The structure shown in FIG. 12a is then patterned by suitable means to yield the structure shown in FIG. 12b. Thus, portions of the layer (1001) have been selectively removed to leave just the first quantity (100) of metal oxide material that will form the first body (10). It will be appreciated that a wide variety of techniques may be used to perform this patterning, for example techniques involving one or more of the following: lithography, photolithography, imprinting, nano-imprinting. In the illustrated method, a layer of conductive material (81) is then formed over the first body (10) and substrate (5). Using suitable techniques, that conductive layer (81) is patterned to form the source and drain terminals (11 and 12) and first and second terminals (21, 22) of the resistor. A layer of resist material (9) is then formed over the terminals/contacts and semi-conductive channel, to yield the structure shown in FIG. 12d. Again, by using suitable techniques, a window (90) is formed in the resist layer (9), exposing at least part of the resistor terminals (21, 22) and a portion of the substrate surface extending between them. Then, FIG. 12f illustrates the formation (by deposition or otherwise) of a second layer (2001) of the same metal oxide material as the first layer (1001), but under different conditions such that the second layer (2001) exhibits resistive behaviour rather than semi-conductive behaviour. This second layer (2001) includes the second quantity (200) of metal oxide material, which forms the second body (20) of the resistor, providing a resistive path between the resistor terminals (21, 22). Thus, in this example the resistor has bottom contacts i.e. its terminals are formed directly on the substrate surface and the resistive body (20) is formed so as to overlap those resistor terminals on top. FIG. 12g illustrates a further step, where the remaining resist material of the layer (9) has been removed and FIG. 12h illustrates the final structure resulting from formation of the dielectric layer (4) over the structure shown in FIG. 12g, and then formation of a gate electrode (13) over the transistor channel body (10). Thus, in the embodiment illustrated in FIG. 12, the channel body (10) and resistor body (20) have been formed from different layers of metal oxide material, those different layers having been formed under different conditions such that the channel (10) exhibits semi-conductive behaviour and the resistor body (20) exhibits resistive behaviour.

Also, in the embodiment shown in FIG. 12, the resistor body (20) has been formed after formation of the conductive contacts of both the transistor and resistor.

Referring to FIG. 13, this shows an alternative technique where the first and second bodies are formed at different times, but before formation of the conductive contacts. FIG. 13a shows the initial formation of a first layer (1001) of metal oxide material including the first quantity (100), on top of the substrate (5). By suitable techniques this layer (1001) is patterned to yield the structure shown in FIG. 13b, comprising the first quantity (100) of metal oxide material on the substrate. Then, in FIG. 13c, the second quantity of metal oxide material (200) has been formed on a different region of the substrate, after formation of the first quantity (100).

Referring now to FIG. 14, this shows an alternative method in which the second quantity of metal oxide material (200) is formed initially on the substrate surface. Then, as illustrated in FIG. 14b, the first quantity (100) is formed on a different portion of the substrate, after forming the second quantity (200).

Referring now to FIG. 15, this illustrates yet another method of forming an electronic circuit module embodying the invention. As shown in FIG. 15a, a layer (2001) of metal oxide material is first formed on the substrate (5), that layer (2001) comprising the second quantity of metal oxide material (200) which will form the body of the resistor. Using suitable techniques, that layer (2001) is patterned, to yield the structure shown in FIG. 15b. This second quantity (200) has been formed under conditions such that the metal oxide material exhibits resistive behaviour. Then, as shown in FIG. 15c, a layer of resist material (9) has been formed. Then, as shown in FIG. 15d, a window (90) has been formed in the resist layer (9), and a layer (1001) of metal oxide material has been deposited, so as to cover the portion of substrate exposed by the window (90) with a first quantity of metal oxide material (100). The formation conditions of the layer (1001) are such that this first quantity (100) is substantially semi-conductive, in contrast to the resistive second quantity (200), even without any subsequent processing. The remaining resist material is then removed by suitable techniques, and a layer of conductive material (81) is formed on top of the underlaying structure, to yield that illustrated in FIG. 15e. That conductive layer (81) is then patterned to yield the structure shown in FIG. 15f, comprising the transistor source and train terminals and the first and second resistor terminals (21, 22). It will be appreciated that the other components of the circuit module may then be built up on top of this structure, using appropriate techniques.

Referring now to FIG. 16, this illustrates part of another circuit module embodying the invention. In this example, each of the first and second bodies (10, 20) is being formed from a layer, sheet, or film of metal oxide material. In this example, the thickness of that layer, film or sheet is T. Thus, the first and second bodies (10, 20) each have the same thickness. However, the semi-conductive channel provided by the first body (10) has length L1, and the resistive path provided by the second body (20) has length L2, where L1 is different from L2. In certain alternative embodiments, however, it will be appreciated that the channel and resistive path may have the same length as each other.

Referring now to FIG. 17, this illustrates yet another embodiment, where the first body (10) has thickness T1, and the second body (20) has a different thickness T2. Again, the length L1 of the channel and the length L2 of the resistive path are different.

It will be appreciated from FIGS. 16 and 17 that, in certain embodiments, the first and second bodies (10, 20) are formed on different respective areas of a surface of the substrate (5), and then the contacts or terminals (11, 12, 21, 22) are formed subsequently, so as to overlap upper surfaces of the first and second bodies (10, 20). FIG. 18 illustrates an alternative embodiment, in which the source and drain terminals (11, 12) and first and second resistor terminals (21, 22) have been formed on the substrate (5) before formation of the first and second bodies (10, 20). Thus, the first body (10) partially overlaps the source and drain terminals (11, 12) in this example, and the second body (20) also partially overlaps upper surfaces of the resistor terminals (21 and 22). A gate dielectric (4) has been formed over the first body (10) and terminals (11, 12), and a gate terminal (13) has been formed on top of the gate dielectric. Thus, it will be appreciated from FIG. 18 that the first body (10) and/or second body (20) are not necessarily planar in all embodiments of the invention. This is further illustrated by FIG. 19, which shows a circuit module embodying the invention where the first body (10) has been formed initially on a surface of the substrate (5), under conditions such that its behaviour is semi-conductive. The source and drain terminals (11, 12) and first resistor terminal (21) have then been formed at the same time, with the source and drain terminals (11, 12) partially overlapping upper surfaces of the first body (10). The first resistor terminal (21) is formed directly on a portion of the surface of the substrate (5). The second body (20) has been formed in a subsequent step (i.e. after formation of the first body (10)), under conditions such that it exhibits resistive behaviour, and that second body (20) covers at least part of the upper surface of the first resistor terminal (21) and a portion of the substrate surface (5) adjacent that first terminal (21). The second resistor terminal (22) has been formed later, and sits on top of the second body (20). Thus, the resistor body (20) is again not simply planar. In this example, it is stepped, and the first and second resistor terminals (21, 22) have been formed in different steps (or different sequences of steps) i.e. from different conductive layers. Thus, the resistor terminals, in this example, are not formed at the same time (or in the same processing step or sequence of steps) as each other.

Referring now to FIG. 20, this shows an alternative circuit embodying the invention where the transistor (1) has a bottom gate structure, and the resistor has bottom contacts. It will be appreciated that the structure shown in FIG. 20 may be formed by a method in which the gate and resistor contacts (21 and 22) may be formed at the same time, for example by the patterning of an initially continuous layer of conductive material formed on a surface of the substrate (5), the resistive body (20) may then be formed form metal oxide material under conditions such that it exhibits resistive behaviour. Then, the gate dielectric may be formed before forming the channel body (10) above the gate, this time under conditions such that the channel body (10) is semi-conductive rather than resistive. The source and drain contacts (11, 12) may then be formed, by suitable techniques. In this example the first body (10) and second body (20) are not coplanar, however their respective planes of orientation are parallel to each other.

Referring now to FIG. 21, this illustrates an alternative circuit module embodying the invention, where the transistor (1) has a bottom gate structure, and the resistor has overlapping top contacts (21, 22). To form the structure of FIG. 21, the gate terminal may first be formed. Then the resistor body (20) may be formed, before or after formation of the gate dielectric. The transistor body (10) is then formed after the resistor body (20), and the source and drain terminals (11, 12) and resistor terminals (21, 22) may be formed in different steps or at the same time as one another, for example by patterning a layer of conductive material.

Referring now to FIG. 22, this shows an alternative embodiment in which the first and second quantities (100, 200) of metal oxide material have been formed at the same or different times, under the same or different processing conditions. However, the first quantity (100) has been formed over a first dopant source (71) and the second quantity (200) has been formed over a second dopant source (72). The dopant materials and/or their concentrations have been selected such that the interaction of the first quantity of metal oxide material (100) with the first dopant source (71) results in the first body (10) being semi-conductive, and the interaction of the second quantity of metal oxide material (200) interacts with the second dopant source (72) such that the second body (20) provides a resistive current path between the terminals (21, 22).

FIG. 23 illustrates a similar embodiment in which the substrate (5) itself has been doped selectively in different regions to provide the different dopant sources (71 and 72) which interact with the first and second quantities (100, 200) to yield a semi-conductive channel and resistive body respectively.

Referring now to FIG. 24, the is illustrates steps in a further method embodying the invention. In step 24a, a layer of metal oxide material (1200) has been formed on a surface of the substrate (5), that layer (1200) comprising first and second quantities (100, 200) of metal oxide material. That structure is then patterned by suitable technique to yield the structure shown in FIG. 24b, a layer of conductive material (81) is then deposited over that structure to yield the structure shown in FIG. 24c, and that layer (81) is then patterned by suitable techniques to yield the structure shown in FIG. 24d, with portions of the previous conductive layer (81) forming the resistor terminals (21, 22) and source and drain terminals (11 and 12), each of those terminals partly overlapping an upper surface of the respective quantity (100, 200) of metal oxide material. A layer of dielectric material (4) is then formed to yield the structure shown in FIG. 24e, and a second layer of conductive material (82) is formed on top, that layer (82) comprising the material which will form the gate terminal (13). That second layer is then patterned by suitable techniques to yield the structure shown in FIG. 24g, with the gate terminal (13) above the semi-conductive channel body (10). At the stage illustrated in FIG. 24g, each of the quantities (100, 200) may be substantially semi-conductive (e.g. “normally off” semiconductor material), FIG. 24h shows a subsequent step in which the structure of FIG. 24g is exposed to electro-magnetic radiation R to thermally anneal (or otherwise affect) just the second quantity (200) of metal oxide material, increasing its conductivity and changing its properties from semi-conductive (normally off) to resistive. The gate (13) acts as a mask or shield, and shields the first quantity (100) from the radiation R such that it is substantially unaffected by the radiation and hence the transistor body (10) exhibits semi-conductive behaviour rather than resistive. Advantageously, this embodiment is one in which the metal oxide material for the transistor channel and resistor body may be deposited at the same time. The difference in eventual electrical properties of the channel and resistor body are achieved by the different subsequent processing.

It will be appreciated that although certain embodiments provide flexible electronic circuits, such as flexible ICs, and/or low cost circuits, other embodiments may provide circuits, such as ICs, that are not flexible, nor necessarily low cost, for example those manufactured on rigid substrates or part-complete systems.

Any suitable material(s) may be used as a substrate (5), which may be composed from one or more layers of such materials. The substrate (5) may be flexible, comprising any one or more materials from the following list: Glass (rigid or flexible); polymer (e.g. polyethylene naphthalate, polyethylene terephthalate; polymethyl methacrylate; polycarbonate, polyvinylalcohol; polyvinyl acetate; polyvinyl pyrrolidone; polyvinylphenol; polyvinyl chloride; polystyrene; polyethylene naphthalate; polyethylene terephthalate; polyimide, polyamide (e.g. Nylon); poly(hydroxyether); polyurethane; polycarbonate; polysulfone; parylene; polyarylate; polyether ether ketone (PEEK); acrylonitrile butadiene styrene; 1-Methoxy-2-propyl acetate (SU-8); polyhydroxybenzyl silsesquioxane (HSQ); Benzocyclobutene (BCB)); Al2O3, SiOxNy; SiO2; Si3N4; UV-curable resin; Nanoimprint resist; photoresist; polymeric foil; paper; insulator-coated metal (e.g. coated stainless-steel); cellulose.

Any suitable material(s) may be used as a layer of dielectric material (4), which may be composed from one or more layers of such materials. Examples of suitable materials include: Metal oxides such as Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5; metal phosphates such as Al2POx; metal sulphates/sulphites such as HfSOx; metal nitrides such as AlN; metal oxynitride such as AlOxNy; inorganic insulators such as SiO2, Si3N4, SiNx; spin on glass (such as polyhydroxybenzyl silsesquioxane, HSQ), polymeric dielectric materials (such as Cytop, a commercially available amorphous fluoropolymer), 1-Methoxy-2-propyl acetate (SU-8), benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinyl pyrrolidone, polyvinylphenol, polyvinylchloride, polystyrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone; UV curable resins; Nanoimprint resists; or photoresists. The dielectric material may have a relatively low dielectric constant (low-K, e.g. Cytop, HSQ, parylene) or a relatively high dielectric constant (high-κ, e.g. Ta2O5, HfO2).

Any suitable material(s) may be used to form the transistor source, drain and gate terminals (11, 12, 13) and the resistor terminals (21, 22), any of which may be composed from one or more layers of such materials. Examples of suitable materials include: Metals, such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys, such as MoNi, MoCr, AlSi; transparent conductive oxides, such as ITO, IZO, AZO; metal nitrides, such as TiN; carbon materials, such as carbon black, carbon nanotubes, graphene; conducting polymers, such as polyaniline, PEDOT:PSS; or semiconductor material.

Any suitable material may be used to form the first body (10) of material providing a controllable semi-conductive channel and the second body (20) of material providing a resistive current path, and any other further semi-conductive and resistive bodies in the circuit. The first body (10) or the second body (20) or both bodies may be composed from one or more layers of such materials. Examples of suitable materials include metal oxides, such as ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO), AlZnO (AZO). Other suitable materials may include organic materials such as polymers, compound semiconductors, 2D materials such as graphene, and perovskites. A suitable material is one that may be used to form a resistive body or a semi-conductive body depending on its stoichiometry, deposition, processing and/or doping. The first body (10) and second body (20) may both consist of the same material. In other embodiments either the first body (10) or the second body (20) or both bodies (10, 20) may each comprise an additional material that may be taken from the above list or may be a different type of material such as a conductor, an insulator or a different type of semiconductor. Thus, another aspect of the invention provides an electronic circuit (or circuit module) comprising a transistor and a resistor, the transistor comprising a source terminal, a drain terminal, a gate terminal, and a first body providing a controllable semiconductive channel between the source and drain terminals, the resistor comprising a first resistor terminal, a second resistor terminal, and a second body providing a resistive current path between the first resistor terminal and the second resistor terminal, wherein said first body comprises a first quantity of a material and said second body comprises a second quantity of said material. Another aspect provides a method of manufacturing such a circuit, comprising forming said first body and forming said second body.

It will also be appreciated from the above-description that certain embodiments of the invention provide improvements to unipolar (i.e. based on either p-type or n-type semiconductors) circuits (e.g. FlexICs) to extend their capabilities for low cost processing, sensing, communication and other applications. The approach is based on the integration of resistors into the circuits (e.g. FlexICs) along with the unipolar transistors. These resistors, in certain embodiments, have some or all of the following properties:

1. Used as a transistor load they enable FlexICs to incorporate logic circuits of greater complexity and efficiency

2. Used in analogue circuits they enable timers and other essential functions in, for example, RF circuits

3. They exhibit sheet resistance values of between approximately 50 kΩ/□ and 10 MΩ/□

4. They may be fabricated using established thin-film deposition techniques, e.g. PVD, CVD, etc.

5. They do not require post-deposition processing of either long duration or high energy consumption

6. They have a high optical transmittance, and may be substantially transparent

7. They are formed from a material composed of the same elements as those in the semiconductor channel of the transistors (e.g. FlexIC's transistors)

8. They are formed from a metal oxide (e.g. NiO, SnO, IGZO)

9. They are formed from Indium Gallium Zinc Oxide (IGZO)

10. They are located in one or more layers of the FlexIC

11. They are located in either the same or different layer(s) as the semiconductor channel of the FlexIC's transistors

The present inventors are aware that electronic properties of metal oxides have been investigated with some intensity relatively recently. Much of this work has been in the context of (i) very low resistivity, for application as transparent conducting oxides such as indium tin oxide, or (ii) very high resistivity, for semiconductor applications. The present inventors appreciate that electromagnetic irradiation, such as from a UV laser or lamp, may reduce the resistivity of a metal oxide semiconductor material from the order of 10⁹Ω/□ to around 10⁵Ω/□. Accordingly, certain embodiments of the present invention use electromagnetic irradiation to modify resistance for the purposes of setting the resistance of one or more resistors in a circuit (e.g. an IC).

Resistors in embodiments of the present invention are formed from metal oxides. Their resistivities may be determined primarily by the stoichiometry of the metal oxides, by the techniques and conditions used to deposit and process them, and by the incorporation of elements from neighbouring materials in the IC structure. For example, a pre-patterned dopant or one present in a layer above or beside the resistor may selectively cause the metal oxide semiconductor film to become resistive after deposition and processing:

By depositing a quantity of initially semiconductive material on top of a dopant (or source of said dopant), the dopant may then change the semiconductive film to a resistive film. This technique is used in certain embodiments.

The dopant may donate atoms, e.g. O, H, F, N, Y, to the initially semiconductive layer, or alternatively the dopant may accept such atoms from the initially semiconductive layer to leave vacancies in the material (and so increase its conductivity/reduce its resistivity). Alternatively a metal oxide film may be deposited as a resistive layer with a pre-patterned dopant selectively causing the resistive layer to become semiconductive.

In another example a semiconducting film may be formed from a material having one stoichiometry (molar proportion of elements) whilst a resistive film may be formed from the same material having a different stoichiometry.

Thus, to achieve a semiconductive channel and a resistive body, each comprising the same metal oxide, the respective quantities of metal oxide material may exhibit different stoichiometries and/or may be formed/deposited under different conditions and/or may be processed differently after being formed. Deposition/processing examples of how to differentiate the resistive bodies from semiconductor channels comprising the same metal oxide material can include the following, either individually or in combinations, and for a body comprising more than one layer of material the deposition/processing may be different for each layer:

Deposition (e.g. of IGZO) by PVD or by ALD (atomic layer deposition) in the presence, absence or different concentrations of O2, N2, F, H2

Deposition by PVD vs ALD

By thermal annealing, e.g. by annealing only resistive bodies or semiconductor channels, or annealing both resistive bodies and semiconductor channels in different conditions of temperature and/or presence of air, O2, N2, Ar, H2, forming gas, etc.

By plasma treatment, e.g. CF4, Ar, O2, N2, NF3, H2, during or after deposition

By UV laser or excimer lamp (as noted above)

By controlling the thicknesses of the semiconductive channel and the resistive body.

It will be appreciated that although the above-mentioned techniques, materials, and configurations have been described in connection with the manufacture of circuit modules incorporating at least one transistor and at least one resistor, they may also be applied, mutatis mutandis, in the manufacture of alternative circuit modules incorporating at least one resistor and at least one Schottky diode, at least one transistor and at least one Schottky diode, or at least one each of a resistor, transistor, and Schottky diode.

Referring now to FIG. 25, this shows another circuit module embodying an aspect of the invention and incorporating a transistor 1 and resistor 2. The transistor in this example is a top-gate transistor, and the resistor is top-contact, i.e. with upper surfaces of its terminals 21, 22 exposed for further connections. The structure is generally the same as the embodiment shown in FIG. 1. The substrate 5 is here referred to as an underlayer and it will be appreciated that this may comprise one or more layers, or may indeed comprise a complex structure (incorporating further electronic components and/or circuits for example) upon which the resistor 2 and transistor 1 have been formed. The gate 13 in this example is stepped, partially filling a recess in the dielectric layer 4 above the body 10 forming the semi-conductive channel (which in this example is an n-type semiconductor).

FIG. 26 illustrates steps in a method of producing a circuit module such as that shown in FIG. 25. FIG. 26A illustrates a first step in which a quantity of metal oxide material 200 is formed on the underlayer 5 under conditions such that it is generally resistive in its electrical behavior. This quantity 200 thus forms the resistor body 20. Next, as shown in FIG. 26B, a further quantity 100 of metal oxide material is deposited on the upper surface of the underlayer, this time under conditions such that the metal oxide material is semi-conductive, and forms the body 10 of the transistor. Next, as shown in FIG. 26C, a layer of conductive material 81 is formed over the first and second bodies 10, 20 and the upper surface of the substrate 5, and then that conductive layer 81 is patterned using a suitable technique to yield the structure shown in FIG. 26D which includes the transistor and resistor terminals 11, 12, 21, 22. Next a layer of dielectric material 4 is formed over the underlying structure, as shown in FIG. 26E and then the gate terminal 13 is formed over the semi-conductive channel 10, as shown in FIG. 26F. Also, the dielectric layer 4 has been processed so as to exposure upper surfaces of the resistor terminals 21, 22.

Whilst this top-contact, top-gate structure is appropriate for use in certain embodiments, there can be issues with the patterning of multiple metal oxide (e. g. IGZO) layers, and there may be the need to separate production of the semi-conductive body 10 and resistor body 20. Also, in certain examples the semi-conductive material 10 may interact with the underlayer and this can be undesirable. Furthermore, it is desirable for certain applications to integrate Schottky devices in circuit modules incorporating a resistor and/or a transistor, and this may require the provision of a bottom-electrode. The integration of Schottky devices in circuit modules embodying certain aspects of the invention is desirable in order to produce lower footprint near field communication (NFC) circuits, to produce lower power circuits, to produce higher speed circuits (e. g. circuits able to operate at UHF frequencies), and also to take into account ESD protection factors.

With these considerations in mind, FIG. 27 illustrates another circuit module embodying an aspect of the invention. This can be regarded as a top-contact, bottom-gate module. Here, the transistor gate 13 has been formed on an upper surface of the substrate 5, as has the resistor body 20. The resistor body can be formed before or after the bottom gate 13, and this may enable the processing on the resistor body to be minimized. A first layer of dielectric material 41 has been formed over the gate 13, this layer 41 also covering the upper surface of the resistor body 20. The semi-conductive body 10 of the transistor 1 has been formed on this first dielectric 41, and then the transistor source and drain terminals 11, 12 have been formed so as to partially overlap the upper surface of the semi-conductive body 10. A further layer of dielectric material 42 has been formed, but leaves upper surfaces of the transistor and resistor terminals 11, 12, 21, 22 exposed for further connections.

Although the n-type semi-conductive channel 10 in this figure is illustrated as a single body, it will be appreciated that in certain embodiments this semi-conductive body 10 can be engineered, for example, to include a graded channel or a plurality of different layers (for example, high-low resistance layers etc.). In other words, the semi-conductive body 10 in this embodiment, and indeed in other embodiments, may consist of two or more layers of semi-conductor, each having tailored conductivity, mobility, carrier concentration etc.

The transistor source and drain terminals 11, 12 may be produced by various suitable techniques, for example, including masking and etching, or patterning a resist layer, forming windows, depositing conductive material inside the windows, and then lifting off remaining resist material. The second dielectric material may be patterned using various suitable techniques. Furthermore, although a simple lateral resistor 2 is shown in the figure, other forms of resistor may be incorporated in alternative circuit modules embody the invention, (for example, vertical resistors, resistors with terminals offset both horizontally and vertically, etc.).

FIG. 28 illustrates some of the steps in the formation of a circuit module such as that shown in FIG. 27. FIG. 28A illustrates the provision (by deposition or otherwise) of a quantity 200 of metal oxide material on a nominal upper surface of the substrate 5. This quantity 200 may be provided in an initial state in which it exhibits generally semi-conductive behavior. FIG. 28A illustrates, with the large arrow, an exposure of that body 200 of initially semi-conductive material to electromagnetic radiation of suitable frequency to change the electrical properties of the body from semi-conductive to resistive, as described above in relation to other embodiments. Then, FIG. 28B illustrates a further stage in the method in which resistor terminals 21, 22 have been formed at the same time as forming the bottom gate electrode 13. Thus, in this example the resistor terminals 21, 22 and gate terminal 13 are formed from the same conductive material (e. g. a metal).

FIG. 28C illustrates a later stage in the method, in which the first dielectric layer 41 has been formed over the resistor and gate electrode, the semi-conductive body 10 has been formed on the first dielectric 41, the transistor source and drain electrodes 11, 12 have then been formed, and then a second dielectric layer 42 has been formed over the underlying structure. In certain examples the upper dielectric layer 42 may be left in this form or, alternatively, it may be patterned to exposure surfaces of one or more of the previously underlying terminals.

As described above, for certain applications is it desirable to integrate a Schottky diode in an integrated circuit comprising at least on transistor and/or at least one resistor as described above. It will be appreciated that the above teachings regarding the production of electronic circuit modules comprising at least one resistor may be applied to the production of circuit module embodying other aspects of the invention and incorporating a Schottky diode and at least one transistor and/or at least one resistor, making the appropriate changes.

FIG. 29 illustrates one such circuit module embodying the invention. This circuit module is similar to that illustrated in FIG. 27 (i. e. a top-contact, bottom-gate module) but, additionally, incorporates a Schottky diode 3000. This Schottky diode comprises a first electrode 3001, which in this example is formed of an upper surface of the substrate 5, like the bottom-gate 13 of the transistor 1. The diode includes a body of semi-conductive material 2010 connected between the first electrode 3001 to second electrode 3002. The interface or junction between the first electrode 3001 and the diode body 3010 is arranged to provide a Schottky (rectifying) contact, and the interface or junction between the diode body 3010 and the upper electrode 3002 is arranged to be ohmic. However, it would be appreciated that the alternative embodiments the upper contact may be a rectifying contact, and the lower contact may be ohmic, to suit requirements. Again, the circuit module comprises a first dielectric layer 41, and a second dielectric 42 which is arranged so that no upper surface of either of the transistor body 10 or diode body 3010 is exposed.

Referring now to FIG. 30, this illustrates steps in the manufacture of a circuit such as that shown in FIG. 29. In FIG. 30A the resistor body 20 has been formed on an upper surface of the substrate 5, and a conductive layer 81 has been formed over the top. That conductive layer has then been patterned to yield the resistor terminals 21, 22, the gate terminal 13 and the diode lower electrode 3001. Then, in FIG. 30C, a first dielectric layer has been formed over the underlying structure and patterned to form a window exposing part of an upper surface of the diode lower electrode 3001. In this example the conductive layer 81 consists of titanium (Ti). In the step illustrated in FIG. 30C the exposed upper surface of the Ti electrode 3001 is oxidized by baking in air at 200° c. to create TiOx. That TiOx layer is illustrated as 3011 in the figure. FIG. 30D illustrates a further stage in the manufacturing process, in which the diode body 3010 has been formed by depositing a further quantity 3100 of metal oxide material so as to fill the window in the dielectric layer 41 and extend along an upper surface of that layer 41. The interface between the metal oxide material of the diode body 3010 and the oxidized surface of the lower electrode 3001 provides the rectifying Schottky contact. A further layer of conductive material 810 has been formed over the structure and that layer is then patterned to yield the structure illustrated in FIG. 30E, with remaining portions of that further conductive layer 810 providing the transistor terminals 11, 12 and upper terminal 3002 of the Schottky diode. Thus, in this embodiment, the diode body 3010 has been formed at a different time to the formation of the resistor body 20 (in this case after). The diode body 3010 may be formed at the same time as forming the transistor body 10 (e.g. under the same process conditions), or may be formed at a different time to the transistor body (e.g. under different process conditions, if the diode and transistor bodies are required to have different electrical properties, or if separate formation is advantageous/desirable for other reasons).

It will be appreciated from FIGS. 29 and 30 that certain embodiments of the invention comprise a Schottky diode incorporating both a vertical and horizonal offset between its terminals, but it will also be appreciated that certain alternative embodiments may incorporate Schottky diodes having purely vertical or purely horizontal structures as is known in the art. In certain embodiments it is possible to repair resistive TIOX on an electrode surface, for example, using CF₄/O₂or a Cl etch.

Referring now to FIG. 31, this shows another circuit module embodying the invention, this time comprising a top-contact, dual-gate transistor 1, a Schottky diode 3000 and a resistor 2. It is similar to the embodiment shown in FIG. 29, but the transistor 1 comprises an additional top-gate 132 (the previous gate now being labelled as the lower gate 131). Thus, the conductive properties of the semi-conductive body 10 can be controlled by application of suitable voltages to both the lower gate 131 and the upper gate 132. Such embodiments find particular application in analogue circuits, and provide additional control of transistor threshold-voltage, by provision of the extra gate. The circuit may be arranged, in use, such that the same voltage is applied to both the lower and upper gates 131 and 132, or separate voltages may be applied to the top gate and the bottom gate. The provision of the dual-gate transistor can enable the higher mobility to be achieved, and enable the transistor to conduct larger currents.

Referring now to FIG. 32, this illustrates yet another circuit module embodying the invention, comprising a Schottky diode 3000, a first transistor 1A having an n-type semi-conductive body/channel 10A, and a second transistor 1B having a p-type semi-conductive body/channel 10B. Although the illustrated module incorporates transistors having just a single gate each, it will be appreciated that additional gates may be employed in one or both of the transistors 1A, 1B, making them dual-gate transistors. In this example, the p-type semi-conductive layer 10B has been formed partly in contact with an upper surface of the substrate 5, partially overlapping terminals 11B and 12B of the second transistor 1B. The gate 13A of the first transistor 1A is also formed on that upper surface of the substrate 5, as is the first electrode 3001 of the diode 3000. These various electrodes may all be formed at the same time, for example, from a common sheet of conductive material, or may be formed in different steps, for example, if the conductive material required for the diode first electrode 3001 is different from the material required for the transistor electrode. It will be appreciated that the circuit module illustrated in FIG. 32 represents the provision of CMOS technology together with a Schottky diode in an integrated circuit.

FIGS. 33-35 illustrate various electronic circuits or circuit modules embodying the invention and incorporating different combinations of Schottky diodes and/or resistors and/or transistors.

Referring now to FIGS. 33 to 35, it will be appreciated that various circuits and circuit modules embodying the present invention may comprise combinations of at least one transistor and/or at least one resistor and/or at least one Schottky diode, for example in the form of flexible integrated circuits/modules. Such circuits/modules include logic gates. Such logic gates may comprise one or more diodes, either as the sole active elements (e.g. in “diode logic”) or in combination with transistors (“diode-transistor logic”). Two diode logic examples embodying the invention and incorporating Schottky diodes are shown in FIGS. 33 and 34. FIG. 33 illustrates a diode OR gate embodying an aspect of the invention, and comprising two diodes, each having a respective anode connected to a respective input terminal, and a respective cathode connected to an output terminal. The output terminal is connected to ground via a resistor. FIG. 34 illustrates a diode AND gate embodying an aspect of the invention, and comprising two diodes, each having a respective cathode connected to a respective input terminal, and a respective anode connected to an output terminal. The output terminal is connected to a positive supply rail 1000 via a resistor. The use of Schottky diodes in logic gates (as in these embodiments, for example) may provide advantages of fast response and small voltage drop, as well as other benefits.

Another circuit module embodying the invention is a diode load inverter, as illustrated in FIG. 35. A conventional unipolar inverter typically places a transistor switch and resistor load between high and low voltage references. The inverter input is connected to the transistor gate terminal, and the inverter output is connected to the junction of the transistor and the resistor. In a diode load inverter, the resistor load is replaced by a diode, for example as shown in FIG. 35. The use of a Schottky diode as a load in a diode load inverter, such as shown in FIG. 35, may provide benefits of fast switching, low voltage drop and low power consumption, among others.

Referring now to FIG. 36, this illustrates a basic CMOS invertor which may be implemented in an integrated circuit having the structure of the first and second transistors 1A, 1B as illustrated in FIG. 32.

As will be appreciated from the above, certain circuit modules embodied in the invention incorporate dual-gate transistors, having top and bottom gates on either side of a semi-conductive channel or body 10. Indeed, a further aspect of the present invention provides a dual-gate transistor and an embodiment of this aspect is illustrated in FIG. 37. Here, the transistor 1 comprises a bottom gate 131 formed on an upper surface of an underlying substrate of structure 5. In certain embodiments, this bottom gate 131 may be a conductive feature already present on the underlying structure. A first layer or body 41 of dielectric material is formed over the bottom gate 131, and then a layer or body of initially semi-conductive material has been formed over that first dielectric layer. A central portion of that layer of semi-conductive material forms the transistor body or channel 10. Furthermore, suitably processed portions of that initially semi-conductive layer that extend beyond the edges of the underlying lower gate terminal 131 provide the source and drain terminals 11, 12 of the device. In other words, the edges of the semi-conductive channel 10 (and hence the edge of the source and drain terminals 11, 12) coincide with the edges of the underlying lower gate terminal 131 such that there is no overlap between the source on drain terminals 11, 12 and lower gate 131 when viewed from above, so as to minimize any parasitic capacitors between the source and drain terminals and the gate terminal 131. In other words, the projections of the source and drain terminals 11, 12 onto the nominal horizontal plane (which generally corresponds to the plane of the upper surface of the substrate 5 in this figure) do not overlap the projection of the lower gate terminal 131 onto that horizontal plane. In this embodiment, the source and drain terminals 11, 12 have been extended by the provision of contacts 111 and 121 formed from metallic material and which partially overlap each of the source and drain terminals 11, 12. A second layer of dielectric material 42 has been formed over the semi-conductive channel 10 and the extended source and drain electrodes, and an upper gate terminal 132 has been formed on top of that second dielectric layer 42. The upper gate 132 is aligned with both the edges of the semi-conductive channel 10 and the edges of the lower gate 131, and has the same projection onto the horizontal plane as the lower gate electrode 131. In other words, the upper and lower gates are aligned and have the same footprint on the horizontal plane. Furthermore, as the source and drain terminals 11, 12 do not overlap the lower gate terminal 131, they also do not have any overlap with the upper gate terminal 132. Thus, any parasitic capacitance between the upper gate electrode 132 and the source and drain terminals is also reduced.

It will be appreciated, therefore, that the dual-gate transistor illustrated in FIG. 37 is aligned, in the sense that its lower gate electrode 131, semi-conductive channel 10, and upper gate electrode 132 form an aligned stack, with no overlap between the source and drain terminals and either gate terminal when viewed from a direction normal to the nominal horizontal plane. This alignment may be achieved in a variety of ways. In certain embodiments, this alignment between the source and drain electrodes in 11 and 12 and the lower gate electrode 131 is achieved by forming the source and drain electrodes 11, 12 by irradiating those corresponding portions of the initially semi-conductive layer with electromagnetic radiation of the appropriate frequency from below, i.e. through the substrate 5, such that the radiation affects those irradiated potions but the central portion forming the semi-conductive channel 10 is shielded from that radiation by the lower gate terminal 131 (which of course must be opaque to the radiation of the desired wavelength/frequency).

Referring now to FIG. 38, this shows another dual-gate transistor embodying an aspect of the invention. This transistor has similar structure that shown in FIG. 37, but here the underlying substrate 5 is a multi-layer structure, with the lower gate electrode 131 again being provided on a nominal upper surface of that structure 5. A quantity 100 of initially semi-conductive material has been deposited over the lower dielectric layer 41 and lower gate 131, and again portions of that layer extending laterally beyond the edges of the underlying lower gate electrode 131 have been suitably processed so as to change their electrical properties from semi-conductive to resistive, thus forming the source and drain terminals 11, 12. In this example a second layer of dielectric material 42 partially covers the source and drain terminals 11, 12 and all of the semi-conductive channel 10, and an upper gate electrode 132 is formed on top of that second dielectric 42, this second, upper gate terminal 132 again being aligned with the lower gate terminal 131 so as to reduce parasitic capacitance.

Referring now to FIG. 39, this illustrates steps in a method suitable for producing a dual-gate transistor embodying the invention, the method also embodying an aspect of the invention. In FIG. 39A, a substrate/structure 5 is provided, having a nominal upper surface 51 on which a lower gate terminal is provided, for example, formed from a suitable metal, then, as show in FIG. 39B, a stack of layers is formed over the lower gate terminal 131, that stack comprising a first dielectric layer 41 a layer of semi-conductive material 100 (e. g. formed from a metal oxide) and a upper layer of dielectric material 42. This structure is then exposed to electromagnetic radiation of an appropriate frequency (for example, UV radiation) from below. For this technique to work then the substrate 5 must of course be at least partially transparent to that radiation and the lower gate terminal 131 should be opaque. By illuminating the structure from below, the lower gate electrode 131 shields a central portion of the semi-conductive layer 100 from that radiation, whilst portions of the semi-conductive layer extending beyond the edges of the lower gate terminal 131 are exposed. In other words, the lower gate 131 is used as a mask and the interface between the exposed portions of semi-conductive material and the unexposed central portion are aligned accurately with the edges of the lower gate terminal 131. In other words, this technique is able to produce “self-alignment” between the lower gate terminal and the source and drain terminals 11, 12 which are each provided by a respective portion of the initially semi-conductive material which has been exposed to the radiation from below, through the substrate. The frequency and dose of radiation is selected as appropriate to result in a change in the electrical properties of the exposed portions of previously semi-conductive material from the semi-conductive to conductive, since those exposed portions form the aligned source and drain terminals 11, 12 with respect to the lower gate terminal 131 as illustrated in FIG. 39C. Then, as illustrated in FIG. 39D, a layer of resist material 9 has been formed over the structure and the resultant structure is again exposed to electromagnetic radiation from below such that the lower gate 131 shields a portion 91 of that resist layer 9 from the radiation, but portions 92 of that layer 9 on either side are exposed. The frequency and dose of this radiation is again selected as appropriate to produce the desired changes in the resist material 9 so as to enable its subsequent development and processing to form a window W in the resist layer that window W being aligned with the lower gate 131. It will be appreciate that this radiation using the second reverse exposure step will in general be at a different frequency and/or different dose from the radiation used in the conversion of portions of the semi-conductive material to source and drain terminals 11, 12.

Referring to FIG. 39E, this illustrates a subsequent step where, after the window W has been formed in the resist layer 9 (that window W accurately aligned with the lower gate 131) conducting material 81 has been deposited to form an aligned upper gate terminal 132 inside the window W, with remaining portions of the conductive material 81 covering the exposed portions 92 of this material on either side of the window W. Then, the structure is processed to remove or lift off the remaining portions 92 of resist material, leaving the structure shown in FIG. 39F which comprises a self-aligned dual-gate transistor. In this example the lower gate 131 has been used as a mask in the formation of both the aligned source and drain terminals 11, 12 and in the formation of the aligned upper gate terminal 132.

In will be appreciated from FIG. 39 and the above description that the material used for the formation of the upper electrode 132 in this example does not need to be transparent to the radiation used in either exposure step.

Referring now to FIG. 40, this shows an alternative technique embodying the invention and for producing a self-aligned dual gate transistor embodying the invention. In FIG. 40A a lower gate 131 has again been provided on the upper surface of a substrate 5 and a stack of dielectric layers and a sandwiched layer of initially semi-conductive material has been formed over the lower gate 131. As shown in FIG. 40A (with the arrows) this structure is exposed to suitable electromagnetic radiation from below such that the lower gate 131 shields a central portion of semi-conductive material, aligned with the lower gate 131, from the radiation and keeps it semi-conductive. However, portions of the initially semi-conductive material 100 on either side of the shielded portion are exposed to that radiation, and have their conductive properties changed to generally resistive as a result of that radiation. These exposed portions form the source and drain terminals 11, 12 as illustrated in FIG. 40B. A layer of conductive material 1320 is then formed over the underlying structure, and a layer of resist material 9 is formed over the conductive material 1320. The structure is then exposed to electromagnetic radiation from below such that the lower gate 131 acts as a mask for a second time. The material for the conductive layer 1320 and the radiation used in this second exposure step are chosen such that the radiation is able to pass through the layer of conductive material 1320 and expose portions of that conductive material 1320 on either side of the lower gate 131. However, the lower gate 131 acts as a mask such that the radiation in the second exposure step does not expose a central portion 91 of the layer of exist material 9. The resist material is then processed such that just the exposed portions 92 are removed leaving the central portion 91 covering a central portion of the layer of conductive material 1320 aligned with the lower gate 131, a shown in FIG. 40C. Then, as shown in FIG. 40D, that remaining portion 91 of resist material is used as an etch mask to remove portions of the layer of conductive material 1320 on either side of the etch mask 91, producing an upper gate 132 accurately aligned with the lower gate 131 and the source and drain terminals 11, 12 produced form portions of the initially semi-conductive layer 100.

It will be appreciate that in this embodiment the material used for the top gate (i.e. the material of the conductive layer 1320) must be transparent to the radiation used in the second exposure step. Again, however, the lower gate 131 has been used as a mask in both the formation of the source and drain terminals 11, 12 aligned to the lower gate and in the formation of the upper gate terminal 132 aligned to the lower gate terminal 131.

Referring now to FIG. 41, this shows steps in yet another method embodying the invention and for producing a dual gate transistor embodying the invention. As illustrated in FIG. 41A, a lower gate 131 is again provided on another surface of a substrate 5 over that underlying structure there is formed a sequence of layers comprising a first dielectric layer 41, a layer of initially semi-conductive material 100, a second dielectric layer 42, a layer of conductive material 1320 and a layer of resist material 9. The structure is then exposed to suitable radiation from below such that the lower gate 131 masks central portions of each of these layers aligned above the lower gate 131 from the radiation. In this example it is, of course, a requirement that, apart from the lower gate 131, each of the layers of the stack including the substrate 5 should be transparent to the radiation used in this first exposure. The radiation frequency and dose is chosen such that it suitably interacts with the exposed portions 92 of the resist layer 9, enabling that resist layer then to be processed so as to remove the exposed portion 92 and leave just the central, shielded portion 91 for use as an etch mask. Then, that central portion 91 is used as etch mask to remove portions of the layer of conductive material 1320, leaving just an aligned central portion forming the upper gate 132 (having the same projection on the horizontal plane as the lower gate 131). Then, as illustrated in FIG. 41C, the structure is again exposed to suitable radiation from below (i.e. through the substrate 5) such that unshielded portions of the originally semi-conductive layer 100 are converted to substantially resistive behavior, becoming the source and drain terminals 11, 12 aligned with the lower gate. A central portion of the previously semi-conductive 100 is shielded by lower gate 131, acting as a mask, and becomes the semi-conductive channel or body 10 of the dual-gate transistor.

Referring now to FIG. 42, this illustrates steps in alternative method embodying the invention and for producing a dual-gate transistor embodying the invention. Here, as shown in FIG. 42A, a lower gate is again provided on a nominal upper surface of a substrate 5. A layer of dielectric material 41 is formed over the gate and a layer of initially semi-conductive material 100 is formed over that dielectric layer. A layer of resist material 9 is then formed over the semi-conductive layer, and the structure is illuminated with suitable electronic radiation from below the substrate such that a central portion 91 of the resist layer is shielded from the radiation by the gate 131 acting as a mask, and portions 92 on either side of that central portion are exposed to the radiation. The radiation is arranged to have the desired effect on the resist material such that the resist layer can then be processed so as to remove the exposed portions 92 and leave central portion 91 in place, aligned with the lower gate 131. Such a structure is show in FIG. 42B, and this figure also shows that a layer of conductive material 1320 has been formed, part of that layer covering the central portion 91 of resist material aligned with the lower gate 131 and further portions of conductive material either side of the resist material 91 covering portions of the semi-conductive layer 100. Then, the structure is processed to lift off that remaining portion 91 of resist material, taking with it the portion of the conductive layer formed on top of it, so leaving just the portions of conductive material 1320 on either side of the bottom gate (i. e. with their edges aligned with the edges of the bottom gate) and respectively providing the source and drain terminals 11, 12. Thus, in this example the source and drain terminals are formed not from portions of the initially semi-conductive layer, but instead are provided by portions of conductive material self-aligned with the lower gate 131 by using a technique in which the lower gate 131 is again used as a mask. Then, as illustrated in FIG. 42C, a further layer of dielectric material 42 is formed over the underlying structure, and a further layer of resist material 9 is formed on top of that second dielectric layer 42. The structure is then again exposed to electromagnetic radiation of suitable frequency and dose from below to expose portions 92 of the resist layer 9 but leave a central portion 91 unexposed. It would be appreciate that in this technique the conductive material 1320 used for the formation of the source and drain terminals 11, 12 must be transparent to the radiation used in the second exposure step of FIG. 42C. This time, the resist material is processed so as to leave the exposed portions 92 in place, but form a window W aligned with the lower gate 131 by removing the exposed portion 91. Then a further layer of conductive material 1320 is formed over the structure as shown in FIG. 42D, this conductive material forming a conductive top gate 1320 inside the window W, and portions of conductive material also covering the remaining portions 92 of resist material on either side. The resist material is then further processed so as to lift off these portions 92, leaving the structure showing FIG. 42E. It will be appreciate that in this embodiment transparent conductive material is required to make the source and drain terminals, but in contrast to other embodiments those source and drain terminals are not manufactured out of portions of the initial semi-conductive layer. However, the conductive material used in the formation of the top gate 132 does not need to be transparent, as it is deposited inside a window W formed in self-alignment with the lower gate 131.

Referring now to FIG. 43, this shows yet another method embodying the invention and suitable for producing a dual gate transistor also embodying the invention. As illustrated in FIG. 43A, a lower gate 131 is provided on a substrate 5, and a stack of three layers is formed over that lower gate 131, that stack comprising a first dielectric 41, a layer of semi-conductive material 100 and a second dielectric layer 42. A layer of resist material 9 is formed over the underlying structure which is then exposed to suitable radiation from below (through the substrate 5) such that the lower gate 131 shields a central portion 91 of the resist material from that radiation, leaving portions 92 on either side exposed, that resist material is then processed suitably to remove the unexposed portion 91, forming a window W in the resist layer 9. That window W is self-aligned to the lower gate 131 as the lower gate has been used as a mask in the formation of that window. Then, as shown in FIG. 43B, the layer of conductive material 1320 has been formed, a portion of that layer inside the window forming the upper gate 132. Then the remaining portions and resist material 92 are removed to yield the structure shown in FIG. 43C. In this embodiment, the conductive material for layer 1320 is not transparent to the radiation used in a second exposure step illustrated in FIG. 43C where the structure is exposed to radiation from above, such that the top gate 132 now acts as a mask, shielding a central portion 10 of the initially semi-conductive layer 100 from that radiation from above, but leaving portions on either side exposed, which have their conductivities increased as an effect of the irradiation becoming generally conductive and forming the source and drain electrodes 11, 12. Thus, in this example, the non-transparent lower gate 131 is used as a mask in the production of the self-aligned upper gate 132, and then the upper gate 132 is used as a mask in the production of the self-aligned source and drain terminals 11, 12. Although FIG. 43C illustrates use of the top gate as a mask in the production of the source and drain terminal 11, 12, it will be appreciated that in alternative embodiments the lower gate 131 could again be used as a mask for such purposes with the substrate 5 being illuminated from below rather than above.

Referring now to FIG. 44, it will be appreciated from the above description that certain thin film transistor (TFT) devices embodying an aspect of the invention may employ dual gate electrodes. They may also employ split channel designs. Such devices may also be integrated with resistors, Schottky diodes, or indeed further single gate transistors. In the embodiment illustrated in FIG. 44, a bottom gate 131 has been formed (or is already provided) on the nominal upper surface of an underlying structure (or substrate) 5. A layer of dielectric material 41 covers the gate 131, and a body of initially semiconductive material 100 has been formed on top of that. A second layer of dielectric material 42 covers the underlying stack structure, and a top gate 132, aligned with the bottom gate 131, has been formed by a suitable technique, as described above, in which the bottom gate is used as a mask. In this example the top gate material is opaque to the radiation used in the subsequent exposure step, discussed below. Also in this example, the body of initially semiconductive material (e.g. comprising a metal oxide) is not uniform, but has a sub-structure comprising a plurality of layers. This split, or graded, channel feature may also be employed in single gate transistors, as described above in relation to alternative embodiments. In the embodiment of FIG. 44 the channel provided by the central portion 10 of the body of initially semiconductive material 100 comprises three layers 10(1), 10(2), and 10(3). As indicated by the arrows in FIG. 44, self-aligned (to the gates, that is) source and drain terminals 11, 12 are formed from portions of the initially semiconductive body 100 by exposing the structure to suitable electromagnetic radiation from above. The top gate 132 shields (i.e. masks) the central portion 10 from that radiation, leaving the electrical properties of its three layers unchanged, whereas the effect of exposing the un-masked portions of material 100 to that radiation is to change their electrical characteristics to essentially conductive, rather than semiconductive. In other words, the radiation is arranged to permanently increase the electrical conductivity of the exposed portions. Thus, FIG. 44 illustrates a device stack embodying the invention and the principle of self-alignment using optical irradiation.

Further details on split channels which may be employed in bottom gate, top gate, or dual gate transistors in embodiments of the invention, are as follows:

The split channels typical consist of two or more layers of semiconductor, for example each having tailored conductivity, mobility, carrier concentration, etc. The layers may be produced using different deposition conditions, e.g. different oxygen partial pressures during PVD, different PVD targets, e.g. IGZO of different stoichiometries, and/or doping measures as previously described. The end portions of the layered semiconductor body (as shown in FIG. 44) are, in the self-alignment approach, irradiated to become conductive; the layers do not become merged or diffused, and their conductivities will be different from each other, but they are all conductive. Additional metal source/drain contacts may be arranged to make electrical connection to these end portions (which themselves define the source and drain terminal portions in direct contact with the channel body 10) near to the device. In a dual gate 3-layer channel device, as shown in FIG. 44, the two interface layers (i.e. 10(1) and 10(3) which are in direct contact with the dielectric layers on either side, i.e. above and below the channel portion 10) may be arranged so as to be low in conductivity compared to the bulk (middle) layer 10(2), so that conduction occurs predominantly at one (or both) clean interface(s) between the three layers (in other words at the interfaces between 10(1) and 10(2), and between 10(2) and 10(3)). This gives improved conduction properties, including higher current, higher mobility, etc. Alternatively, in a dual gate 3-layer channel device, the two interface layers could be high in conductivity compared to the bulk (middle) layer, so that conduction occurs in two substantially independent channels, each controlled by its respective gate. In a single gate 2-layer channel device, the upper interface layer could be low in conductivity compared to the lower (bulk) layer, so that conduction occurs predominantly at the clean interface between the two layers. Benefits as discussed above, and those benefits make this split (dual) channel approach relevant to integration with Schottky and single gate TFTs (and resistors).

It will be appreciated that certain embodiments are applicable to the process of building up a FlexIC on a pre-existing structure, rather than onto a plain (e.g. glass) carrier. Such pre-existing structures may comprise arrays of devices, components or features, which may have a conductive surface layer to which the FlexIC devices need to connect.

Certain embodiments comprise at least one dual-gate TFT comprising a stack of gate terminal/gate insulator/semiconductor/source-drain terminals/gate insulator/gate terminal. By influencing the electric field in the semiconductor channel from opposing directions, the characteristics of the TFTs may be under greater control. For example, if both gates are electrically connected to each other, the effective TFT on-current may be doubled due to the creation of two channels at the two interfaces of the semiconductor with the respective gate dielectrics.

When depositing a FlexIC onto an existing structure, e.g. on a part-finished substrate, conductive features or elements on the surface of the existing structure may be used as functional elements during integration of devices, as described herein, onto the part-finished substrate. This presents an opportunity to generate self-aligned FlexICs incorporating dual gate TFTs, e.g. using conductive features on the surface of the part-finished substrate as a bottom gate of such a dual gate TFT.

Advantageously, this can allow an effective 2× Ion (i.e. doubling of “on” current) by connecting the two gates, as described above. Alternatively the dual gates may be independently controlled to shift threshold voltage (Vt) or create depletion type/like devices. Conventional lithography approaches would mean larger gates at the top to account for overlay, whereas the self-aligned techniques described herein can produce top gates having the same footprints as, and accurately aligned with, the bottom gates. In certain embodiments, more complexity may be added to the semiconductor stack e.g. using multiple layers including highly-doped/undoped layers for example. This can be arranged at only at one semiconductor/gate dielectric interface or at both such interfaces. Similarly to self-aligned top-gate structures, the properties of an interface layer may be used to selectively dope/increase the conductivity of areas of semiconductor (optionally including in the channel region). This approach can also be used to create resistors. In certain embodiments, the bottom-gate can be used to align the second (top) gate (or both second gate and second gate dielectric) using rear side exposure, creating either a window (for “lift-off”) or an etch-mask aligned to the first gate. If integrated onto a part-finished substrate that emits radiation or provides some other way of activating the channel, the bottom gate can protect or block the channel from the LED/light-source/other below. In effect this would also mean that the system would “self-align” to the bottom-gate if the part-finished substrate below excited or temporarily or permanently doped the unprotected channel extending laterally beyond the bottom gate. The device stack could be engineered so that the source and drain electrodes did not overlap the gate (or either gate).

The same effects may be achieved by UV light irradiation (e.g. from an excimer laser) through the device stack from above or below to create self-aligned source-drain contacts (i.e. aligned to one, or both, of the gates). From the bottom-side of the substrate one could also align a top-gate to the bottom-gate electrode. The gate-source/drain overlap, rather than the gate-gate overlap, is particularly critical (in terms of reducing parasitic capacitance, but this approach allows the two gates to have a similar positional accuracy relative to the SD.

In certain embodiments, use of a doping underlayer (formed e.g. by ALD) may allow doped resistors to be created. Suitable resistors include those with lateral or vertical orientation, or a combination of both.

In certain embodiments, the underlayer may be formed as part of the bottom-gate process (i.e. it may already be provided on a part-finished substrate).

The dual gate architecture employed in certain embodiments also provides an opportunity to form vertically stacked lateral capacitors integrated into the stack. This can provides more capacitance per unit area of a FlexIC

In certain embodiments the dual gate TFT stack includes at least 2×ALD layers with electrodes: Bottom Gate/Dielectric1/Source-Drain/Dielectric2/Top Gate. The two ALD layers may be arranged to provide dopants to one or more channel layers.

Referring now to FIG. 45, this shows another circuit module embodying the invention and comprising a self-aligned dual gate transistor and a resistor. A layer of initially semiconductive material (e.g. in an initial “normally off” state) has been formed over the bottom gate and first dielectric layer 41. An aligned top gate 132 has been formed, using the bottom gate as a mask, and the top gate has then been used as mask to shield the channel portion 10 from processing (by radiation exposure) to render a portion of the originally semiconductive layer resistive (to form the resistor body 20) and a further portion conductive (to form the drain terminal 12). The resistor body 20 thus directly connects to the semiconductor channel, in effect combining the transistor source and resistor second terminals 11,22

Referring now to FIG. 46, this shows another circuit module embodying the invention and comprising a resistor, a top-gate transistor, and a Schottky diode. This circuit module thus integrates three different devices, each comprising a respective body of material comprising a respective quantity of the same metal oxide. The module is based on a top gate TFT structure, and has the resistor lifted up so that it is co-planar with, and/or is formed directly or indirectly upon the same dielectric layer as, the diode semiconductor layer. One terminal of the source/drain terminals of the transistor and one of the Schottky terminals are provided by a common terminal. That common terminal may thus be described as a source/drain, interconnect, and Schottky diode electrode, provided by a single, common body of conductive material. In this example, that common terminal/body is formed so as to partially overlap the transistor body and an adjacent portion of a nominal upper surface of the underlying substate. In this example, the transistor body may be formed first, e.g. directly on the substrate, followed by formation of the transistor source/drain terminals, one of which is the common electrode/interconnect to the Schottky diode. Then, a layer or other body of dielectric material may be formed over the transistor body and source/drain terminals, and then a window or via may be formed down through the dielectric layer to expose a portion of an upper surface of the common electrode. The quantities of metal oxide material for the diode and resistor bodies may then be formed/deposited/provided, either at the same time or in separate processes. If provided in separate processes, the process conditions may be adapted such that the quantity of metal oxide material forming the diode body is formed in a semiconducting state (e.g. a “normally off” state), whereas the quantity forming the resistor body is formed in a resistive state (i.e. having higher conductivity than the diode body in its non-conducting (i.e. off) state). The diode body at least partly fills the window through the dielectric, contacts the common terminal, and also covers a portion of an upper surface of the dielectric, that upper surface also directly or indirectly supporting the resistor body. The resistor terminals, transistor gate terminal, and upper terminal of the diode may be formed in at the same time, e.g. by selective deposition, printing, forming and then patterning a layer of conductive material, or by any other suitable technique.

Number	Date	Country	Kind
1912025.2	Aug 2019	GB	national
2000887.6	Jan 2020	GB	national

ELECTRONIC CIRCUITS AND CIRCUIT ELEMENTS

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