Patent Application
20230138154
The present invention relates to an electronic component and a manufacturing method therefore and, more particularly, to an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate and a manufacturing method therefor.
Patent Document 1 discloses an LC filter having a configuration in which a capacitor and an inductor are formed on a substrate. In the LC filter described in Patent Document 1, a lower electrode of the capacitor and a coil pattern constituting the inductor are disposed in the same conductor layer.
However, when the conductor thickness of the coil pattern is increased so as to increase the Q-value of the coil in the configuration in which the capacitor lower electrode and the coil pattern are disposed in the same conductor layer, the conductor thickness of the capacitor lower electrode is inevitably increased. This makes it difficult to form an upper electrode on the lower electrode with high accuracy, which may increase variation in capacitance.
An object of the present invention is therefore to, in an electronic component integrating an element that requires high processing accuracy, such as a capacitor, and an element that requires a sufficient conductor thickness, such as an inductor, satisfy characteristics required for both of the elements. Another object of the present invention is to provide a manufacturing method for such an electronic component.
An electronic component according to an aspect of the present invention includes: a substrate; and a plurality of conductor layers and a plurality of insulating resin layers which are alternately stacked on the substrate. The plurality of insulating resin layers include a first insulating resin layer positioned in the lowermost layer and a plurality of second insulating resin layers positioned on the first insulating resin layer. The plurality of conductor layers include a first conductor layer embedded in the first insulating resin layer and a plurality of second conductor layers embedded respectively in the plurality of second insulating resin layers. The first conductor layer includes a capacitor constituted by a lower electrode and an upper electrode stacked on the lower electrode through a dielectric film made of an inorganic insulating material. The plurality of second conductor layers include a coil pattern. The first insulating resin layer is smaller in thickness than each of the second insulating resin layers, and the second insulating resin layers are smaller in thermal expansion coefficient than the first insulating resin layer.
According to the present invention, a capacitor requiring high processing accuracy is embedded in the first insulating resin layer positioned in the lowermost layer and having a small thickness, and an inductor requiring a sufficient conductor thickness is embedded in the second insulating resin layers having a large thickness, so that characteristics required for both of the elements can be satisfied. In addition, since the second insulating resin layers have a small thermal expansion coefficient, the occurrence of warpage and peeling can be suppressed. The first insulating resin layer can be made of polyimide-based resin. The second insulating resin layers can be made of a material obtained by adding fillers to epoxy-based resin.
In the present invention, each of the plurality of second conductor layers may have a larger thickness than the total thickness of the upper and lower electrodes. This can increase the Q-value of the coil.
In the present invention, a first via conductor provided so as to penetrate the first insulating resin layer and connecting the first and second conductor layers may have a rectangular planar shape, and a second via conductor provided so as to penetrate the second insulating resin layer and connecting different second conductor layers may have a circular planar shape. This can ensure a sufficient area for the first via conductor and prevent the occurrence of peeling in the vicinity of the second via conductor.
In the present invention, the first insulating resin layer may be partly removed, and one of the plurality of second insulating resin layers that contacts the first insulating resin layer may be embedded in a portion where the first insulating resin layer has been removed. This increases the volume of the second insulating resin layer having a small thermal expansion coefficient, thus making warpage of the entire electronic component less likely to occur.
An electronic component manufacturing method according to an aspect of the present invention includes: a first step of forming, on a substrate, a first conductor layer including a capacitor constituted by a lower electrode and an upper electrode stacked on the lower electrode through a dielectric film made of an inorganic insulating material; a second step of forming a first insulating resin layer that covers the first conductor layer; and a third step of alternately forming, on the first insulating resin layer, second conductor layers including a coil pattern and second insulating resin layers larger in thickness and smaller in thermal expansion coefficient than the first insulating resin layer.
According to the present invention, it is possible to form a capacitor requiring high processing accuracy in the first conductor layer and to form an inductor requiring a sufficient conductor thickness in the second conductor layer. In addition, since the second insulating resin layer has a small thermal expansion coefficient, the occurrence of warpage and peeling can be suppressed.
In the present invention, the first insulating resin layer may be formed by a coating method in the second step, and the second insulating resin layer may be formed by a lamination method in the third step. This facilitates the formation of the first and second insulating resin layers different in thickness.
In the present invention, the second conductor layer may have a first via conductor and a second via conductor, the first via conductor being provided so as to penetrate the first insulating resin layer and connecting the first conductor layer and one of a plurality of the second conductor layers that is positioned in the lowermost layer, the second via conductor being provided so as to penetrate the second insulating resin layers and connecting the plurality of second insulating resin layers. The first via conductor may have a flat bottom, and the surfaces of the plurality of second conductor layers each have a recess at a portion thereof connected to the second via conductor. The bottom of the second via conductor may be projected so as to bite into the recess. Since the bottom of the first via conductor is thus flat, variation in capacitance due to the surface irregularity of the lower electrode or upper electrode can be suppressed. On the other hand, since the bottom of the second via conductor is projected so as to bite into the recess, the contact area between the second conductor layer and a third conductor layer increases, thus making it possible to enhance adhesion therebetween.
In the present invention, the first via conductor may have a rectangular planar shape, and the second via conductor may have a circular planar shape. This can ensure a sufficient area for the first via conductor and prevent the occurrence of peeling in the vicinity of the second via conductor.
In the present invention, each of the plurality of second conductor layers may have a larger thickness than the total thickness of the upper and lower electrodes. This can increase the Q-value of the coil.
The electronic component manufacturing method according to the aspect of the present invention may further include: a fourth step of exposing the first conductor layer by forming an opening in the first insulating resin layer; and a fifth step of exposing the second conductor layer by forming an opening in the second insulating resin layer. The fourth step may be performed by a photolithography method, and the fifth step may be performed by laser processing. Thus, it is possible to achieve high processing accuracy in the fourth step and to process the opening of the first insulating resin layer into a desired planar shape. Further, the fifth step can be performed at low cost, and a non-photosensitive material can be used as the material of the second insulating resin layer.
An electronic component according to another aspect of the present invention includes: a substrate; a first conductor layer formed on the substrate and including a capacitor constituted by a lower electrode and an upper electrode stacked on the lower electrode through a dielectric film made of an inorganic insulating material; a first insulating resin layer that covers the first conductor layer; a second conductor layer formed on the first insulating resin layer; a second insulating resin layer that covers the second conductor layer; and a third conductor layer formed on the second insulating resin layer. The second and third conductor layers each include a coil pattern. The first insulating resin layer has a first opening exposing the first conductor layer. The second insulating resin layer has a second opening exposing the second conductor layer. The second conductor layer has a first via conductor connected to the first conductor layer through the first opening. The third conductor layer has a second via conductor connected to the second conductor layer through the second opening. The first via conductor has a flat bottom, and the surface of the second conductor layer has a recess at a portion thereof connected to the second via conductor. The bottom of the second via conductor is projected so as to bite into the recess.
According to the present invention, an element that requires high processing accuracy, such as a capacitor, is embedded in the first insulating resin layer positioned in the lowermost layer, and an element that requires a sufficient conductor thickness, such as an inductor, is embedded in the second and third insulating resin layers, so that characteristics required for both of the elements can be satisfied. In addition, since the bottom of the first via conductor is flat, variation in capacitance due to the surface irregularity of the lower electrode or upper electrode can be suppressed. On the other hand, since the bottom of the second via conductor is projected so as to bite into the recess, the contact area between the second and third conductor layers increases, thus making it possible to enhance adhesion therebetween.
An electronic component manufacturing method according to another aspect of the present invention includes: a first step of forming, on a substrate, a first conductor layer including a capacitor constituted by a lower electrode and an upper electrode stacked on the lower electrode through a dielectric film made of an inorganic insulating material; a second step of forming a first insulating resin layer that covers the first conductor layer; a third step of forming a first opening exposing the first conductor layer in the first insulating resin layer using a photolithography method; a fourth step of forming, on the first insulating resin layer, a second conductor layer including a coil pattern such that the second conductor layer is connected to the first conductor layer through the first opening; a fifth step of forming a second insulating resin layer that covers the second conductor layer; a sixth step of forming, in the second insulating resin layer, a second opening exposing the second conductor layer using laser processing; a seventh step of forming a recess in the surface of the second conductor layer exposed through the second opening; and an eighth step of forming, on the second insulating resin layer, a third conductor layer including a coil pattern such that the third conductor layer is connected to the second conductor layer through the second opening.
According to the present invention, it is possible to form a capacitor requiring high processing accuracy in the first conductor layer and to form an inductor requiring a sufficient conductor thickness in the second conductor layer. In addition, after the second opening is formed in the second insulating resin layer by laser processing, a recess is formed in the surface of the second conductor layer exposed through the second opening, so that the contact area between the second and third conductor layers increases, thereby enhancing adhesion therebetween. Further, the second opening can be formed at low cost, and a non-photosensitive material can be used as the material of the second insulating resin layer. On the other hand, the first opening is formed by a photolithography method, so that it is possible to achieve high processing accuracy in the formation of the first opening and to process the first opening into a desired planar shape.
In the present invention, the first insulating resin layer may be formed by a coating method in the second step, and the second insulating resin layer may be formed by a lamination method in the fifth step. This facilitates the formation of the first and second insulating resin layers different in thickness.
As described above, according to the present invention, in an electronic component integrating an element that requires high processing accuracy, such as a capacitor, and an element that requires a sufficient conductor thickness, such as an inductor, characteristics required for both of the elements can be satisfied.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As illustrated in
The conductor layer M1 is a layer positioned in the lowermost layer and includes conductor patterns 21 and 22. The conductor patterns 21 and 22 are each constituted of a thin seed layer S contacting the planarizing layer 3 and a plating layer P provided on the seed layer S and having a film thickness larger than that of the seed layer S. Similarly, the conductor patterns positioned in other conductor layers are each formed of a laminated body of the seed layer S and plating layer P. The conductor pattern 21 constitutes a lower electrode of a capacitor, and the upper and side surfaces thereof are covered with a dielectric film (capacitive insulating film) 4. The dielectric film 4 is removed at the outer peripheral portion of the electronic component 1, whereby stress is relieved.
A conductor pattern 23 is formed on the upper surface of the conductor pattern 21 through the dielectric film 4. The conductor pattern 23 belongs to a conductor layer MM positioned between the conductor layers M1 and M2 and constitutes a capacitor upper electrode. Thus, there is formed a capacitor having the conductor pattern 21 as the lower electrode and the conductor pattern 23 as the upper electrode. The conductor layers M1 and MM are covered with the insulating resin layer 11 through a passivation film 5. In the present embodiment, the dielectric film 4 and passivation film 5 are both made of an inorganic insulating material. The inorganic insulating material constituting the dielectric film 4 and that constituting the passivation film 5 may be the same or different. The passivation film 5 is removed at the outer peripheral portion of the electronic component 1, whereby stress is relieved.
The conductor layer M2 is the second conductor layer that is provided on the surface of the insulating resin layer 11 and includes conductor patterns 24 and 25. The conductor pattern 24 is connected to the conductor patterns 23 and 22 through respective via conductors 24a and 24b. The conductor pattern 25 is connected to the conductor pattern 21 through a via conductor 25a. The conductor layer M2 is covered with the insulating resin layer 12.
The conductor layer M3 is the third conductor layer that is provided on the surface of the insulating resin layer 12 and includes conductor patterns 26 and 27. The conductor pattern 26 is connected to the conductor pattern 24 through a via conductor 26a. The conductor layer M3 is covered with the insulating resin layer 13.
The conductor layer M4 is the fourth conductor layer that is provided on the surface of the insulating resin layer 13 and includes conductor patterns 28 and 29. The conductor pattern 28 is connected to the conductor pattern 26 through a via conductor 28a. The conductor layer M4 is covered with the insulating resin layer 14.
Terminal electrodes E1 and E2 are provided on the upper surface of the insulating resin layer 14. The terminal electrodes E1 and E2 are connected to the conductor patterns 28 and 29, respectively, through via conductors Ela and E2a. The conductor patterns 22 and 24 to 29 each constitute a part of a coil pattern, for example, whereby a capacitor and an inductor are integrated on the substrate 2.
In the present embodiment, the material constituting the insulating resin layer 11 and the material constituting the insulating resin layers 12 to 14 differ from each other. Specifically, as the material of the insulating resin layer 11, a photosensitive material such as polyimide-based resin that is capable of easily forming the insulating resin layer by a coating method (e.g., a spin-coating method). On the other hand, as the material of the insulating resin layers 12 to 14, a material such as one obtained by adding fillers to epoxy-based resin that is capable of easily adjusting a thermal expansion coefficient and forming the insulating resin layer by a lamination method can be used.
As illustrated in
Further, in the present embodiment, the insulating resin layers 12 to 14 have a thermal expansion coefficient smaller than that of the insulating resin layer 11. Thus, it is possible to prevent peeling at the boundary between the insulating resin layers 12 to 14 having a large thickness and the conductor patterns 24 to 29 and to make warpage of the entire electronic component 1 less likely to occur. The thermal expansion coefficient of the insulating resin layers 12 to 14 can be adjusted by the amount and material of the fillers to be added to the insulating resin layers 12 to 14. As the material of the fillers, a material having a small thermal expansion coefficient, such as silica, can be used. Although the insulating resin layer 11 is larger in thermal expansion coefficient than the insulating resin layers 12 to 14, it is smaller in thickness than the insulating resin layers 12 to 14, so that the insulating resin layer 11 is not subjected to strong stress and thus less subjected to peeling or the like. The substrate 2 is preferably smaller in thermal coefficient than the insulating resin layers 12 to 14. As described above, the insulating resin layer 11 having a large thermal expansion coefficient is sandwiched by the substrate 2 and the insulating resin layers 12 to 14 having a smaller thermal expansion coefficient, thereby making it possible to suppress warpage of the entire electronic component 1.
Further, the conductor layers M1 and MM each have a flat surface, and the via conductors 24a, 24b, and 25a connecting the conductor layer M2 and the conductor layers M1, MM each have a flat bottom. This suppresses variation in capacitance due to the surface irregularity of the lower electrode or upper electrode. On the other hand, the surfaces of the conductor layers M2 to M4 each have a recess, and the bottoms of the via conductors 26a, 28a, E1a, and E2a each have a projection biting into the recess of each of the conductor layers M2 to M4. This increases the contact areas between the via conductors 26a, 28a, E1a, E2a and the conductor patterns 24, 26, 28, 29 connected thereto, thereby enhancing adhesion therebetween.
In the present embodiment, the planar shape of each of the via conductors 24a, 24b, and 25a having a flat bottom may be formed into a rectangular shape, and the planar shape of each of the via conductors 26a, 28a, Ela, and E2a having a projecting bottom may be formed into a circular shape. Thus, it is possible to increase the contact areas of the via conductors 24a, 24b, and 25a and to prevent the occurrence of peeling around the via conductors 26a, 28a, Ela, and E2a.
Of the via conductors 24a, 24b, and 25a, the via conductor 24a connected to the conductor pattern 23 which is the upper electrode is provided so as to penetrate the insulating resin layer 11 and passivation film 5, while the via conductors 24b and 25a connected to the conductor patterns 21 and 22 which is the lower electrode or coil pattern are provided so as to penetrate the insulating resin layer 11, passivation film 5, and dielectric film 4. That is, the via conductor 24a penetrates an inorganic insulating film of a single layer, while the via conductors 24b and 25a penetrate an inorganic insulating film of two layers. This is because, except an area where the conductor pattern 23 which is the upper electrode, the upper surfaces of the conductor patterns 21 and 22 are covered with an inorganic insulating film of two layers constituted of the dielectric film 4 and passivation film 5. Since the upper surfaces of the conductor patterns 21 and 22 are thus covered with inorganic insulating film of two layers constituted of the dielectric film 4 and passivation film 5, it is possible to protect the conductor patterns 21 and 22 more effectively.
The following describes a manufacturing method for the electronic component 1 according to the present embodiment.
As illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
After removal of the resist layer R3, the conductor layer M2 is formed on the insulating resin layer 11 using the same method as the formation method for the conductor layer M1, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Thereafter, the same process is repeated to form the insulating resin layer 13, conductor layer M4, and insulating resin layer 14 in this order, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, after removal of the resist layer R4, the substrate 2 is cut along the spaces A to individualize the electronic component 1. As a result, the electronic component 1 according to the present embodiment is completed.
As described above, in the electronic component 1 according to the present embodiment, the material and thickness of the insulating resin layer 11 positioned in the lowermost layer are different from those of each of the insulating resin layers 12 to 14 positioned on the insulating resin layer 11. Specifically, the insulating resin layer 11 is smaller in thickness than the insulating resin layers 12 to 14, and the insulating resin layers 12 to 14 are smaller in thermal expansion coefficient than the insulating resin layer 11. Thus, a capacitor requiring high processing accuracy can be embedded in the insulating resin layer 11 having a small thickness, and an inductor requiring a sufficient conductor thickness can be embedded in the insulating resin layers 12 to 14 each having a large thickness. In addition, since the insulating resin layers 12 to 14 have a small thermal expansion coefficient, the occurrence of warpage and peeling can be suppressed.
Further, in the electronic component 1 according to the present embodiment, the conductor layers M1 and MM each have a flat surface, so that it is possible to suppress variation in capacitance due to the surface irregularity of the lower electrode or upper electrode. On the other hand, the surfaces of the conductor layers M2 to M4 each have a recess, and the bottoms of the via conductors 26a, 28a, E1a, and E2a each have a projection biting into the recess of each of the conductor layers M2 to M4. This increases the contact areas between the via conductors 26a, 28a, Ela, E2a and the conductor patterns 24, 26, 28, 29 connected thereto, thereby enhancing adhesion therebetween.
Furthermore, of the via conductors 24a, 24b, and 25a, the via conductor 24a connected to the conductor pattern 23 which is the upper electrode is provided so as to penetrate the insulating resin layer 11 and passivation film 5, while the via conductors 25a and 24b connected respectively to the conductor patterns 21 and 22 which are the lower electrode or coil pattern are provided so as to penetrate the insulating resin layer 11, passivation film 5, and dielectric film 4. This makes it possible to protect the conductor patterns 21 and 22 more effectively.
The electronic component 1A according to the first modification differs from the electronic component 1 according to the above embodiment in that the insulating resin layer 11 is partly removed in an area not overlapping the coil pattern and that the insulating resin layer 12 is embedded in the area where the insulating resin layer 11 has been removed. The embedded insulating resin layer 12 is in contact with the planarizing layer 3 or passivation film 5, and the thickness of the insulating resin layer 12 is locally increased at the contact portion. Other basic configurations are the same as those of the electronic component 1 according to the above embodiment, so the same reference numerals are given to the same elements, and overlapping description will be omitted. According to the electronic component 1A of the first modification, the insulating resin layer 12 having a small thermal expansion coefficient increases in volume, so that warpage of the entire electronic component 1 is much less likely to occur.
The electronic component 1B according to the second modification differs from the electronic component 1A according to the first modification in that the dielectric film 4 and passivation film 5 are removed at the removal area of the insulating resin layer 11. The embedded insulating resin layer 12 is in contact with the planarizing layer 3 or conductor pattern 21. Other basic configurations are the same as those of the electronic component 1A according to the first modification, so the same reference numerals are given to the same elements, and overlapping description will be omitted. According to the electronic component 1B of the second modification, the insulating resin layer 12 having a small thermal expansion coefficient further increases in volume, so that warpage of the entire electronic component 1 is still much less likely to occur. Further, the dielectric film 4 and passivation film 5 are partly removed, so that stress due to the presence of the dielectric film 4 and passivation film 5 is relieved.
While the preferred embodiment of the present invention has been described, the present invention is not limited to the above embodiment, and various modifications may be made within the scope of the present invention, and all such modifications are included in the present invention.
For example, although the present invention is applied to an LC filter in the above embodiment, the present invention can be applied not only to the LC filter but also to electronic components of other types.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-053614 | Mar 2020 | JP | national |
| 2020-053615 | Mar 2020 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/009985 | 3/12/2021 | WO |
