Patent Application
20240087809
The present disclosure relates to an electronic component including a semiconductor substrate, such as a capacitor or an inductor.
Japanese Patent No. 5458514 (hereinafter “Patent Literature 1”) discloses a semiconductor device in which a passive component such as a thin film capacitor is provided on a semiconductor substrate. A terminal electrode is provided on such a semiconductor substrate including a passive component, so that a surface mount electronic component is obtained.
In a general surface mount electronic component including a semiconductor substrate, the semiconductor substrate itself has no electrical function. The semiconductor substrate is used as a base material for keeping the entire shape.
In the semiconductor device disclosed in Patent Literature 1, when a high-frequency current flows into the passive component (a function portion) due to the conductivity of the semiconductor substrate, a magnetic field generated by the high-frequency current is applied to the semiconductor substrate, As a result, an eddy current flows into the semiconductor substrate. As a result, the loss of a high-frequency signal is increased by the eddy current.
In view of the foregoing, exemplary embodiments of the present disclosure are directed to provide an electronic component capable of significantly reducing the loss of a high-frequency signal by significantly reducing an eddy current flowing into a semiconductor substrate.
An electronic component as one example of the present disclosure includes: a semiconductor substrate; an insulator layer on the semiconductor substrate; a conductor layer facing the semiconductor substrate across the insulator layer; and a non-conductor layer facing the semiconductor substrate across the insulator layer, wherein the conductor layer, or the conductor layer and a portion of the non-conductor layer, configure a passive component, and the insulator layer includes a conduction path that passes through the insulator layer and electrically connects the conductor layer and the semiconductor substrate.
An electronic component as another example of the present disclosure includes: a semiconductor substrate; a non-conductor layer on the semiconductor substrate; and a conductor layer facing the semiconductor substrate across the non-conductor layer, wherein the non-conductor layer, and the semiconductor substrate and the conductor layer form a capacitor.
According to the present disclosure, an electronic component in which the loss of a high-frequency signal is significantly reduced by significantly reducing an eddy current flowing into a semiconductor substrate is obtained.
Hereinafter, a plurality of exemplary embodiments of the present disclosure will be described with reference to the attached drawings and several specific examples. In the drawings, components and elements assigned with the same reference numerals or symbols will represent identical components and elements. While an exemplary embodiment of the present disclosure is divided and described into a plurality of exemplary aspects for the sake of convenience in consideration of ease of description or understanding of main points, elements described in different exemplary embodiments are able to be partially replaced or combined with each other. In the second and subsequent exemplary embodiments, a description of features common to the first exemplary embodiment will be omitted, and only different features will be described. In particular, the same advantageous functions and effects by the same configurations will not be described one by one for each exemplary embodiment.
The electronic component 101 includes a semiconductor substrate 1, an insulator layer 2 provided on the semiconductor substrate 1, a conductor layer 3 provided so as to face the semiconductor substrate 1 across the insulator layer 2, and a dielectric layer 4 provided so as to face the semiconductor substrate 1 across the insulator layer 2. The dielectric layer 4 corresponds to a portion of a non-conductor layer according to the present disclosure. The conductor layer 3 includes a lower electrode 31 provided on the insulator layer 2, and an upper electrode 32 provided on the dielectric layer 4. In this example, the dielectric layer 4 is provided on the upper surface of the lower electrode 31.
In the present disclosure, the “conductor layer” is a name of a concept that includes, for example, an electrode and a conductor pattern. In addition, the “non-conductor layer” is a name of a concept that includes an insulator layer and a dielectric layer.
The insulator layer 2 includes a plurality of conduction paths 5 passing through the insulator layer 2 and electrically connecting the lower electrode 31 and the semiconductor substrate 1. It is to be noted that, although the present exemplary embodiment describes an example of the plurality of conduction paths 5 electrically connecting the lower electrode 31 and the semiconductor substrate 1, the conduction path 5 that provides a single current path that bypasses at least the semiconductor substrate 1 may be present.
A passivation layer 6 covering the insulator layer 2, the lower electrode 31, the dielectric layer 4, and the upper electrode 32 is provided on the surface of the semiconductor substrate 1.
A first terminal electrode 81 and a second terminal electrode 82 are provided on the surface of the passivation layer 6. A first extended electrode 71 electrically connecting the first terminal electrode 81 and the lower electrode 31 is provided between the first terminal electrode 81 and the lower electrode 31, and a second extended electrode 72 electrically connecting the second terminal electrode 82 and the upper electrode 32 is provided between the second terminal electrode 82 and the upper electrode 32.
The surface of the passivation layer 6, a portion of the surface of the first terminal electrode 81, and a portion of the surface of the second terminal electrode 82 are covered with a solder resist film 9.
The dielectric layer 4, and the lower electrode 31 and the upper electrode 32 that are provided across the dielectric layer 4 configure a passive component as a capacitor. In short, the electronic component 101 is a capacitor that uses the first terminal electrode 81 and the second terminal electrode 82 as a surface-mount connection terminal.
Herein, a configuration of an electronic component as a comparative example of the present exemplary embodiment is shown in
In
In contrast, since the electronic component 101 according to the present exemplary embodiment includes the plurality of conduction paths 5 electrically connecting the lower electrode 31 and the semiconductor substrate 1 in the insulator layer 2, the semiconductor substrate 1 is parallelly connected to the lower electrode 31. Therefore, a current flows into the semiconductor substrate 1 in approximately the same direction as the direction into which the current flowing into the lower electrode 31 flows. The arrow C31 in
The semiconductor substrate 1 is a silicon substrate, for example, and may be a silicon intrinsic semiconductor substrate or a silicon impurity semiconductor substrate. The insulator layer 2 is an SiO2 film being a thermal oxide film of a silicon substrate. The lower electrode 31 and the upper electrode 32 are an Al film or a Cu film. The dielectric layer 4 is an SiO2 film. The passivation layer 6 is an SiN film and a film of an organic material provided on the SiN film. Alternatively, the passivation layer 6 is an SiN film. The first extended electrode 71 and the second extended electrode 72 are Cu films (Cu/Ti films) including a Ti film as a base. The first terminal electrode 81 and the second terminal electrode 82 are Au films (Au/Ni films) including an Ni film as a base. The solder resist film 9 is a film of an organic material.
Examples of materials and thickness sizes of each portion described above are shown below.
Subsequently, an example of a method of manufacturing the electronic component 101 will be described based on
The step (1) is a substrate supplying step and supplies a silicon substrate as a semiconductor substrate 1 to manufacturing equipment.
The step (2) is an insulator layer forming step and forms an SiO2 film as an insulator layer 2 by thermally oxidizing the surface of the semiconductor substrate 1.
The step (3) is an insulator layer etching step and forms a hole for forming a conduction path to be shown later by etching a predetermined portion of the insulator layer 2.
The step (4) is a lower electrode forming step and forms a conduction path 5 and a lower electrode 31 by sputtering Al or Cu on the insulator layer 2.
The step (5) is a dielectric layer forming step and forms an SiO2 film as a dielectric layer 4 on the upper surface of the lower electrode 31.
The step (6) is an upper electrode forming step and forms an upper electrode 32 by sputtering Al or Cu on the upper surface of the dielectric layer 4.
The step (7) is a passivation layer forming step and forms a passivation layer 6 by covering the surface of the semiconductor substrate 1, the insulator layer 2, the lower electrode 31, the dielectric layer 4, and the upper electrode 32 with a passivation film.
The step (8) is a passivation layer aperture-forming step and forms an aperture AP in a position in which a first extended electrode and a second extended electrode to be shown later.
The step (9) is a power supply film forming step and forms a power supply film E0 by sputtering a Ti film on the surface of the passivation layer 6 and then sputtering a Cu film on the Ti film.
The step (10) is a pad electrode forming step, and forms pad electrodes E1 and E2 by sputtering a Ni film on the power supply film E0 and then sputtering an Au film on the Ni film.
The step (11) is a power supply film etching step, and forms a first extended electrode 71, a second extended electrode 72, a first terminal electrode 81, and a second terminal electrode 82 by etching and removing an exposed portion of the power supply film E0 shown in the step (10).
The step (12) is a solder resist film forming step and covers with a solder resist film 9 the surface of the passivation layer 6, a portion of the surface of the first terminal electrode 81, and a portion of the surface of the second terminal electrode 82.
Although the above example exemplifies the electronic component including the first terminal electrode 81 and the second terminal electrode 82, the present disclosure is similarly applicable to an electronic component including a capacitor configured by the lower electrode 31, the dielectric layer 4, and the upper electrode 32.
The second exemplary embodiment exemplifies an electronic component in which a portion of a path of a current flowing into a passive component is configured by a portion of the semiconductor substrate.
The electronic component 102 includes a semiconductor substrate 1, an insulator layer 2 provided on the semiconductor substrate 1, a first lower electrode 31A and a second lower electrode 31B that are provided so as to face the semiconductor substrate 1 across the insulator layer 2, and a dielectric layer 4 provided so as to face the semiconductor substrate 1 across the insulator layer 2. The dielectric layer 4 corresponds to a portion of a non-conductor layer according to the present disclosure. The first lower electrode 31A and the second lower electrode 31B that are provided on the insulator layer 2, and the upper electrode 32 provided on the dielectric layer 4 are portions of the conductor layer according to the present disclosure.
The electronic component 102 according to the present exemplary embodiment includes the lower electrode divided into the first lower electrode 31A and the second lower electrode 31B, and the dielectric layer 4 provided on the upper surface of the first lower electrode 31A.
The insulator layer 2 includes a first conduction path 5A passing through the insulator layer 2 and electrically connecting the first lower electrode 31A and the semiconductor substrate 1. In addition, the insulator layer 2 includes a second conduction path 5B passing through the insulator layer 2 and electrically connecting the second lower electrode 31B and the semiconductor substrate 1.
A passivation layer 6 covering the insulator layer 2, the first lower electrode 31A, the second lower electrode 31B, the dielectric layer 4, and the upper electrode 32 is provided on the surface of the semiconductor substrate 1.
A first terminal electrode 81 and a second terminal electrode 82 are provided on the surface of the passivation layer 6. A first extended electrode 71 electrically connecting the first terminal electrode 81 and the second lower electrode 31B is provided between the first terminal electrode 81 and the second lower electrode 31B, and a second extended electrode 72 electrically connecting the second terminal electrode 82 and the upper electrode 32A is provided between the second terminal electrode 82 and the upper electrode 32A.
The surface of the passivation layer 6, a portion of the surface of the first terminal electrode 81, and a portion of the surface of the second terminal electrode 82 are covered with a solder resist film 9.
The dielectric layer 4, and the first lower electrode 31A and the upper electrode 32 that are provided across the dielectric layer 4 configure a passive component as a capacitor. A current path of the first lower electrode 31A, the first conduction path 5A, the semiconductor substrate 1, the second conduction path 5B, and the second lower electrode 31B is configured between the first lower electrode 31A and the second lower electrode 31B. In short, the electronic component 102 is a capacitor that uses the first terminal electrode 81 and the second terminal electrode 82 as a surface-mount connection terminal.
The semiconductor substrate 1 is a silicon impurity semiconductor substrate. In the electronic component 102 according to the present exemplary embodiment, the semiconductor substrate 1 configures a portion of a path of a current flowing into the passive component. Therefore, a current flows into the semiconductor substrate 1 in approximately the same direction as the direction into which the current flowing into the lower electrode 31A flows. The current flowing into the semiconductor substrate 1 is a portion of the path of the current flowing into the capacitor, so that, unlike the eddy current, the current is not loss.
Although the above example exemplifies the electronic component including the first terminal electrode 81 and the second terminal electrode 82, the present disclosure is similarly applicable to an electronic component including a capacitor configured by the first lower electrode 31A, the dielectric layer 4, and the upper electrode 32.
The third exemplary embodiment exemplifies an electronic component in which a portion of a path of a current flowing into a passive component is configured by a portion of the semiconductor substrate.
The electronic component 103 includes a semiconductor substrate 1, and a dielectric layer 4 and a substrate electrode 34 that are provided on the semiconductor substrate 1. The dielectric layer 4 corresponds to a portion of a non-conductor layer according to the present disclosure. A dielectric layer electrode 35 is provided on the upper surface of the dielectric layer 4. The dielectric layer electrode 35 is an example of a conductor layer according to the present disclosure.
In the electronic component 103 according to the present exemplary embodiment, an electrode is not provided under the dielectric layer 4, and the semiconductor substrate 1 functions as a lower electrode of the dielectric layer 4.
A passivation layer 6 covering the substrate electrode 34, the dielectric layer 4, and the dielectric layer electrode 35 is provided on the surface of the semiconductor substrate 1.
A first terminal electrode 81 and a second terminal electrode 82 are provided on the surface of the passivation layer 6. A first extended electrode 71 electrically connecting the first terminal electrode 81 and the substrate electrode 34 is provided between the first terminal electrode 81 and the substrate electrode 34, and a second extended electrode 72 electrically connecting the second terminal electrode 82 and the dielectric layer electrode 35 is provided between the second terminal electrode 82 and the dielectric layer electrode 35.
The surface of the passivation layer 6, a portion of the surface of the first terminal electrode 81, and a portion of the surface of the second terminal electrode 82 are covered with a solder resist film 9.
The dielectric layer 4, and the semiconductor substrate 1 and the dielectric layer electrode 35 that are provided across the dielectric layer 4 configure a passive component as a capacitor. In short, the electronic component 103 is a capacitor that uses the first terminal electrode 81 and the second terminal electrode 82 as a surface-mount connection terminal.
The semiconductor substrate 1 is a silicon impurity semiconductor substrate. In the electronic component 103 according to the present exemplary embodiment, the semiconductor substrate 1 configures a portion of a path of a current flowing into the passive component (the capacitor). Unlike an eddy current, the current is not loss.
Although the above example exemplifies the electronic component including the first terminal electrode 81 and the second terminal electrode 82, the present disclosure is similarly applicable to an electronic component including a capacitor configured by the semiconductor substrate 1, the dielectric layer 4, dielectric layer electrode 35, and the substrate electrode 34.
The fourth exemplary embodiment exemplifies an electronic component including an inductor.
The electronic component 104 includes a semiconductor substrate 1, insulator layers 21 and 22 that are provided on the semiconductor substrate 1, conductor patterns 36A and 36B that are provided on the insulator layer 21, conductor patterns 37A and 37B that are provided on the insulator layer 22, and conductor patterns 38A and 38B that are provided on the insulator layer 22. The conductor patterns 36A, 36B, 37A, 37B, 38A, and 38B correspond to a conductor pattern according to the present disclosure.
The insulator layer 21 includes conduction paths 5A and 5B passing through the insulator layer 21 and electrically connecting the conductor patterns 36A and 36B and the semiconductor substrate 1.
A passivation layer 6 covering the insulator layers 21 and 22 and the conductor patterns 37A and 37B is provided on the surface of the semiconductor substrate 1.
A first terminal electrode 81 and a second terminal electrode 82 are provided on the surface of the passivation layer 6. A first extended electrode 71 electrically connecting the first terminal electrode 81 and the conductor pattern 37A is provided between the first terminal electrode 81 and the conductor pattern 37A, and a second extended electrode 72 electrically connecting the second terminal electrode 82 and the conductor pattern 37B is provided between the second terminal electrode 82 and the conductor pattern 37B.
The surface of the passivation layer 6, a portion of the surface of the first terminal electrode 81, and a portion of the surface of the second terminal electrode 82 are covered with a solder resist film 9.
The semiconductor substrate 1 is a silicon impurity semiconductor substrate. The conductor patterns 36A, 36B, 37A, and 37B and a portion of the semiconductor substrate 1 configure a passive component as an inductor. In short, the electronic component 104 is an inductor that uses the first terminal electrode 81 and the second terminal electrode 82 as a surface-mount connection terminal.
Herein, a configuration of an electronic component as a comparative example of the present exemplary embodiment is shown in
In
In contrast, in the electronic component 104 of the present exemplary embodiment, the semiconductor substrate 1 is not an isolated conductor and configures a portion of a path of a current flowing into the passive component (the inductor). Unlike an eddy current, the current is not loss.
Examples of materials and thickness sizes of each portion of the electronic component 104 described above are shown below.
Subsequently, an example of a method of manufacturing the electronic component 104 will be described based on
The step (1) is a substrate supplying step and supplies a silicon substrate as a semiconductor substrate 1 to manufacturing equipment.
The step (2) is an insulator layer forming step and forms an SiO2 film as an insulator layer 2 by thermally oxidizing the surface of the semiconductor substrate 1.
The step (3) is an insulator layer etching step and forms a hole for forming a conduction path to be shown later by etching a predetermined portion of the insulator layer 2.
The step (4) is a lower conductor pattern forming step, and forms conduction paths 5A and 5B, and conductor patterns 36A and 36B by sputtering Al or Cu on the insulator layer 2.
The step (5) is an insulator layer forming-etching step and forms an SiO2 film as an insulator layer 22 on the upper surface of the conductor patterns 36A and 36B and on the upper surface of the insulator layer 21.
The step (6) is an upper conductor pattern forming step, and forms conductor patterns 37A, 37B, 38A, and 38B by sputtering Al or Cu on the insulator layer 22.
The step (7) is a passivation layer forming step and forms a passivation layer 6 by covering the surface of the semiconductor substrate 1, the insulator layers 21 and 22, and the conductor patterns 37A and 37B with a passivation film.
The step (8) is a passivation layer aperture-forming step and forms an aperture AP in a position in which a first extended electrode and a second extended electrode to be shown later.
The step (9) is a power supply film forming step and forms a power supply film E0 by sputtering a Ti film on the surface of the passivation layer 6 and then sputtering a Cu film on the Ti film.
The step (10) is a pad electrode forming step, and forms pad electrodes E1 and E2 by sputtering a Ni film on the power supply film E0 and then sputtering an Au film on the Ni film.
The step (11) is a power supply film etching step, and forms a first extended electrode (the first extended electrode 71 shown in
The step (12) is a solder resist film forming step and covers with a solder resist film 9 the surface of the passivation layer 6, a portion of the surface of the first terminal electrode 81, and a portion of the surface of the second terminal electrode 82.
Although the above example exemplifies the electronic component including the first terminal electrode 81 and the second terminal electrode 82, the present disclosure is similarly applicable to an electronic component including an inductor configured by the conductor patterns 36A, 36B, 37A, 37B, 38A, and 38B and the insulator layers 21 and 22.
It is to be noted that, although the first, second, and third exemplary embodiments show the electronic component including a capacitor as a passive component, and the fourth exemplary embodiment shows the electronic component including an inductor as a passive component, an electronic component including a passive component including both a capacitor and an inductor is able to be configured similarly. In addition, an electronic component including a passive component including a plurality of capacitors and a plurality of inductors is also able to be configured.
Finally, the present disclosure is not limited to the foregoing exemplary embodiments. Various modifications or changes can be appropriately made by those skilled in the art. The scope of the present disclosure is defined not by the foregoing exemplary embodiments but by the following claims. Furthermore, the scope of the present disclosure is intended to include all possible modifications or changes from the exemplary embodiments within the scopes of the claims and the scopes of equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-090991 | May 2021 | JP | national |
The present application is a continuation of International application No. PCT/JP2022/019748, filed May 10, 2022, which claims priority to Japanese Patent Application No. 2021-090991, filed May 31, 2021, the entire contents of each of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/019748 | May 2022 | US |
| Child | 18513945 | US |
