Patent Application
20090242413
1. Field of the Invention
The present invention relates to semiconductor fabrication.
2. Description of the Related Art
In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
The series of manufacturing operations for defining features on the semiconductor wafers can include an electroplating process for adding material to the surface of the semiconductor wafer. Conventionally, electroplating is performed in a complete wafer electroplating processor with the entire wafer submerged in an electrolyte. During the conventional electroplating process, the wafer is maintained at a negative potential with respect to a positively charged anode plate, wherein the anode plate is substantially equal in size to the wafer. The anode plate is also submerged in the electrolyte and maintained in a position proximate to and parallel with the wafer.
During the plating process the wafer acts as a cathode. Thus, the wafer is required to be electrically connected to a number of electrodes. The number of electrodes are required to be uniformly distributed around a perimeter of the wafer and have substantially matched contact resistances in order to achieve a uniform current distribution across the wafer. In the complete wafer electroplating processor, a non-uniform current distribution across the wafer can result in a non-uniform plating thickness across the wafer.
While the conventional complete wafer electroplating processor is capable of depositing material on the surface of the wafer, there is an ever present need to continue researching and developing improvements in electroplating technology applicable to material deposition during semiconductor wafer fabrication.
In one embodiment, an electroplating head is disclosed. The electroplating head includes a chamber having a fluid entrance and a fluid exit. The chamber is configured to contain a flow of electroplating solution from the fluid entrance to the fluid exit. The electroplating head also includes an anode disposed within the chamber. The anode is configured to be electrically connected to a power supply. The electroplating head further includes a porous resistive material disposed at the fluid exit such that the flow of electroplating solution is required to traverse through the porous resistive material.
In one embodiment, an apparatus for electroplating a semiconductor wafer is disclosed. The apparatus includes a wafer support configured to hold a wafer. The apparatus also includes an electroplating head configured to be disposed over an upper surface of the wafer to be held by the wafer support. The electroplating head is configured to have a processing area defined to be substantially parallel with and proximate to an upper surface of the wafer. The processing area is defined by a long dimension that is at least equal to a diameter of the wafer and a short dimension that is less than the diameter of the wafer. The processing area is further defined as an exterior surface area of a porous resistive material. The apparatus further includes a first electrode disposed at a first location proximate to a first peripheral half of the wafer support. The first electrode is movably configured to electrically contact the wafer to be held by the wafer support. Additionally, the apparatus includes a second electrode disposed at a second location proximate to a second peripheral half of the wafer support that is exclusive of the first peripheral half of the wafer support. The second electrode is movably configured to electrically contact the wafer to be held by the wafer support. The electroplating head and the wafer support are configured to move with respect to one another in a direction extending between the first electrode and the second electrode, such that the electroplating head can traverse over an entirety of the upper surface of the wafer when the wafer is held by the wafer support.
In one embodiment, a method for operating an electroplating head is disclosed. The method includes an operation for disposing an electroplating head over and proximate to an upper surface of a wafer. The method also includes an operation for transferring cations from an anode to an electroplating solution within the electroplating head. In another operation of the method, the electroplating solution is flowed through a porous resistive material to exit the electroplating head and be disposed on the upper surface of the wafer. The method further includes an operation for establishing an electric current between the anode and the upper surface of the wafer through the electroplating solution. The electric current is uniformly distributed by the porous resistive material present between the anode and the upper surface of the wafer. Also, the electric current causes the cations to be attracted to the upper surface of the wafer.
In one embodiment, a method is disclosed for electroplating a semiconductor wafer. The method includes positioning an upper surface of the semiconductor wafer below and proximate to a processing surface of an electroplating head. The processing surface is defined as a porous electrically resistive material. The method also includes flowing an electroplating solution through the electroplating head to exit the electroplating head at the processing surface and be disposed on the upper surface of the semiconductor wafer. During the flow of the electroplating solution through the electroplating head, cations are transferred from an anode to the electroplating solution. The method further includes establishing an electric current between the anode and the upper surface of the semiconductor wafer through the electroplating solution. The electric current is uniformly distributed by the porous electrically resistive material. The electric current causes the cations to be attracted to the upper surface of the semiconductor wafer.
Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
The electroplating head 100 also includes a first anode 115A and a second anode 115B disposed within anode chambers 105A and 105B, respectively. Each of the anodes 115A/115B is configured to be electrically connected to a power supply as indicated by a positive polarity 117. A shape and an orientation of each anode 115A/115B within its respective anode chamber 105A/105B can be defined in a number of different ways. Though the anodes 115A/115B and associated anode chambers 105A/105B can be configured in various ways within the electroplating head 100, it is desirable to establish the anodes 115A/115B and associated anode chambers 105A/105B in a manner that will provide a substantially uniform distribution of cations throughout the electroplating solution within the main chamber 105.
In one embodiment, the anodes 115A/115B are disposed with their respective anode chambers 105A/105B in a vertical orientation. The vertical orientation of the anodes 115A/115B enables natural circulation of an electroplating solution present within the respective anode chambers 105A/105B. The natural circulation can be induced by gravity acting upon particulate materials released from the anodes 115A/115B during the electroplating process. Also, it should be appreciated that the vertical orientation of the anodes 115A/115B corresponds to a perpendicular orientation of the anodes 115A/115B with respect to the wafer 307.
During the electroplating process, anode polarization can occur when solubility limits of dissolving ions cause precipitation of salts at the anode surface. The precipitated salts cause the anode to be insulated from the surrounding electroplating solution. The anode polarization effect is generally associated with exceeding a critical current flux during the electroplating process. As the precipitated salts proceed to insulate the anode, decreasing areas of uninsulated anode become responsible for providing an increased current flux. As the current flux increases at the uninsulated anode areas, a precipitate cascade results in a shut-down of reactions at the anode.
The vertical orientation of anodes within the anode chambers, as previously described, provides for mass transfer within anode chambers via natural convection, thus resulting in circulation of the electroplating solution within the anode chambers. The circulation of electroplating solution within the anode chambers prevents adhesion of precipitated salts to surfaces of the anode. It should be appreciated that the vertical orientation of each anode within its respective anode chamber, as provided by the present invention, avoids electroplating head design complexity, electroplating process complexity, and increased expense associated with having to mechanically circulate electroplating solution in order to reduce deposition of precipitated salts on the anode. Also, due to the reduction in salt deposition on the anode, the vertical orientation of each anode allows for an increase in a maximum allowable current flux.
While the embodiment of
With respect to
During operation, each membrane 109A and 109B is defined to allow cations to pass from the anode chambers 105A and 105B, respectively, to the main chamber 105, as indicated by arrows 303. Also, the membranes 109A/109B are configured to prevent passage into the main chamber 105 of materials, e.g., particles and gases, from the anode chambers 105A/105B that could be detrimental to the electroplating process. In one embodiment, the membrane 109A/109B is defined by a fluorocarbon material. Also, in one embodiment, the membrane 109A/109B is defined to have a pore size, i.e., average pore diameter, within a range extending from about 0.2 micrometer to about 0.05 micrometer. The pore size of the membranes 109A/109B is sufficient to allow passage of cations from the anode chamber 105A/105B to the main chamber 105, without allowing passage from the anode chamber 105A/105B to the main chamber 105 of particulate materials generated by anodic reactions. Therefore, using the membranes 109A/109B to separate the analyte from the catalyte, as provided by the present invention, avoids problems associated with unwanted foreign particle transport from the anode to the wafer during the electroplating process.
In one embodiment, key organic additives are included within the catalyte to enhance the electroplating process performance at the cathode, i.e., wafer. In conventional electroplating systems where the anode and cathode interface directly with the same electroplating solution, these key organic additives are vulnerable to being consumed by the anode, thus reducing the additives available for the electroplating process at the cathode without replenishment of these additives. Consumption of the key organic additives by the anode is particularly problematic in the presence of copper (Cu) metal. The membranes 109A/109B of the present invention, however, serve to prevent these key organic additives present in the catalyte of the main chamber 105 from mixing with the analyte or being exposed to the copper electrodes in the anode chambers 105A/105B. Thus, due to the membranes 109A/109B, the key organic additives are not exposed to the anodes 115A/1115B. Also, since the catalyte chemistry and the analyte chemistry can be separately controlled, a concentration of the key organic additives in the catalyte can be more closely controlled.
Further with respect to
During operation, a voltage potential is maintained between the anodes 115A/115B and the wafer 307, as indicated by a negative polarity 309. Thus, an electric current is established between the anodes 115A/115B and the wafer 307 via the electroplating solution (catalyte and analyte). The electric current causes metal ions (cations) produced at the anode to diffuse through the membranes 109A/109B to be carried by the catalyte through the porous resistive material 119 to the wafer 307 where plating occurs. The porous resistive material 119 serves to uniformly distribute the electric current established between the anodes 115A/115B and the wafer 307. Establishment of a more uniformly distributed electric current across the wafer 307 surface results in a more uniform material deposition. Thus, the porous resistive material 119 serves to provide a more uniform material deposition across the wafer surface.
In various embodiments, the porous resistive material 119 is defined as a porous ceramic, a porous glass, or a porous polymeric material. In one embodiment, the porous resistive material 119 is defined as aluminum oxide (Al2O3). In one embodiment, the porous resistive material 119 is defined to have a pore size, i.e., average pore diameter, within a range extending from about 30 micrometer to about 200 micrometers. It should be understood that the porous resistive material 119 of the present invention can be defined by any material capable of providing sufficient throughput of electroplating solution and sufficient pore/solid ratio to provide the required effective resistivity that yields electric current distribution uniformity.
As previously mentioned, the processing area 201 is defined by the lower surface of the porous resistive material 119 disposed at the fluid exit 112 of the electroplating head 100. With respect to
During the electroplating process, the wafer 307 is held by a wafer support 403. Each of a first electrode 405A and a second electrode 405B is located proximate to a periphery of the wafer support 403. Additionally, the second electrode 405B is located at a position that is substantially opposite from the first electrode 405A relative to the wafer support 405. In one embodiment, the first electrode 405A is disposed at a first position near the periphery of the wafer support 403, such that the first position resides along a first peripheral half of the wafer support 403. Also, in the same embodiment, the second electrode 405B is disposed at a second position near the periphery of the wafer support 403, such that the second position resides along a second peripheral half of the wafer support 403 that is exclusive of the first peripheral half of the wafer support 403.
Each of the first electrode 405A and the second electrode 405B is configured to be moved to electrically connect to and disconnect from the wafer 307 as indicated by arrows 407A and 407B, respectively. It should be appreciated that the movement of the electrodes 405A and 405B to connect with and disconnect from the wafer 307 can be conducted in an essentially limitless number of ways. For example, in one embodiment, the electrodes 405A and 405B can be moved linearly in a plane aligned with the wafer. In another embodiment, the electrodes 405A and 405B having a sufficient elongated shape and being oriented in a coplanar arrangement with the wafer 307 can be moved in a rotational manner to contact the wafer. Also, it should be appreciated that the shape of the electrodes 405A and 405B can be defined in a number of different ways. For example, in one embodiment, the electrodes 405A and 405B can be substantially rectangular in shape. In another embodiment, the electrodes 405A and 405B can be rectangular in shape with the exception of a wafer contacting edge which can be defined to follow a curvature of the wafer periphery. In yet another embodiment, the electrodes 405A and 405B can be C-shaped. It should be understood, that the present invention requires at least two electrodes that can be independently manipulated to electrically connect with and disconnect from a wafer 307.
Also with respect to
During the electroplating process, the anodes 115A/115B and at least one of the first and second electrodes 405A/405B are electrically connected to a power supply such that a voltage potential exist therebetween. With respect to
The first electrode 405A remains connected to the wafer 307 as the electroplating head 100 traverses away from the second electrode 405B toward the first electrode 405A. In one embodiment, the second electrode 405B is maintained in the retracted position until the electroplating head 100 and meniscus 305 is a sufficient distance away from the second electrode 405B to ensure that the second electrode 405B is not exposed to electroplating solution.
Also, connection of the first electrode 405A and the second electrode 405B to the wafer 307 is managed to optimize a current distribution present at the portion of the upper surface of the wafer 307 that is in contact with the meniscus 305. In one embodiment, it is desirable to maintain a substantially uniform current distribution at an interface between the meniscus 305 and the wafer 307 as the electroplating head 100 traverses over the wafer 307. It should be appreciated, that maintaining the electroplating head 100 a sufficient distance away from the connected electrode allows the current distribution at the interface between the meniscus 305 and the wafer 307 to be more uniformly distributed. Thus, in one embodiment, transition from connection of the first electrode 405A to connection of the second electrode 405B occurs when the processing area 201 of the electroplating head 100 is substantially near a centerline of the upper surface of the wafer 307, wherein the centerline is oriented to be perpendicular to a traversal direction of the electroplating head 100.
During transition from connection of the first electrode 405A to connection of the second electrode 405B, the connection of the first electrode 405A to the wafer 307 is maintained until the second electrode 405B is connected. Once the second electrode 405B is connected to the wafer 307, the first electrode 405A is disconnected from the wafer 307. Maintaining at least one electrode connected to the wafer 307 serves to minimize a potential for gaps or deviations in material deposition produced by the electroplating process.
With respect to
The method further includes an operation 607 for confining the electroplating solution disposed on the upper surface of the wafer to form a meniscus of electroplating solution. The meniscus of electroplating solution is maintained within a region between the porous resistive material and the upper surface of the wafer directly below the porous resistive material. In one embodiment, electroplating solution is removed from the meniscus in order to establish a flow of electroplating solution through the meniscus.
In an operation 609, an electric current is established between the anode and the upper surface of the wafer through the electroplating solution. The porous resistive material causes the electric current to be uniformly distributed across the upper surface of the wafer in contact with the meniscus of electroplating solution. The electric current causes the cations within the meniscus of electroplating solution to be attracted to and plated on the upper surface of the wafer. The method further includes an operation 611 in which the electroplating head and wafer are controlled to be moved with respect to each other. In one embodiment, the wafer is maintained in a fixed position and the electroplating head is moved over the wafer such that an entirety of the upper surface of the wafer is exposed to the meniscus of electroplating solution. In another embodiment, the electroplating head is maintained in a fixed position and the wafer is moved under the electroplating head such that an entirety of the upper surface of the wafer is exposed to the meniscus of electroplating solution.
In contrast to the present invention, conventional electroplating systems require systematic replenishment, or spiking, of the electroplating solution. The systematic replenishment of the electroplating solution requires sophisticated real-time chemical assay capability to determine whether the electroplating solution is within process control limits. Also, the convention electroplating system requires reclamation of the electroplating solution in order to control process costs.
In contrast to the conventional electroplating system, the electroplating head and associated meniscus of the present invention provides a confined electroplating reaction region that allows for implementation of a low-volume use-and-discard approach for managing chemistry of the electroplating solution, i.e., the separate analyte and catalyte. For example, with the present invention less than 50 milliliters of electroplating solution, i.e., catalyte, is required to plate a 200 millimeter diameter wafer. Therefore, the present invention allows for implementation of a cost effective use-and-discard method for electroplating solution management. Hence, expensive chemical metrology, spiking, recirculation, and reclamation capabilities are not required to maintain tight process control during the electroplating process performed using the electroplating system of the present invention.
Conventional electroplating systems that are configured to provide simultaneous full-wafer plating are unable to plate very resistive barrier films on the wafer surface without a having a low-resistance intermediate film previously applied to the wafer. For example, in the case of Cu plating over a very resistive barrier film, the conventional system requires a PVD Cu seed layer to be applied prior to the full-wafer electroplating process. Without this seed layer, a resistance drop across the wafer will induce a bipolar effect during the full-wafer plating. The bipolar effect results in de-plating and etching within a region adjacent to electrodes contacting the wafer. Use of the porous resistive material, as described with respect to the present invention, allows effects due to a resistivity of the upper surface of the wafer, particularly at the wafer edges, to be decoupled and minimized, thereby improving the uniformity of the subsequent plating process.
Also, the conventional full-wafer electroplating system requires uniformly distributed electrodes about the periphery of the wafer, wherein a resistance for each of the uniformly distributed electrodes is matched. In the conventional full-wafer electroplating system, the presence of an asymmetric contact resistance from one electrode to another will cause a non-uniform current distribution across the wafer, thus resulting in a non-uniform material deposition across the wafer. Use of the porous resistive material, as described with respect to the present invention, allows the current flux to be uniformly distributed across the wafer surface area being plated, regardless of the number of electrodes and contact resistance of the electrodes.
While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.
This application is a divisional application of U.S. patent application Ser. No. 10/879,396, filed on Jun. 28, 2004, the disclosure of which is incorporated in its entirety herein by reference. This application is related to U.S. patent application Ser. No. 10/879,263, filed on Jun. 28, 2004, and entitled “Method and Apparatus for Plating Semiconductor Wafers.” The disclosure of this related application is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10879396 | Jun 2004 | US |
| Child | 12482171 | US |
