Claims
- 1. An ESD protection circuit comprising:
a gateable channel disposed between first and second lines; a first filter to receive a signal of the first line and to filter the signal to establish a first output signal; a second filter to receive and filter the signal to establish a second output signal; and logic circuitry to enable the gateable channel based on the first and second signals.
- 2. The circuit according to claim 1, in which the logic circuitry disables the gateable channel when it determines a non-ESD event.
- 3. The circuit according to claim 2, in which the logic circuitry enables the gateable channel when it determines an ESD event and disables the gateable channel when it determines a non-ESD event.
- 4. The circuit of claim 1, in which the first filter comprises a low-pass filter.
- 5. The circuit of claim 4, in which the second filter comprises a high-pass filter.
- 6. The circuit of claim 1, in which
the first filter comprises a low-pass filter having a frequency cut-off and operable to pass a DC component, and the second filter comprises a high-pass filter having a frequency response to pass frequencies greater than the frequency cut-off of the first filter and operable to block a DC component of the signal received.
- 7. The circuit of claim 6,
the first line to carry a supply signal; and the first and second filters in combination with the logic circuitry to distinguish different slew-rate transients.
- 8. The circuit of claim 6, the first and second filters in combination with the logic circuitry to
discern an ESD event from a non-ESD event; drive the gateable channel with a first level upon determining an ESD event, and drive the gateable channel with a second level different from the first level upon determining a non-ESD event.
- 9. The circuit of claim 8,
the logic circuitry to enable the gateable channel when
the first output signal is below a first predetermined threshold, and the second output signal exceeds a second predetermined threshold; and the logic circuitry to disable the gateable channel when
the first output signal exceeds the first predetermined threshold.
- 10. The claim of claim 9, the logic circuitry further to disable the gateable channel when the second output signal is less than the second predetermined threshold.
- 11. The circuit of claim 9, in which:
the gateable channel comprises:
an N-channel MOSFET having its channel disposed between the first and second lines, and a gate to receive a bias to affect a conductivity of the channel; and the logic circuitry comprises:
an inverter to drive the gate of the N-channel MOSFET; and a NAND gate to drive the inverter with a signal based on the first and second output signals.
- 12. The circuit of claim 11, in which
the NAND gate comprises at least first and second inputs; the first and second inputs of the NAND gate to be driven by the first and second output signals respectively; and the logic circuitry further comprises a second inverter to invert the first output signal and to drive the first input of the NAND gate with the first output signal inverted.
- 13. The circuit of claim 12, in which the second inverter comprises a tripping point defining the first threshold level; and the NAND gate comprises a tripping point defining the first threshold level.
- 14. The circuit of claim 1, in which
the first line comprises a supply bus; and the first filter comprises low-pass filter having a time constant characteristic of magnitude less than a predetermined power-up time constant for the supply bus.
- 15. The circuit of claim 14, in which the second filter comprises a high-pass filter having a frequency entry in the vicinity of the cut-off frequency of the low-pass filter.
- 16. The circuit of claim 1, in which the first filter comprises a time constant characteristic substantially greater than the ramp-up duration of a human body modeled ESD transient.
- 17. The circuit of claim 1, further comprising a diode to be reversed biased between the first line and the second line.
- 18. The circuit of claim 1, further comprising:
an I/O pad; and clamping devices between the I/O pad and respective first and second lines.
- 19. The circuit according to claim 18, in which the clamping devices comprise:
a first diode between the I/O pad and the first line; and a second diode between the I/O pad and the second line.
- 20. A semiconductor device comprising:
a shunting device between first and second supply buses; a first conditioning circuit to receive and condition a signal of the first supply bus in accordance with a first frequency response; a second conditioning circuit to receive and condition a signal of the first supply bus in accordance with a second frequency response; and control logic to operate the shunting device based on the signals conditioned by the first and second conditioning circuits.
- 21. The device of claim 20, in which the first conditioning circuit comprises a high-pass filter.
- 22. The device of claim 21, the high-pass filter to filter a signal of the first supply line relative to the second supply line.
- 23. The device of claim 22, in which the second conditioning circuit comprises a low-pass filter.
- 24. The device of claim 20, in which the control logic is operable to:
AND the first and second conditioned signals to obtain a control signal, and operate the shunting device based on the control signal.
- 25. The device of claim 20, in which the control logic comprises:
a NAND circuit to
receive signals processed by the first and second conditioning circuits, and generate an output signal based on a NAND operative of the signals received; and an inverter to enable the shunting device based on the output signal of the NAND circuit.
- 26. The device of claim 25, in which the control logic further comprises an inverter to receive and invert the signal conditioned by the first conditioning circuit and to drive an input of the NAND circuit with the inverted signal.
- 27. The device of claim 25, in which
the shunting device comprises a transistor having a gateable channel disposed between the first and second buses; and the inverter to enable the transistor based on at least one of the signal of the first supply line and the output signal of the NAND circuit.
- 28. The device of claim 27, further comprising:
a pad; a first diode between the pad and a first supply line; and a second diode between the pad and a second supply line.
- 29. The device of claim 27, in which the inverter comprises:
a P-channel transistor and an N-channel transistor; the N and P-channel transistors disposed with their channels electrically in series and between the first and second supply lines; gates of the N and P-channel transistors to be driven by the NAND circuit; and drains of the N and P-channel transistors to drive the transistor of the shunting device.
- 30. The device of claim 27, in which the first conditioning circuit comprises a resistive element and capacitor disposed serially between the first and second supply lines, and an intermediate node between the resistive element and capacitor to establish a signal for driving a first input of the NAND circuit.
- 31. The device of claim 30, in which the second conditioning circuit comprises a capacitor and resistive element disposed serially between the first and second supply lines, and an intermediate node between the capacitor and the resistive element to establish a signal for driving a second input of the NAND circuit.
- 32. The device of claim 31, in which the first conditioning circuit further comprises an inverter to receive and invert a signal of the intermediate node and to drive the second input of the NAND circuit with the inverted signal.
- 33. An integrated circuit comprising:
a plurality of pads to interface the integrated circuit; first and second supply buses coupled to first and second pads respectively of the plurality; a switch operable to selectably short the first and second supply buses; and a discrimination circuit to
discern an ESD event from non-ESD events, and enable the switch dependent on the discernment.
- 34. The circuit of claim 33, in which the discrimination circuit is operable to discern at least one of a power-up and noise event on the first supply bus as a non-ESD event.
- 35. The circuit of claim 33, in which the selectable switch comprises an NMOS device.
- 36. The circuit of claim 35, in which the discrimination circuit comprises:
a low-pass filter coupled to the first supply bus to receive and filter a signal thereof per a first frequency response; a high-pass filter coupled to the first supply bus to receive and filter a signal thereof per a second frequency response; and control circuitry to drive the NMOS device based on the signal filtered by the low-pass filter and the signal filtered by the high-pass filter.
- 37. The circuit of claim 36, in which the low-pass filter comprises a frequency response characterized with a time-constant substantially less than a time-constant associated with a non-ESD event of the first supply bus when the first supply bus is initially in an un-powered state.
- 38. The circuit of claim 37, in which the high-pass filter comprises a transfer function to attenuate frequency components of a power-up event on the first supply bus.
- 39. The circuit of claim 36, in which the low-pass filter comprises a time constant less than that of a voltage ramp-up for the first supply bus and greater than that of a human model electrostatic discharge event.
- 40. The circuit of claim 36, in which the low-pass filter comprises a time constant of at least 500 nS.
- 41. The circuit of claim 33, further comprising a plurality of I/O circuits, each I/O circuit comprising:
an I/O pad of the plurality of pads; and first and second clamping diodes disposed electrically between the I/O pad and respective first and second supply busses; and one each of the selectable switch and the discrimination circuit proximate the I/O pads.
- 42. A method of operating a semiconductor device, comprising:
monitoring a signal of a supply line; checking a transient on the supply line; and checking a power signal on the supply line, shunting current of the supply line based on the checking the transient and the checking the power signal.
- 43. The method of claim 42, in which
the monitoring monitors the signal level relative to a level of a second supply line; the checking the transient comprises determining a transition-rate of the signal on the first supply line; the checking the power signal comprises determining a presence thereof, and the shunting comprises shorting the first supply line to the second supply line during at least a portion of a rapid transient event when so determined by the checking.
- 44. The method of claim 43, in which the checking the transient comprises filtering the signal of the first supply line using transfer-function of a high-pass frequency characteristic.
- 45. The method of claim 44, in which the determining the presence of the power signal comprises filtering the signal of the first supply line using another transfer-function of a low-pass frequency characteristic.
- 46. The method of claim 45, in which the determining the presence of the power signal comprises filtering the signal of the first supply line using another transfer function of responsiveness less than the transition speed of an ESD event.
REFERENCE TO RELATED APPLICATION
[0001] This application claims benefit and priority to Provisional Application Serial No. 60/436,699, filed Dec. 27, 2002 and entitled ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT, the disclosure of which is hereby incorporated by reference in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60436699 |
Dec 2002 |
US |