Patent Grant
9704850
This application claims priority under 35 U.S.C. §119 to European Patent application no. 15176256.4, filed on 10 Jul. 2015, the contents of which are incorporated by reference herein.
This invention relates to an electrostatic discharge protection device comprising a silicon controlled rectifier.
Integrated circuits generally include an electrostatic discharge (ESD) device for shunting currents which occur during the manufacturing process (e.g. due to discharging of a charged human body (‘human body model’, or ‘HBM’)). In pad-based ESD designs, in particular, the ESD protection is usually placed locally, and is connected to the drains of an output stage MOS. During an ESD event, current shunting occurs after a trigger voltage across the ESD device has been reached. When the ESD device triggers, its voltage drops to a holding voltage. The trigger voltage of the ESD device should therefore be above a maximum operating voltage of the product.
A challenge related to pad-based ESD design is that the ESD protection device often has a higher trigger voltage than the trigger voltage of a driver MOS device to be protected. Triggering of the MOS devices may thus occur earlier than triggering of the ESD device when the gate voltage of the driver MOS is uncontrolled and unknown during an ESD event. An early trigger of the MOS device is unwanted because it may lead to immediate failure.
Silicon controlled rectifiers are often used as an ESD protection device for pad-based ESD protection. The current shunting capacity per unit of area of SCR's is typically superior to that of gate-grounded NMOS (ggNMOS) devices. However, traditional SCR designs typically have a trigger voltage that is too high to be usable in many designs.
Furthermore, an SCR typically has low holding voltage (i.e. the voltage at which the current shunting mode operates, after triggering the SCR), which can lead to latch-up during testing or thereafter when an ESD event occurs. Latch-up generally leads to device failure.
Various approaches have been taken in the past for tuning the trigger and holding voltages of an SCR, leads to designs including Medium Voltage Silicon Controlled Rectifiers (MVSCRs) and Low Voltage Silicon Controlled Rectifiers (LVSCRs).
Aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
According to an aspect of the invention, there is provided an electrostatic discharge protection device comprising a silicon controlled rectifier, the silicon controlled rectifier comprising:
a blocking region having a higher resistivity than the region having the second conductivity type, wherein the blocking region is located between the contact region of the first conductivity type and the contact region of the second conductivity type in the region having the second conductivity type, for reducing a trigger voltage of the silicon controlled rectifier.
The provision of the blocking region having a higher resistivity than the region having the second conductivity type may reduce the trigger voltage of the silicon controlled rectifier. In some examples the reduced trigger voltage may allow the silicon controlled rectifier to trigger before triggering of a device (e.g. an output stage MOS) that the ESD protection device is intended to protect. This may avoid failure of the protected device during an ESD event. Accordingly, the reduced trigger voltage that may be provided by the blocking region may allow the device to be used in a wider range of applications (e.g. for applications that require ESD protection for smaller output stage MOS devices).
The device may include a further region having the first conductivity type located adjacent the region having the second conductivity type in the semiconductor substrate. A contact region of the first conductivity type and a contact region of the second conductivity type may be located in the further region having the first conductivity type. This arrangement may allow the failure current of the device (It2) to be increased.
The device may be connected to provide ESD protection that, during an ESD event, may shunt an ESD current from a first node (which may be a power supply rail or I/O pad of the device) to a second node (which may be a ground rail of the device).
In one example, the contact region of the first conductivity type and the contact region of the second conductivity type located in the region having the first conductivity type are connected to a first node of the device. The contact region of the first conductivity type and the contact region of the second conductivity type located in the further region having the first conductivity type may also be connected to the first node. In this way, an ESD current may be received by the silicon controlled rectifier for shunting the current away from a device under protection. The contact region of the first conductivity type and the contact region of the second conductivity type located in the region having the second conductivity type may be connected to a second node of the device, e.g. to allow the ESD current to be shunted to ground.
The device may include a further contact region of the first conductivity type located in the region having the second conductivity type. The contact region of the first conductivity type and the further contact region of the first conductivity type located in the region having the second conductivity type may collectively form a bipolar transistor (e.g. npn) within the region having the second conductivity type. A gate may be provided for applying a potential to a portion of the region having the second conductivity type located in-between the contact region of the first conductivity type and the further contact region of the first conductivity type. The gate may be connected to a slew rate detection circuit. In another example, the gate may be connected to the second node of the device.
The device may include a layer having the first conductivity type extending beneath the region having the second conductivity type in the substrate for isolating the region having the second conductivity type from an underlying region of the substrate. The layer may be in contact with the region(s) having the first conductivity type and may provide a current path between them.
In some examples, certain characteristics of the blocking region may be selected for tuning the trigger voltage and/or holding voltage of the silicon controlled rectifier. For instance, the resistivity of the blocking region may be selected according to a desired trigger voltage. The resistivity of the blocking region may be selected by selecting a doping level of the blocking region. For example the blocking region may be undoped and/or may have a lower doping level than the region having the second conductivity type. As described in more detail below, the blocking region may be pinched/narrowed by the layer having the first conductivity type located beneath it in the substrate. The shape/dimensions of the blocking region may also be selected according to the desired trigger voltage. For instance a dimension of the blocking region extending between the contact region of the first conductivity type and the contact region of the second conductivity type in the region having the second conductivity type may be in the range 1 μm≦W≦2 μm.
The first conductivity type and the second conductivity type are different conductivity types. Accordingly, the first conductivity type may be n-type and the second conductivity type may be p-type. Nevertheless, it is also envisaged that the first conductivity type may be p-type and the second conductivity type may be n-type. It is envisaged that the substrate may have the second conductivity type.
According to an aspect of the invention, there is provided an electrostatic discharge protection device comprising a silicon controlled rectifier, the silicon controlled rectifier comprising:
a first n-type region located in a semiconductor substrate;
a first p-type region located adjacent the first n-type region in the semiconductor substrate;
an n-type contact region and a p-type contact region located in the first n-type region;
an n-type contact region and a p-type contact region located in the first p-type region, and
a blocking region having a higher resistivity than the first p-type region, wherein the blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.
According to another aspect of the invention, there is provided an electrostatic discharge protection circuit including an electrostatic discharge protection device of the kind described above.
According to a further aspect of the invention, there is provided an integrated circuit including an electrostatic discharge protection circuit of the kind described above.
Embodiments of the present disclosure will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:
Embodiments of the present disclosure are described in the following with reference to the accompanying drawings.
Embodiments of this disclosure may provide an electrostatic discharge (ESD) protection device that comprises a silicon controlled rectifier (SCR). The device can be provided in a semiconductor substrate, such as a silicon substrate.
The following embodiments are described in the context of devices for which the first conductivity type is n-type and the second conductivity type is p-type. Nevertheless, as noted above, it is envisaged that the first conductivity type may be p-type and the second conductivity type may be n-type.
The device includes region having a first conductivity type (in the examples described below, a first n-type region) located in the substrate. The device includes region having a second conductivity type (in the examples described below, a first p-type region), which is also located in the substrate. The region having the second conductivity type may be located adjacent the region having the first conductivity type in the substrate. Contact regions of the first and second conductivity type may be provided for each region. The contact regions may be more highly doped (n+, p+) than the n regions in which they are located.
The device further includes a blocking region. The blocking region may be located between a contact region of the first conductivity type and a contact region of the second conductivity type in the region having the second conductivity type. The blocking region may have a resistivity that is higher than the resistivity of the surrounding region having the second conductivity type. As will be explained in more detail below, the provision of the blocking region between the contact regions in the region having the second conductivity type may reduce a trigger voltage of the silicon controlled rectifier. Reduction of the trigger voltage may allow an ESD protection device to be used in a wide range of applications, including for instance those that require a lower trigger voltage than may normally be achieved using a conventional silicon controlled rectifier.
The device 10 includes a semiconductor substrate 8, which may be a silicon substrate and which may be p-doped. A first n-type region 4 is located in the substrate 8. A first p-type region 6 is also located in the substrate 8. As shown in
The device 10 includes a number of contact regions. For instance, an n-type contact region 14 and a p-type contact region 12 are located in the first n-type region 4. As is known in the art of ESD protection devices including silicon controlled rectifiers, the p-type contact region 12 in the first n-type region 4 may form an anode of the silicon controlled rectifier. Contact regions are also provided in the first p-type region. As shown in
Typically, the contact regions have a higher doping level (n+, p+) than the n-type and p-type regions within which they are located. The first p-type region 6 may only be lightly doped (p−).
The device further includes a blocking region 20. The blocking region 20 is located in the first p-type region 6. More particularly, the blocking region 20 is located between the n-type contact region 16 and the p-type contact region 24 in the first p-type region 6. In the present embodiment, the blocking region 20 divides the first p-type region 6 into two parts, a first part of which contains the n-type contact region 16 and a second part of which contains the p-type contact region 24.
The blocking region 20 has a higher electrical resistivity than the first p-type region 6 within which it is located. The higher resistivity of the blocking region may be implemented in a number of ways. For instance, the blocking region 20 may have a lower doping level than the surrounding p-type material of the first p-type region 6, or indeed may be undoped. Combined with the doping conditions of the n-type layer 2 beneath it (to be described in more detail below), the p-type area in the blocking region may be narrowed in height (the remaining part being lightly n-doped due to the process steps in involved in forming the n-type layer 2). The narrowed p-type channel in blocking region 20 may have an even further increased resistance compared to a region which is completely p-type. It is also envisaged that the resistance of the blocking region 20 may be varied by varying a width of the blocking region (measured along the dimension extending between the n-type contact region 16 and the p-type contact region 24 in the first p-type region 6 (as indicated by the arrow in
The provision of the blocking region 20 can lower the trigger voltage of the SCR since the resistance between the area where avalanching occurs (as the SCR activates) and the p-type contact region 24 in the first p-type region 8 is increased. Due to the increased resistance provided by the blocking region 20, for a given current (comprising charge carriers created by avalanching during activation of the SCR) through the blocking region 20, there would be a higher potential across the blocking region 20, whereby the potential below the n-type contact region 24 is increased. This may lower the trigger voltage of the SCR.
In the present example, the first n-type region 4 is located at a first side of the first p-type region 6.
The second n-type contact region 4A can also include contact regions. In this example, the second n-type region 4A includes an n-type contact region 28 and a p-type contact region 26. This arrangement can provide a pnp action during an ESD event. In particular, the p-type contact region 26 can form an emitter for the pnp action, the second n-type region 4A can provide the base and the p-type region 6 (and contact region 24) can form the collector.
In the present embodiment, an n-type layer 2 (which may, for instance, comprise a deep n-well or buried well) may be provided beneath the first p-type region 6 of the device 10. This n-type layer 2 may, in combination with the n-type region 5, isolate the first p-type region 6 from the underlying substrate 8. The n-type layer 2 may also provide a current path through the device 10 as explained below. As shown in
As shown in
Since the gate 18 in this example is connected to a low potential (VI.), and the contact region 30 is connected to a high potential (Vhigh), large electric fields may occur between the contact region 30 and gate 18. It is therefore that at this particular location that avalanching may take place during triggering of the device 10. Properties of the gate 18, like its thickness, may affect the electric field. Therewith the voltage at which avalanching starts (and triggering occurs) may be controlled by altering the configuration of the gate 18.
During operation, in an ESD event, the SCR of the device may be triggered by avalanching that occurs near to the gate 18 and the further n-type contact region 30. The avalanching current increases strongly with increasing electric field (and with voltage if the gate voltage is kept constant). Triggering of the device may occur when the potential near the n-type contact region 16 is increased such that its pn junction (i.e. the junction between the n-type contact region 16 and the first p-type region 6) starts to conduct. In order to lower the trigger voltage (given the same potential near the n-type contact region 16 to trigger), a strongly increased resistance to the p-type contact region 24 is required. In accordance with embodiments of the disclosure, this strongly increased resistance is embedded in the structure via blocking region 20. As described above, a strongly increased resistance may result from the ‘pinching action’ of the underlying layer 2: only a fraction of the height of blocking region 20 may be p-type. Moreover, the p-type doping level may be lower than the doping level of the first p-type region 6, which may also increase the resistivity of the blocking region 20. In addition, the resistance of the blocking region 20 may be varied by altering the width of blocking region 20.
With continued reference to
The current path through the silicon controlled rectifier is represented by the components contained within the dashed box 94 in
A second current path (denoted by the dashed box labelled 92 in
The third current path 96 (denoted by the dashed box labelled 96 in
Thus, a device 10 according the present disclosure, which includes the blocking region 20, may provide multiple current paths for current flow during an ESD event. These multiple paths may reduce the heating associated with current flow within any particular current path, which may in turn improve the robustness of the device 10 (by increasing the failure current). The resistances 42, 44, 46 may be tuned to determine how much current is taken by each of the current paths explained above in relation to
As described herein, the resistance provided by the blocking region 20 within the first p-type region 6 (denoted using reference numeral 42 in
In general, a larger width for the blocking region 20 would result in a decreased trigger voltage for the device 10, while a narrower width for the blocking region 20 would result in a correspondingly higher trigger voltage for the device 10. Accordingly, the provision of the blocking region 20 within the first p-type region 6 of the device conveniently may allow for the trigger voltage of a device of the kind described herein to be tuned for a particular application. It is envisaged that the thickness of the gate 18, which would affect the avalanching behaviour of the device, may also influence the trigger voltage of the device.
It is further envisaged that the width of the blocking region 20 may also influence the holding voltage of the silicon controlled rectifier, thereby to tune the holding voltage to a level above the operating voltage for providing latch-up protection. These include:
From the above, it will be appreciated that there are a significant number of parameters for varying both the trigger voltage and holding voltage of a device of the kind described herein. Moreover, by embedding multiple current shunting paths within a device of the kind described herein, with their relative strengths determined by independent parameters such as those noted above, it is possible to allow for independent control over the trigger voltage, holding voltage and leakage current of a device according to embodiments of this disclosure.
A device according to embodiments of this disclosure may also have a relatively low leakage current. One of the main issues for conventional ESD solutions that are used to protect thin gate oxide devices is the high leakage. A ‘standard’ solution is an ESD protection device with the same gate oxide thickness as the thin gate oxide of the MOS device that is to be protected. Embodiments of this disclosure may allow for the usage of a thicker gate oxide in combination with the blocking layer 20, allowing a trigger voltage comparable to a ‘standard’ thin gate oxide protection. Thicker gate oxides have the advantage of much less leakage.
It is further envisaged that the leakage current of a device described herein can be tuned by varying parameters such as those noted above. For instance, the leakage of the device may be reduced by increasing the length of the gate 18. Moreover, a change in holding voltage, induced by such an increase in the gate length, may be cancelled by tuning the other parameters noted above, such as:
In
Each of the devices tested in
As can be seen in
In addition to this, comparison of plots 52 and 54 in
Embodiments of this disclosure may be used in a wide range of applications.
A device according to an embodiment of this disclosure may also be used as protection for a power supply line. Examples of this are shown in
Embodiments of this disclosure may allow a single device to protect both the IO pads and the power supply line of an integrated circuit using a single ESD protection device by careful engineering of the trigger voltage as described above. An example of this is shown in
Embodiments of this disclosure may allow the creation of a rail clamp that need not include a trigger circuit, which may substantially reduce the area occupied by the clamp on an integrated circuit. This may be achieved by careful engineering of the trigger voltage of the device as illustrated in
By tuning the trigger voltage as described herein, the trigger voltage may be chosen such that it is above the maximum operating voltage Vdd (see plot 104), and also such that the sum of the trigger voltage and the voltage drop from the diode and the bus resistance (see plot 106) falls below the holding voltage of the NMOS driver to be protected (see plot 100).
Embodiments of this disclosure may further be used as a charged device model (CDM) clamp. An example of this is shown in
Accordingly, there has been described an electrostatic discharge protection device including a silicon controlled rectifier, an electrostatic discharge protection circuit including the electrostatic discharge protection device and an integrated circuit including the electrostatic discharge protection circuit. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate. The silicon controlled rectifier also includes a first p-type region located adjacent the first n-type region in the semiconductor substrate. The silicon controlled rectifier further includes an n-type contact region and a p-type contact region located in the first n-type region. The silicon controlled rectifier also includes an n-type contact region and a p-type contact region located in the first p-type region. The silicon controlled rectifier further includes a blocking region having a higher resistivity than the first p-type region. The blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.
Although particular embodiments of the present disclosure have been described, it will be appreciated that many modifications/additions and/or substitutions may be made within the scope of this disclosure.
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| Number | Date | Country | |
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| 20170012036 A1 | Jan 2017 | US |
