1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device, and more particularly, to an ESD protection device of an output driver stage for preventing ESD from flowing into an internal circuit from the output driver stage.
2. Description of the Related Art
When electrostatic discharge (ESD) caused from the human body or machinery flows into an integrated semiconductor chip, internal microcircuits in the semiconductor chip may be damaged or generate errors. The ESD mainly flows into input/output driver stages of the semiconductor chip.
On the other hand, input driver stages of almost all semiconductor chips may include ESD protection devices. When a concept about the ESD for the output driver stages of semiconductor chips was not established, additional ESD protection devices were not used. However, recently, ESD protection devices for preventing ESD that may flow into the output driver stages of the semiconductor chips from flowing into internal circuits have been widely used.
Referring to
However, the diodes DP and DN and the limiting resistor R1 for ESD protection of the output driver stage may result in increase in the entire chip size.
The present invention provides an electrostatic discharge (ESD) protection device of an output driver stage capable of preventing ESD from flowing into an internal circuit in the output driver stage without diodes and limiting resistors.
According to an aspect of the present invention, there is provided an electrostatic discharge (ESD) protection device of an output driver stage, which includes a p-channel metal-oxide-semiconductor (PMOS) transistor having a source connected to a first source voltage and an n-channel metal-oxide-semiconductor (NMOS) transistor having a source connected to a second source voltage, the MOS transistors having gates applied with output signals from an internal circuit and drains connected to the output pad, wherein a distance between contacts formed on a drain region and a gate poly of the MOS transistors is relatively greater than a value according to a predetermined design rule.
According to another aspect of the present invention, there is provided an ESD protection device of an output driver stage, which includes a PMOS transistor P1 having a source connected to a first source voltage and an NMOS transistor having a source connected to a second source voltage, the MOS transistors having gates applied with output signals from an internal circuit and drains connected to the output pad, wherein a resistor is formed between the drain and the output pad of the MOS transistors.
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
An output driver stage 200 includes a p-channel metal-oxide-semiconductor (PMOS) transistor P1 and an n-channel metal-oxide-semiconductor (NMOS) transistor N1, and the PMOS transistor P1 and the NMOS transistor N1 are selectively turned on. In
The ESD protection device of the output driver stage illustrated in
Here, for examples, for the drain resistor, in a MOS transistor manufacturing process, according to a design rule determined in consideration of electromagnetic characteristics, a minimum distance between a contact formed on a drain region and a gate poly is needed. Accordingly, the drain resistor necessarily exists. However, in a case where the MOS transistors are manufactured according to the determined design rule, a value of resistance of the drain resistor is not that high and not that effective for the ESD protection.
In a case where the distance between the contact formed on the drain region and the gate poly is increased, the drain resistor can have an increased value. In this case, referring to
Referring to
Here, the gate poly 301 is disposed at predetermined intervals from the contacts 302 formed on a drain region and the contacts 303 formed on a source region. This applies the same concept as the aforementioned design rule. Here, an active region between the contacts 302 formed on the drain region and the gate poly 301 becomes a drain resistor 310. A value of resistance of the drain resistor 310 is determined by the distance d1 between the contacts 302 formed on the drain region and the gate poly 301. As the distance d1 between the contacts 302 formed on the drain region and the gate poly 301 is closer to a value according to the determined design rule, the value of resistance of the drain resistor 310 decreases. However, as the distance d1 between the contacts 302 formed on the drain region and the gate poly 301 increases, the value of resistance of the drain resistor 310 increases. As the value of resistance of the drain resistor 310 increases, a more amount of ESD flowing into the output pad is consumed.
Therefore, by increasing the distance d1 between the contacts 302 formed on the drain region and the gate poly 301 to be greater than the value according to the determined design rule, the ESD flowing into the output pad can be properly removed by the drain resistor 310 and prevented from flowing into the distance circuit 210, without the conventional diodes DP and DN and limiting resistor R1.
Here, when the distance d1 between the contacts 302 formed on the drain region and the gate poly 301 is increased, an area of the MOS transistor is also increased. However, removing the conventional diodes DP and DN and the limiting resistor R1 is much more effective than increasing the distance d1 between the contacts 302 formed on the drain region and the gate poly 301 to be greater than the value according to the determined design rule, in terms of the chip size. Therefore, a disadvantage of increasing the area of the MOS transistor can be overcome. The distance d1 between the contacts 302 formed on the drain region and the gate poly 301 may be increased by at least 5% from the value according to the determined design rule.
In an active region 400, a number of contacts 402 formed on a drain region and a number of contacts 403 formed on a source region are formed. The resistors may be formed as an active region having a relatively higher impurity concentration or a well region having a relatively lower impurity concentration. If a relatively lower resistance is required, the active region is formed as the resistor, and if a relatively higher resistance is required, the well region is formed as the resistor.
Referring to
The contacts 412 relatively closer to the output pad are connected to the output pad by metal 422. Here, in order to occupy an enough region to consume ESD in preparation for the inflow of the ESD, an overlap distance d2 of the contacts 412 relatively closer to the output pad may be increased by 5% from a value according to the determined design rule. Here, the overlap distance d2 of each of the contacts 412 relatively closer to the output pad means a distance occupied from the corresponding contact to an edge of the active region 410.
In the illustrated example of
In
The electrostatic discharge (ESD) protection device of the output driver stage according to the present invention can prevent ESD that flows from the output pad from flowing into the internal circuit by increasing the drain resistors of the MOS transistors included in the output driver stage or using the active resistor. Therefore, the conventional diodes and limiting resistor are not needed and the entire chip size can be reduced.
While the present invention has been shown and described in connection with the exemplary embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2007-0087349 | Aug 2007 | KR | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/KR2008/004410 | 7/29/2008 | WO | 00 | 2/25/2010 |