Claims
- 1. A method for fabricating an electrostatic discharge protection device for use with a semiconductor chip package of a type having a top surface and an opposite bottom surface and a plurality of lateral surfaces integral with said top and bottom surfaces where the semiconductor chip package has extending therefrom a plurality of connector pins disposed in a spaced apart relationship with respect to each other for insertion into a mating receptacle, said method comprising
- stamping a base to form a plurality of apertures corresponding to the plurality of connector pins such that the at least one row of connector pins pass through the plurality of apertures and to form one or more cuts in the base transverse to the central axis of the base such that an area surrounding each of the plurality of apertures is free to move at an angle relative to a plane of the base;
- depositing a conductive material on said base to provide electrical communication between outer portions of the plurality of apertures; and
- shaping said base to have a resilient bias to urge the outer portions of the plurality of apertures into contact with the connector pins such that the electrostatic discharge protection device has an operative position for connecting a shunt across selected pins of the connector pins and has an inoperative position for disconnecting said shunt to provide electrical isolation between the connector pins where insertion of said semiconductor chip package into said mating receptacle moves the base into the inoperative position by overcoming the inward bias and removal of the semiconductor chip package from the mating receptacle automatically moves the base into said operative position.
- 2. The method according to claim 1 wherein said step of depositing comprises a step of coating a conductive ink onto said base.
- 3. The method according to claim 1 wherein said step of depositing further comprises a step of applying the conductive material in excess over the outer portions of the plurality of apertures to ensure mechanical contact with the connector pins.
- 4. The method according to claim 3 wherein said step of depositing further comprises a step of photo-etching the conductive material to form the apertures.
- 5. The method according to claim 3 wherein said step of depositing further comprises a step of mechanically punching the conductive material to form the apertures.
- 6. The method according to claim 1 wherein said step of depositing comprises a step of laminating a conductive material onto said base.
Parent Case Info
This application is a division of application Ser. No. 08/361,426, filed Dec. 21, 1994, U.S. Pat. No.5,583,733.
US Referenced Citations (11)
Foreign Referenced Citations (5)
Number |
Date |
Country |
0071031 |
Feb 1983 |
EPX |
2348630 |
Apr 1975 |
DEX |
59-13353 |
Jan 1984 |
JPX |
61-148852 |
Nov 1986 |
JPX |
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Non-Patent Literature Citations (2)
Entry |
Middlebrook, Carlton G., "Electrical Shorting Cap," Navy Technical Disclosure Bulletin, vol. 6, No. 3, Mar. 1981, pp. 33-36 (Navy Technology Catalog No. 5260 1530, Navy Case No. 63818). |
Wang, Shay-Ping T., and Ogden, Paul, "Membrane-Type Pin Protector for Pin Grid Array Devices," 1991 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 120-127. |
Divisions (1)
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Number |
Date |
Country |
Parent |
361426 |
Dec 1994 |
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