The present application claims priority from Japanese Patent Application No. 2022-121176 filed on Jul. 29, 2022, the entire contents of which are hereby incorporated by reference.
The disclosure relates to an element array circuit including an element array in which impedance elements are arranged, and to an electromagnetic wave sensor, a temperature sensor, and a strain sensor each including the element array circuit.
A resistor array circuit has been proposed that includes resistors arranged in a matrix. Such a resistor array circuit is usable, for example, as an infrared detection circuit. For example, reference is made to Japanese Unexamined Patent Application Publication (JP-A) No. H08-94443. Such an infrared detection circuit includes infrared-sensitive resistors arranged therein. Examples of the infrared-sensitive resistors may include a thermistor whose resistance value changes with changing temperature.
An element array circuit according to an embodiment of the disclosure includes one or more first wiring lines, a plurality of second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The second wiring lines each extend in a direction different from a direction in which the one or more first wiring lines each extend. The impedance elements are each coupled to both one of the one or more first wiring lines and one of the second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
An electromagnetic wave sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes one or more first wiring lines, a plurality of second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The second wiring lines each extend in a direction different from a direction in which the one or more first wiring lines each extend. The impedance elements are each coupled to both one of the one or more first wiring lines and one of the second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
A temperature sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes one or more first wiring lines, a plurality of second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The second wiring lines each extend in a direction different from a direction in which the one or more first wiring lines each extend. The impedance elements are each coupled to both one of the one or more first wiring lines and one of the second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
A strain sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes one or more first wiring lines, a plurality of second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The second wiring lines each extend in a direction different from a direction in which the one or more first wiring lines each extend. The impedance elements are each coupled to both one of the one or more first wiring lines and one of the second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
An element array circuit according to an embodiment of the disclosure includes a plurality of first wiring lines, one or more second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The one or more second wiring lines each extend in a direction different from a direction in which the first wiring lines each extend. The impedance elements are each coupled to both one of the first wiring lines and one of the one or more second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the one or more second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the one or more second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
An electromagnetic wave sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes a plurality of first wiring lines, one or more second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The one or more second wiring lines each extend in a direction different from a direction in which the first wiring lines each extend. The impedance elements are each coupled to both one of the first wiring lines and one of the one or more second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the one or more second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the one or more second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
A temperature sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes a plurality of first wiring lines, one or more second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The one or more second wiring lines each extend in a direction different from a direction in which the first wiring lines each extend. The impedance elements are each coupled to both one of the first wiring lines and one of the one or more second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the one or more second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the one or more second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
A strain sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes a plurality of first wiring lines, one or more second wiring lines, a plurality of impedance elements, one or more operational amplifiers, one or more conversion elements, and one or more switchers. The one or more second wiring lines each extend in a direction different from a direction in which the first wiring lines each extend. The impedance elements are each coupled to both one of the first wiring lines and one of the one or more second wiring lines. The one or more operational amplifiers each include a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to one of the one or more second wiring lines. The one or more conversion elements are each coupled to the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and each configured to convert a current flowing through one of the one or more second wiring lines that is coupled to the negative input terminal into a voltage. The one or more switchers are each coupled to one of the one or more conversion elements in parallel between the negative input terminal and the output terminal of corresponding one of the one or more operational amplifiers, and are each configured to come into either a conducting state or a nonconducting state.
An element array circuit according to an embodiment of the disclosure includes a first wiring line, a second wiring line, an impedance element, an operational amplifier, and a processor. The second wiring line extends in a direction different from a direction in which the first wiring line extends. The impedance element is coupled to both the first wiring line and the second wiring line. The operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to the second wiring line. The processor is configured to perform charging of a parasitic capacitance parasitic to the second wiring line coupled to the negative input terminal, and measures, after performing the charging, an output voltage resulting from the impedance element and outputted from the output terminal.
An electromagnetic wave sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes a first wiring line, a second wiring line, an impedance element, an operational amplifier, and a processor. The second wiring line extends in a direction different from a direction in which the first wiring line extends. The impedance element is coupled to both the first wiring line and the second wiring line. The operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to the second wiring line. The processor is configured to perform charging of a parasitic capacitance parasitic to the second wiring line coupled to the negative input terminal, and measures, after performing the charging, an output voltage resulting from the impedance element and outputted from the output terminal.
A temperature sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes a first wiring line, a second wiring line, an impedance element, an operational amplifier, and a processor. The second wiring line extends in a direction different from a direction in which the first wiring line extends. The impedance element is coupled to both the first wiring line and the second wiring line. The operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to the second wiring line. The processor is configured to perform charging of a parasitic capacitance parasitic to the second wiring line coupled to the negative input terminal, and measures, after performing the charging, an output voltage resulting from the impedance element and outputted from the output terminal.
A strain sensor according to an embodiment of the disclosure includes an element array circuit. The element array circuit includes a first wiring line, a second wiring line, an impedance element, an operational amplifier, and a processor. The second wiring line extends in a direction different from a direction in which the first wiring line extends. The impedance element is coupled to both the first wiring line and the second wiring line. The operational amplifier includes a positive input terminal, a negative input terminal, and an output terminal. The negative input terminal is couplable to the second wiring line. The processor is configured to perform charging of a parasitic capacitance parasitic to the second wiring line coupled to the negative input terminal, and measures, after performing the charging, an output voltage resulting from the impedance element and outputted from the output terminal.
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the specification, serve to explain the principles of the disclosure.
It is desirable that an element array circuit such as an infrared detection circuit provide a measured value related to, for example, a resistance value quickly with high accuracy.
It is desirable to provide an element array circuit that provides a measured value quickly with high accuracy, and an electromagnetic wave sensor, a temperature sensor, and a strain sensor that each include such an element array circuit.
In the following, some example embodiments of the disclosure are described in detail with reference to the accompanying drawings. Note that the following description is directed to illustrative examples of the disclosure and not to be construed as limiting to the disclosure. Factors including, without limitation, numerical values, shapes, materials, components, positions of the components, and how the components are coupled to each other are illustrative only and not to be construed as limiting to the disclosure. Further, elements in the following example embodiments which are not recited in a most-generic independent claim of the disclosure are optional and may be provided on an as-needed basis. The drawings are schematic and are not intended to be drawn to scale. Throughout the present specification and the drawings, elements having substantially the same function and configuration are denoted with the same reference numerals to avoid any redundant description. In addition, elements that are not directly related to any embodiment of the disclosure are unillustrated in the drawings. Note that the description is given in the following order.
As illustrated in
The row lines A may correspond to a specific but non-limiting example of “one or more first wiring lines” in one embodiment of the disclosure.
The row lines A may each extend in a first direction and may be arranged to be adjacent to each other in a second direction different from the first direction. In the example embodiment illustrated in
The row lines A may each have a first end that is couplable to a direct-current power supply PS1 via corresponding one of switches SWA1 of the row line selector SA, and also couplable to a direct-current power supply PS2 via corresponding one of switches SWA2 of the row line selector SA. In
For convenience, a resistor R selected from among the plurality of resistors R will be referred to as a selected resistor RS. A row line A corresponding to the selected resistor RS, among the plurality of row lines A, will be referred to as a selected row line AS. The row lines A other than the selected row line AS will each be referred to as an unselected row line AU. In performing measurement on the selected resistor RS, one of the switches SWA1 that corresponds to the selected row line AS may be caused to be in a conducting state to thereby cause a first voltage V1 to be applied to the selected row line AS from the direct-current power supply PS1. Further, in performing the measurement on the selected resistor RS, a second voltage V2 not equal to the first voltage V1 may be applied to all the unselected row lines AU from the direct-current power supply PS2 via ones of the switches SWA2 that correspond to the respective unselected row lines AU and are in the conducting state.
By way of example,
The column lines B may correspond to a specific but non-limiting example of “a plurality of second wiring lines” in one embodiment of the disclosure.
The column lines B each extend in a direction different from the direction in which the row lines A each extend. For example, the column lines B may each extend in the second direction, and may be arranged to be adjacent to each other in the first direction different from the second direction. In the example embodiment illustrated in
The column lines B may each have a first end coupled to corresponding one of the operational amplifiers OP. For example, the first end of the column line B1 may be coupled to a negative input terminal T2 of the operational amplifier OP1, the first end of the column line B2 may be coupled to the negative input terminal T2 of the operational amplifier OP2, and the first end of the column line Bn may be coupled to the negative input terminal T2 of the operational amplifier OPn.
To each single column line B, multiple ones of the resistors R may be coupled at their respective second ends. The respective second ends of the resistors R may be opposite to the respective first ends each coupled to corresponding one of the row lines A. In the example embodiment illustrated in
The resistors R may correspond to a specific but non-limiting example of “a plurality of impedance elements” in one embodiment of the disclosure.
The resistors R may each be coupled to both one of the row lines A and one of the column lines B. The resistors R may each have the first end coupled to the one of the row lines A, and the second end coupled to the one of the column lines B. As described above, in the example embodiment illustrated in
The resistor R may be a component of an infrared light receiving device that converts infrared rays condensed by, for example, a lens into an electric signal. In one example, the resistor R may include a resistance change layer whose resistance changes with changing temperature, for example. Examples of the resistance change layer may include a thermistor film. The thermistor film may include, for example, vanadium oxide, amorphous silicon, polycrystalline silicon, a manganese-containing oxide having a spinel crystal structure, titanium oxide, or yttrium-barium-copper oxide. The resistor R may further include an infrared absorption layer adjacent to the thermistor film. The infrared absorption layer may absorb infrared rays and generate heat. The infrared absorption layer may include, for example, silicon oxide (SiO2), aluminum oxide (AlO3), silicon nitride (Si3N4), or aluminum nitride (AlN). In the resistor R, temperatures of the infrared absorption layer and the resistance change layer may change with intensity of received infrared rays, and as a result, the resistance change layer may change in resistance value.
The row line selector SA may include the switches SWA1 (SWA1-1 to SWA1-m) and the switches SWA2 (SWA2-1 to SWA2-m). The switches SWA1 (SWA1-1 to SWA1-m) and the switches SWA2 (SWA2-1 to SWA2-m) may each be switchable between the conducting state and the nonconducting state. The switches SWA1 (SWA1-1 to SWA1-m) may each be provided between corresponding one of the row lines A (A1 to Am) and the direct-current power supply PS1. The switches SWA2 (SWA2-1 to SWA2-m) may each be provided between corresponding one of the row lines A (A1 to Am) and the direct-current power supply PS2.
The row line selector SA may select one row line A to be the selected row line AS, from among the plurality of row lines A. The row line selector SA may couple the selected row line AS to the direct-current power supply PS1, and may couple the unselected row lines AU other than the selected row line AS to the direct-current power supply PS2. The direct-current power supply PS1 may apply the first voltage V1 to the selected row line AS. The direct-current power supply PS2 may apply the second voltage V2 to the unselected row lines AU. The second voltage V2 may be different from the first voltage V1. Operation of the row line selector SA may be controlled by the processor CTRL. For example, a switching operation of the row line selector SA on each of the switches SWA1 (SWA1-1 to SWA1-m) and each of the switches SWA2 (SWA2-1 to SWA2-m) may be executed based on a command from the processor CTRL.
The operational amplifiers OP may each be coupled to corresponding one of the column lines B. The operational amplifiers OP, which are denoted as OP1 to OPn in
The capacitors CP may correspond to a specific but non-limiting example of “one or more conversion elements” in one embodiment of the disclosure.
The capacitors CP are each coupled to both the negative input terminal T2 and the output terminal T3 of corresponding one of the operational amplifiers OP, and each convert a current flowing through one of the column lines B that is coupled to the negative input terminal T2 into a voltage. For example, in the example embodiment illustrated in
The switches SW may correspond to a specific but non-limiting example of “one or more switchers” in one embodiment of the disclosure.
The switches SW may each be coupled to corresponding one of the operational amplifiers OP. The switches SW are each coupled to corresponding one of the capacitors CP in parallel between the negative input terminal T2 and the output terminal T3 of the corresponding one of the operational amplifiers OP. The switches SW are each configured to come into either a conducting state or a nonconducting state. For example, in the example embodiment illustrated in
The processor CTRL may be a microcomputer, for example. The processor CTRL may execute predetermined control processing by causing a central processing unit (CPU) to execute a control program. The processor CTRL may control, for example, a switching operation on each of the switches SW. The processor CTRL may execute a control of: performing charging of a parasitic capacitance parasitic to each of the column lines B; and switching, after performing the charging, one switch SW corresponding to relevant one of the column lines B into the nonconducting state. The processor CTRL may perform the charging of the parasitic capacitance of each of the column lines B by causing the one switch SW corresponding to the relevant one of the column lines B to be in the conducting state and by establishing electrical continuity between: the column line B coupled to the negative input terminal T2 of corresponding one of the operational amplifiers OP; and the output terminal T3 of the corresponding one of the operational amplifier OP.
Further, the processor CTRL may control the switching operation of the row line selector SA. For example, the processor CTRL may cause one switch SWA1 corresponding to the selected row line AS to be in the conducting state and cause the other switches SWA1 corresponding to the unselected row lines AU to be in the nonconducting state. The selected row line As may be one row line A corresponding to the selected resistor RS. The unselected row lines AU may be all the row lines A excluding the selected row line AS.
After performing the charging of the parasitic capacitance of each of the column lines B, the processor CTRL may switch the one switch SW corresponding to the relevant one of the column lines B into the nonconducting state, and may measure an output voltage outputted from the output terminal T3 of one operational amplifier OP corresponding to the relevant one of the column lines B, the output voltage resulting from the selected resistor RS coupled to both the selected row line AS and the relevant one of the column lines B.
A period of time over which the parasitic capacitance of each of the column lines B is to be charged by causing the one switch SW corresponding to the relevant one of the column lines B to be in the conducting state may be longer than a period of time that allows electric charge of one capacitor CP corresponding to the relevant one of the column lines B to be discharged almost completely. For example, the above-described period of time may be longer than five times a product of a capacitance value of the one capacitor CP corresponding to the relevant one of the column lines B and a resistance value of the one switch SW corresponding to the capacitor CP when the switch SW is in the conducting state. Further, the period of time over which the parasitic capacitance of each of the column lines B is to be charged by causing the one switch SW corresponding to the relevant one of the column lines B to be in the conducting state may be longer than five times the product of a capacitance value of the parasitic capacitance of the relevant one of the column lines B and the resistance value of the one switch SW corresponding to the relevant one of the column lines B. One reason for this is that such a length of time allows the parasitic capacitance of each of the column lines B to be sufficiently charged and thus allows for accurate measurement of the output voltage resulting from each of the selected resistors RS.
The direct-current power supplies PS1 and PS2 may each be provided inside the element array circuit 1 or outside the element array circuit 1.
In the element array circuit 1, it is possible to perform measurement on each of the resistors R in the following manner, for example. The following measurement operation may be performed in accordance with a command from the processor CTRL.
Thereafter, one row line corresponding to the selected resistor RS targeted for the measurement may be selected to be the selected row line AS (step S102). For example, the switch SWA1 corresponding to the selected row line AS to which the selected resistor RS is coupled may be caused to be in the conducting state to thereby cause the first voltage V1 to be applied to the selected row line AS. The other switches SWA1 corresponding to the unselected row lines AU may be kept in the nonconducting state. Further, the switches SWA2 corresponding to the unselected row lines AU may be caused to be in the conducting state to thereby cause the second voltage V2 to be applied to the unselected row lines AU. The switch SWA2 corresponding to the selected row line AS may be kept in the nonconducting state.
Thereafter, the switches SW corresponding to the respective column lines B may be caused to be in the conducting state (step S103) to allow for charging of the parasitic capacitances parasitic to the respective column lines B. For example, for each of the column lines B, one switch SW corresponding thereto may be caused to be in the conducting state to thereby establish electrical continuity between: the column line B coupled to the negative input terminal T2 of corresponding one of the operational amplifiers OP; and the output terminal T3 of the corresponding one of the operational amplifier OP. In the example embodiment illustrated in
Thereafter, the switches SW corresponding the respective column lines B may be caused to be in the nonconducting state (step S104). This may end the charging of the parasitic capacitances PC of the respective column lines B that has been performed by causing the switches SW corresponding to the respective column lines B to be in the conducting state. In the example embodiment illustrated in
Thereafter, output voltages corresponding to the respective selected resistors RS may be measured (step S105). For example, an output voltage may be measured that results from each selected resistor RS coupled to both the selected row line AS and one of the column lines B and that is outputted from the output terminal T3 of one of the operational amplifiers OP corresponding to the one of the column lines B. In the example embodiment illustrated in
Vout [V]={(V2 [V]−V1 [V])/(cs[F]×rs[Ω])}×T[sec.]+V2 [V] (1)
where:
The measurement operation in the element array circuit 1 may thus be completed. When measuring the output voltage Vout corresponding to any of the resistors R other than the resistors R(1, 1) to R(1, n), steps S101 to S105 described above may be repeated. However, for the column line B to which the resistor R having undergone the measurement is coupled, the operation of charging the parasitic capacitance thereof again may be omitted. Further, in some embodiments, the order of steps S102 and S103 may be reversed, or step S102 may be performed between step S104 and step S105.
As described above, the element array circuit 1 according to the present example embodiment includes the one or more row lines A, the plurality of column lines B, the plurality of resistors R, the one or more operational amplifiers OP, the one or more capacitors CP, and the one or more switches SW. The column lines B each extend in a direction different from the direction in which the one or more row lines A extend. The resistors R are each coupled to both one of the one or more row lines A and one of the column lines B. The one or more operational amplifiers OP each include the positive input terminal T1, the negative input terminal T2, and the output terminal T3. The negative input terminal T2 is couplable to one of the column lines B. The one or more capacitors CP are each coupled to the negative input terminal T2 and the output terminal T3 of corresponding one of the one or more operational amplifiers OP, and each convert a current flowing through the column line B coupled to the negative input terminal T2 into a voltage. The one or more switches SW are each coupled to one of the one or more capacitors CP in parallel between the negative input terminal T2 and the output terminal T3 of corresponding one of the one or more operational amplifiers OP, and are each configured to come into either the conducting state or the nonconducting state. In the element array circuit 1 of such a configuration, by causing one switch SW corresponding to each column line B into the conducting state and by establishing electrical continuity between: the column line B coupled to the negative input terminal T2 of corresponding one of the operational amplifier OP; and the output terminal T3 of the corresponding one of the operational amplifier OP, the parasitic capacitance parasitic to the column line B coupled to the negative input terminal T2 of the corresponding one of the operational amplifier OP is charged quickly. Upon switching the switch SW into the nonconducting state after the charging, it is possible to measure the output voltage Vout that results from relevant one of the selected resistors RS and is outputted from the output terminal T3 of the operational amplifier OP corresponding to the relevant one of the selected resistors RS.
In contrast, in the infrared detection circuit of JP-A No. H08-94443, for example, a low-pass filter is formed by a resistor (a resistor element Rtmn) and a parasitic capacitance parasitic to a wiring line coupled to the resistor and a negative input terminal of an operational amplifier. Due to an influence of such a low-pass filter, a potential at the negative input terminal of the operational amplifier to which the wiring line is coupled can take a long time to reach a steady state as a result of charging of the parasitic capacitance, and accordingly, an output voltage value resulting from the resistor can take a long time to reach a steady state. To measure the resistance value of the resistor with accuracy, it would thus be necessary to wait for the long time until the output voltage value reaches the steady state. An output voltage value before reaching the steady state could be measured, but with low accuracy.
In this regard, the element array circuit 1 according to the present example embodiment is provided with the switches SW, which allows for quick charging of the parasitic capacitances parasitic to the respective column lines B. This helps to bring the output voltages Vout resulting from the selected resistors RS coupled to the respective column lines B into a steady state quickly, thus allowing for quick and accurate measurement of the output voltages Vout related to the resistance values of the respective selected resistors RS.
Moreover, the element array circuit 1 according to the present example embodiment may be provided with a plurality of operational amplifiers OP, the operational amplifiers OP corresponding to the respective column lines B. This helps to measure the output voltages Vout quickly as compared with, for example, when any of the column lines B is selectively coupled to a single operational amplifier OP to measure the output voltage Vout.
The resistors RE may correspond to a specific but non-limiting example of “one or more conversion elements” in one embodiment of the disclosure, and may each correspond to a specific but non-limiting example of a “first resistor” in one embodiment of the disclosure. The resistors RE may each include a resistor element including, for example, a metal material having a predetermined specific resistance. The resistors RE are each coupled to both the negative input terminal T2 and the output terminal T3 of corresponding one of the operational amplifiers OP, and each convert a current flowing through the column line B coupled to the negative input terminal T2 into a voltage. For example, in the example embodiment illustrated in
In the element array circuit 2, it is possible to perform measurement on each of the resistors R in the following manner, for example. The following measurement operation may be performed in accordance with a command from the processor CTRL.
The measurement operation in the element array circuit 2 may be basically the same as the measurement operation in the element array circuit 1. See
Thereafter, the switches SW corresponding the respective column lines B may be caused to be in the nonconducting state (step S104). This may end the charging of the parasitic capacitances PC of the respective column lines B that has been performed by causing the switches SW corresponding to the respective column lines B to be in the conducting state. In the example embodiment illustrated in
Vout [V]=(re [Ω]/rs[Ω])×(V2 [V]−V1 [V])+V2 [V] (2)
where:
Because the resistance value re [Ω] of the resistor RE1 is known, the output voltage Vout may be dependent on the resistance value rs [Ω] of the selected resistor RS, as indicated in Expression (2) above. Accordingly, the resistance value rs of each of the selected resistors RS is calculable from the output voltage Vout, based on Expression (2) above.
The element array circuit 2 according to the second example embodiment is expected to provide effects similar to those of the element array circuit 1 according to the foregoing first example embodiment. For example, the element array circuit 2 according to the second example embodiment is provided with the switches SW, which allows for quick charging of the parasitic capacitances parasitic to the respective column lines B. This helps to bring the output voltages Vout resulting from the selected resistors RS coupled to the respective column lines B into a steady state quickly, thus allowing for quick and accurate measurement of the output voltages Vout related to the resistance values of the respective selected resistors RS.
Moreover, the element array circuit 2 according to the second example embodiment may be provided with a plurality of operational amplifiers OP, the operational amplifiers OP corresponding to the respective column lines B. This helps to measure the output voltages Vout quickly as compared with, for example, when any of the column lines B is selectively coupled to a single operational amplifier OP to measure the output voltage Vout.
The column line selector SB may include switches SWB1 (SWB1-1 to SWB1-n) and switches SWB2 (SWB2-1 to SWB2-n). The switches SWB1 (SWB1-1 to SWB1-n) and the switches SWB2 (SWB2-1 to SWB2-n) may each be switchable between the conducting state and the nonconducting state. The switches SWB1 (SWB1-1 to SWB1-n) may each be provided between corresponding one of the column lines B (B1 to Bn) and the negative input terminal T2 of the operational amplifier OP. The switches SWB2 (SWB2-1 to SWB2-n) may each be provided between corresponding one of the column lines B (B1 to Bn) and the direct-current power supply PS2.
The column line selector SB may select one column line B, which will be referred to as a selected column line BS for convenience, from among the plurality of column lines B, and may couple the selected column line BS to the negative input terminal T2 of the operational amplifier OP. The column line selector SB may further couple the column lines B other than the selected column line BS, which will be referred to as unselected column lines BU for convenience, to the direct-current power supply PS2 via the switches SWB2 (SWB2-1 to SWB2-n). Operation of the column line selector SB may be controlled by the processor CTRL. For example, a switching operation of the column line selector SB on each of the switches SWB1 (SWB1-1 to SWB1-n) and each of the switches SWB2 (SWB2-1 to SWB2-n) may be executed based on a command from the processor CTRL.
In the element array circuit 3, it is possible to perform measurement on each of the resistors R in the following manner, for example. The following measurement operation may be performed in accordance with a command from the processor CTRL.
Thereafter, one row line corresponding to the selected resistor RS targeted for the measurement may be selected to be the selected row line AS (step S302). This step S302 may be performed in a manner similar to that for step S102 of
Thereafter, one column line corresponding to the selected resistor RS targeted for the measurement may be selected to be the selected column line BS (step S303). For example, the switch SWB1 coupled to the selected column line BS to which the selected resistor RS is coupled may be caused to be in the conducting state to thereby couple the selected column line BS to the operational amplifier OP. The other switches SWB1 corresponding to the unselected column lines BU may be kept in the nonconducting state. Further, the switches SWB2 of the unselected column lines BU may be caused to be in the conducting state to thereby cause the second voltage V2 to be applied to the unselected column lines BU. The switch SWB2 corresponding to the selected column line BS may be kept in the nonconducting state.
Thereafter, the switch SW may be caused to be in the conducting state (step S304) to allow for charging of the parasitic capacitance parasitic to the selected column line BS corresponding to the selected resistor RS targeted for the measurement. For example, while causing the switch SWB1-1 corresponding to the column line B1 as the selected column line BS to be in the conducting state, the switch SW may be caused to be in the conducting state to thereby establish electrical continuity between the column line B1 and the output terminal T3 of the operational amplifier OP.
Thereafter, the switch SW may be caused to be in the nonconducting state (step S305). This may end the charging of the parasitic capacitance PC of the selected column line BS that has been performed by causing the switch SW to be in the conducting state. At this time, the difference voltage between the first voltage V1 and the second voltage V2, i.e., V2−V1, may be applied to the resistor R(1, 1), and a current dependent on the resistance value of the resistor R(1, 1) may flow through the resistor R(1, 1) and through the column line B1 as the selected column line BS toward the capacitor CP. In contrast, the second voltage V2 may be applied to the row lines A2 to Am other than the row line A1 as the selected row line AS, and to the column line B1. Accordingly, the voltage to be applied to the resistors R other than the resistor R(1, 1) as the selected resistor RS, among the resistors R(1, 1) to R(1, m) coupled to the column line B1 as the selected column line BS, may be zero, resulting in no current flowing through the resistors R(1, 2) to R(1, m). Further, because the resistors R coupled to the column lines B2 to Bn as the unselected column lines BU are not coupled to the capacitor CP, those resistors R will not affect the capacitor CP.
Thereafter, the output voltage corresponding to the selected resistor RS may be measured (step S306). This step S306 may be performed in a manner similar to that for step S105 of
The measurement operation in the element array circuit 3 may thus be completed. When measuring the output voltage Vout corresponding to any of the resistors R other than the resistor R(1, 1), steps S301 to S306 described above may be repeated. However, for the column line B to which the resistor R having undergone the measurement is coupled, the operation of charging the parasitic capacitance thereof again may be omitted. In the example embodiment illustrated in
The element array circuit 3 according to the third example embodiment is expected to provide effects similar to those of the element array circuit 1 according to the foregoing first example embodiment. For example, the element array circuit 3 according to the third example embodiment is provided with the switch SW, which allows for quick charging of the parasitic capacitance parasitic to the selected column line BS. This helps to bring the output voltage Vout resulting from the selected resistor RS coupled to the selected column line BS into a steady state quickly, thus allowing for quick and accurate measurement of the output voltage Vout related to the resistance value of the selected resistor RS.
Moreover, in the element array circuit 3 according to the third example embodiment, any of the column lines B is selectively couplable to the single operational amplifier OP through the use of the column line selector SB. This helps to achieve further downsizing of the circuit as compared with the element array circuit 1 of the foregoing first example embodiment that includes the plurality of operational amplifiers OP.
The measurement operation of the element array circuit 4 according to the present example embodiment may also be performed in accordance with the procedure described with reference to
The element array circuit 4 according to the fourth example embodiment is expected to provide effects similar to those of the element array circuit 3 according to the foregoing third example embodiment. For example, the element array circuit 4 according to the fourth example embodiment is provided with the switch SW, which allows for quick charging of the parasitic capacitance parasitic to the selected column line BS. This helps to bring the output voltage Vout resulting from the selected resistor RS coupled to the selected column line BS into the steady state quickly, thus allowing for quick and accurate measurement of the output voltage Vout related to the resistance value of the selected resistor RS.
Moreover, in the element array circuit 4 according to the fourth example embodiment, any of the column lines B is selectively couplable to the single operational amplifier OP through the use of the column line selector SB. This helps to achieve further downsizing of the circuit as compared with the element array circuit 2 of the foregoing second example embodiment that includes the plurality of operational amplifiers OP.
The detector 10 may include at least one of the element array circuit 1, 2, 3, or 4 described in the first, second, third, or fourth example embodiment above. Examples of the detector 10 may include an infrared detector that receives infrared rays and outputs a voltage that changes with the intensity of the received infrared rays. Alternatively, the detector 10 may receive an electromagnetic wave other than infrared rays, such as a terahertz wave, and may output a voltage that changes with the intensity of the received electromagnetic wave.
The arithmetic processor 20 may receive an output voltage from the detector 10 and perform arithmetic processing thereon, such as converting the output voltage into data of a desired parameter. The storage 30 may hold the data generated at the arithmetic processor 20. The outputter 40 may output the data generated at the arithmetic processor 20 to an external apparatus as an electric signal.
The sensor device 101 according to the present example embodiment may be provided with the detector 10 including at least one of the element array circuit 1, 2, 3, or 4. This allows for quick and accurate measurement of the intensity of the received electromagnetic wave.
Note that the description is given above of an example case in which the resistors R in the detector 10 may each be a light receiving element that converts an electromagnetic wave such as infrared rays into an electric signal; however, the sensor device 101 according to the present example embodiment is not limited to such a kind of device.
For example, as the resistor R of the element array circuit 1, 2, 3, or 4 in the detector 10, a temperature-sensitive resistor element including, for example, a thermistor material or a temperature-sensitive electrically-conductive ink material may be employed. Such a temperature-sensitive resistor element may change in electrical resistance value with changing temperature. In such a case, the sensor device 101 may serve as a temperature sensor configured to detect a temperature distribution in a plane.
Alternatively, as the resistor R of the element array circuit 1, 2, 3, or 4 in the detector 10, a pressure-sensitive element including, for example, a pressure-sensitive electrically-conductive ink material may be employed. Such a pressure-sensitive element may change in electrical resistance value with changing magnitude of an applied pressure. The sensor device 101 with the detector 10 including the pressure-sensitive elements as the resistors R may serve as a pressure sensor configured to detect a pressure distribution in a plane.
Alternatively, as the resistor R of the element array circuit 1, 2, 3, or 4 in the detector 10, a strain gauge may be employed. The strain gauge may change in electrical resistance value with changing magnitude of an applied stress. The sensor device 101 with the detector 10 including the strain gauges as the resistors R may serve as a strain sensor configured to detect a stress distribution in a plane.
Although some example embodiments of the disclosure have been described hereinabove, the disclosure is not limited to such example embodiments, and may be modified in a variety of ways.
For example, although respective illustrations of the element array circuits 1 to 4 of the foregoing first to fourth example embodiments in the drawings each exemplify a case in which the row lines extend in parallel to each other, embodiments of the disclosure are not limited thereto. In some embodiments, the row lines may be non-parallel to each other. Further, each of the row lines does not have to extend linearly, and may extend in a curved shape as a whole, or may be shaped to include a curved portion or a bent portion. Similarly, although the respective illustrations of the element array circuits 1 to 4 of the first to fourth example embodiments in the drawings each exemplify a case in which the column lines extend in parallel to each other, embodiments of the disclosure are not limited thereto. In some embodiments, the column lines may be non-parallel to each other. Further, embodiments of the disclosure are not limited to a case in which the row lines and the column lines extend in directions orthogonal to each other. Moreover, each of the column lines does not have to extend linearly, and may extend in a curved shape as a whole, or may be shaped to include a curved portion or a bent portion.
The element array circuits 1 to 4 of the foregoing first to fourth example embodiments may each include a plurality of row lines and a plurality of column lines; however, embodiments of the disclosure are not limited thereto. For example, an element array circuit 3A illustrated in
The element array circuits 1 to 4 of the foregoing first to fourth example embodiments may each include the plurality of resistors R as a plurality of impedance elements; however, embodiments of the disclosure are not limited thereto. For example, an element array circuit 1B illustrated in
Further, although the element array circuits 1 to 4 of the foregoing first to fourth example embodiments may each include the one or more capacitors CP or the one or more resistors RE as one or more conversion elements, embodiments of the disclosure are not limited thereto. In some embodiments, one or more semiconductor elements may be employed, for example. As in an element array circuit 1C illustrated in
It is possible to achieve at least the following configurations from the foregoing example embodiments and modification examples of the disclosure.
An element array circuit including:
The element array circuit according to (1), further including a processor configured to execute a control of: performing charging of a parasitic capacitance parasitic to one of the second wiring lines that is coupled to the negative input terminal of corresponding one of the one or more operational amplifiers; and switching, after performing the charging, one of the one or more switchers that corresponds to the negative input terminal into the nonconducting state, in which
The element array circuit according to (2), in which the processor is configured to, after performing the charging of the parasitic capacitance, switch the one of the one or more switchers that corresponds to the negative input terminal into the nonconducting state, and to measure, after switching the one of the one or more switchers, an output voltage outputted from the output terminal, the output voltage resulting from one of the impedance elements that is coupled to both relevant one of the one or more first wiring lines and the one of the second wiring lines that is coupled to the negative input terminal.
The element array circuit according to (1), further including a second wiring line selector configured to select one of the second wiring lines and to couple the one of the second wiring lines selected to the negative input terminal.
The element array circuit according to (4), further including a processor configured to execute a control of: performing charging of a parasitic capacitance parasitic to one of the second wiring lines that is coupled to the negative input terminal of corresponding one of the one or more operational amplifiers; and switching, after performing the charging, one of the one or more switchers that corresponds to the negative input terminal into the nonconducting state, in which
The element array circuit according to (1), in which
The element array circuit according to (6), further including a processor configured to execute a control of: performing charging of a parasitic capacitance parasitic to one of the second wiring lines that is coupled to the negative input terminal of corresponding one of the operational amplifiers; and switching, after performing the charging, one of the switchers that corresponds to the negative input terminal into the nonconducting state, in which
The element array circuit according to (1), in which
An element array circuit including:
The element array circuit according to (9), further including a processor configured to execute a control of: performing charging of a parasitic capacitance parasitic to one of the one or more second wiring lines that is coupled to the negative input terminal of corresponding one of the one or more operational amplifiers; and switching, after performing the charging, one of the one or more switchers that corresponds to the negative input terminal into the nonconducting state, in which
The element array circuit according to (10), in which the processor is configured to, after performing the charging of the parasitic capacitance, switch the one of the one or more switchers that corresponds to the negative input terminal into the nonconducting state, and to measure, after switching the one of the one or more switchers, an output voltage outputted from the output terminal, the output voltage resulting from one of the impedance elements that is coupled to both relevant one of the first wiring lines and the one of the one or more second wiring lines that is coupled to the negative input terminal.
The element array circuit according to (10), in which a period of time over which the charging of the parasitic capacitance is to be performed by causing the one of the one or more switchers that corresponds to the negative input terminal to be in the conducting state is longer than five times a product of a capacitance value of the parasitic capacitance and a resistance value of the one of the one or more switchers that corresponds to the negative input terminal.
The element array circuit according to (2) or (10), in which
The element array circuit according to (1) or (9), in which each of the one or more conversion elements includes a capacitor, a first resistor, or a first semiconductor element.
The element array circuit according to (1) or (9), in which each of the impedance elements includes a second resistor or a second semiconductor element.
An element array circuit including:
An electromagnetic wave sensor including the element array circuit according to any one of (1), (9), and (16).
A temperature sensor including the element array circuit according to any one of (1), (9), and (16).
A strain sensor including the element array circuit according to any one of (1), (9), and (16).
In the element array circuit according to at least one embodiment of the disclosure, charging of the parasitic capacitance parasitic to the second wiring line coupled to the negative input terminal of the operational amplifier is performed quickly by causing the switcher into the conducting state to thereby establish electrical continuity between: the second wiring line coupled to the negative input terminal; and the output terminal of the operational amplifier. It is possible to measure the output voltage resulting from the impedance element and outputted from the output terminal, upon switching the switcher into the nonconducting state after the charging.
The element array circuit, the electromagnetic wave sensor, the temperature sensor, and the strain sensor according to at least one embodiment of the disclosure each provide a measured value quickly with high accuracy.
The effects described herein are mere examples and non-limiting, and other effects may be achieved.
Although the disclosure has been described hereinabove in terms of the example embodiment and modification examples, the disclosure is not limited thereto. It should be appreciated that variations may be made in the described example embodiment and modification examples by those skilled in the art without departing from the scope of the disclosure as defined by the following claims. The limitations in the claims are to be interpreted broadly based on the language employed in the claims and not limited to examples described in this specification or during the prosecution of the application, and the examples are to be construed as non-exclusive. The use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another. The term “substantially” and its variants are defined as being largely but not necessarily wholly what is specified as understood by one of ordinary skill in the art. The term “disposed on/provided on/formed on” and its variants as used herein refer to elements disposed directly in contact with each other or indirectly by having intervening structures therebetween. Moreover, no element or component in this disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
Number | Date | Country | Kind |
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2022-121176 | Jul 2022 | JP | national |