Element for solid-state imaging device

Abstract

In an element for a MOS type solid-state imaging device, a leakage current caused by a stress generated in a vicinity of an element isolation region having an STI structure is reduced. The element for the MOS type solid-state imaging device comprises: a signal accumulation region 102, of a second conductivity type, provided in an interior of a semiconductor substrate or well 101 of a first conductivity type, for accumulating a signal charge generated by performing photoelectric convention; agate electrode 104 provided on the semiconductor substrate or well 101; a drain region 105, of a second conductivity type, provided on a surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed; and an element isolation region 201 provided on the surface portion, of the semiconductor substrate or well 101, on which the gate electrode is formed. The element isolation region 201 has the STI structure, and a cavity 202 is formed in an interior of the element isolation region 201.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating an embodiment of an element for a solid-state imaging device according to the present invention;

FIG. 2 is a cross-sectional view of the element for the solid-state imaging device along lines Y1-Y2 of FIG. 1;

FIG. 3 is a cross-sectional view of the element for the solid-state imaging device along lines X1-X2 of FIG. 1;

FIG. 4 is a plan view illustrating an element for a solid-state imaging device according to a conventional art;

FIG. 5 is a cross-sectional view of the element for the solid-state imaging device along lines Y1-Y2 of FIG. 4;

FIG. 6 is a cross-sectional view illustrating a vicinity of an element isolation region of the solid-state imaging device according to the conventional art;

FIG. 7 is a schematic cross-sectional view showing a method for fabricating the element for the solid-state imaging device according to the conventional art, particularly, illustrating a step for performing an ion implantation in order to form a defect suppression layer;

FIG. 8 is a schematic cross-sectional view showing the method for fabricating the element for the solid-state imaging device according to the conventional art, particularly, illustrating a case where the ion implantation for forming the defect suppression layer is difficult to perform; and

FIG. 9 is a cross-sectional view of the element for the solid-state imaging device according to the conventional art along lines X1-X2 of FIG. 4.

Claims

1. An element for a solid-state imaging device comprising: a signal accumulation region, of a second conductivity type, provided in an interior of a semiconductor substrate of a first conductivity type or in an interior of a well of the first conductivity type, for accumulating a signal charge-generated by performing photoelectric conversion;a gate electrode provided on the semiconductor substrate or the well;a drain region, of the second conductivity type, provided on a surface portion of the semiconductor substrate or a surface portion of the well; andan element isolation region formed on the surface portion of the semiconductor substrate or the surface portion of the well, whereinthe element isolation region has an STI (Shallow Trench Isolation) structure, and a cavity is formed in an interior of the element isolation region.

2. The element for the solid-state imaging device according to claim 1, wherein a width of the element isolation region is smaller than a depth of the element isolation region.

3. The element for the solid-state imaging device according to claim 1, wherein a surface shield layer is formed on the surface portion of the semiconductor substrate or the surface portion of the well, such that at least a portion of the surface shield layer is faced to the signal accumulation region, with the semiconductor substrate or the well which is situated between the surface shield layer and the signal accumulation region, andthe surface shield layer is an impurity region, of the first conductivity type, having an impurity concentration higher than that of the semiconductor substrate or the well, and the gate electrode is located, such that at least a portion of the gate electrode is faced to the signal accumulation region, with the semiconductor substrate or the well which is situated between the gate electrode and the signal accumulation region.