Patent Application
20230198058
This disclosure relates generally to integrated circuit packaging and, more particularly, to embedded batteries within glass cores of package substrates.
Integrated circuit (IC) chips and/or semiconductor dies are routinely connected to larger circuit boards such as motherboards and other types of printed circuit boards (PCBs) via a package substrate. As IC chips and/or dies reduce in size and interconnect densities increase, alternatives to traditional substrate layers are needed for providing stable transmission of high frequency data signals between different circuitry and/or increased power delivery.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of a semiconductor device, “above” is not with reference to Earth, but instead is with reference to a bulk region of a base semiconductor substrate (e.g., a semiconductor wafer) on which components of an integrated circuit are formed. Specifically, as used herein, a first component of an integrated circuit is “above” a second component when the first component is farther away from the bulk region of the semiconductor substrate than the second component.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.
Highly integrated microelectronic systems are needed to satisfy the continuous increase in data demand as well as the overall user experience. This has not only led to new integration strategies involving die disaggregation and re-stitching of technologies (e.g. semiconductor dies) from different nodes and processes, but also to an increase in the number of dies that are to be co-integrated in close proximity of each other on the same package substrate. Assembling multiple dies using 3D-IC technologies such as Foveros and hybrid bonding leads to smaller footprints. However, such IC packages come with thermal management challenges that only grow exponentially as the number of dies or active device layers in the 3D-IC stack-up increases. As more dies are included in a package, the thermal challenges can be at least partially alleviated by spreading out the dies across a large package substrate. In today's high speed systems, latency, bandwidth density, and power efficiency determine the relative locations of high-speed dies associated with computing and storage. For example, high-speed dies are typically on the same side of the package substrate as memory dies because going through an organic package core is detrimental to at least one of bandwidth density or power efficiency. However, placing separate dies on the same side of the package substrate has the inherent drawback of contributing to an increase in the package size and low yield from substrate manufacturing and potential assembly.
One option that is being considered to address present challenges is the implementation of glass cores in package substrates instead of the copper clad laminate (CCL) cores typically used in many existing IC packages manufactured today. By using laser-assisted etching, crack free, high-density via drills (e.g., hollow shapes, openings, channels, etc.) can be formed into a glass substrate that may then serve as the core for a package substrate. Different process parameters can be adjusted to achieve drills of various shapes and depths, thereby opening the door for innovative devices, architectures, processes and designs in glass.
Furthermore, drills or openings produced in a glass core can be filled with materials other than metals to achieve other purposes beyond simple metal interconnects that route signals through a package substrate. More particularly, examples disclosed herein include core-embedded thin film batteries to power small discrete units or devices (e.g., a light emitting diode (LED)), integrated passive devices, and/or other integrated components (e.g., semiconductor dies). In some examples, solid state electrolyte (e.g., lithium-based batteries are implemented to provide high operating voltage, high specific capacity, and long cycle life. The synthesis of lithium-based batteries typically requires substrates that can withstand high temperature processing, which has limited the incorporation of such batteries into organic packaging or thin films. However, by implementing batteries in glass core substrates, as disclosed herein, these concerns are overcome because glass can handle high temperature processing. Furthermore, implementing embedded batteries within glass cores can provide performance improvements due to the properties of glass as compared with the properties of traditional organic substrates.
The plurality of layers 104, 106, 108, 110, 112 of the battery 103 correspond to an anode current collector 104, an anode layer 106, an electrolyte 108, a cathode layer 110, and a cathode current collector 112. The anode current collector 104 and the cathode current collector 112 are positioned on opposite ends of the stack of layers with the anode layer 106 adjacent the anode current collector 104, the cathode layer 110 adjacent the cathode current collector 112, and the electrolyte 108 between the anode layer 106 and cathode layer 110. In the illustrated examples of
In this example, the battery 103 is a lithium-based battery. Accordingly, in this example, the anode layer 106 is composed of lithium (Li) lithium oxide (Li2O), and/or graphite or carbon (C) based materials. Further, the cathode layer 110 is composed of any suitable material capable of transporting positive lithium (Li+) ions (e.g., lithium cobalt oxide (LiCoO2 (LCO)), lithium manganese oxide (LiMn2O3), etc.).
The electrolyte 108 (also referred to herein as a separator) electrically isolates (e.g., separates, positioned between) the anode layer 106 from the cathode layer 110. Further, the electrolyte 108 is composed of a material that enables lithium ions to flow or be transported (e.g., ion diffusion) between the anode layer 106 and the cathode layer 110. More particularly, in some examples, the electrolyte 108 is composed of a solid state electrolyte such as lithium phosphorous oxynitride (LiPON). In the illustrated example of
In the example IC package 100 of
As shown in the illustrated example, the battery 103 is electrically isolated or separated from the electrical device 120 by a dielectric 122. In some examples, the dielectric 122 enclosed or covers portions of the battery 103 that are not otherwise directly enclosed by the glass core 102. In some examples, the dielectric 122 is composed of multiple layers of organic laminate dielectric (e.g., laminated epoxy layers), also known as layers of build-up film. The electrical device 120 is electrically coupled to both the anode current collector 104 and the cathode current collector 112 through corresponding conductive vias 124, 126 that extend through the dielectric 122 towards the electrical device 120. In some examples, the electrical device 120 is positioned to be in alignment with the battery 103 in a direction normal to the first surface 114 of the glass substrate such that the conductive vias 124, 126 may extend directly towards the device 120. herein some examples, the electrical device 120 can be electrically connected to the vias 124, 126 through the use of via pads and/or micro solder balls. In some examples, as shown in
The batteries 802 are electrically coupled to the device 120 through conductive traces or routing 128. In particular, in this example, the separate batteries 802 are arranged in parallel with the anode current collector 104 of each battery 802 electrically coupled to one another and electrically coupled to the electrical device 120 by traces 128 extending therebetween along the first surface 114 of the glass core 102. As shown in
Further, as shown in the illustrated example, the cathode current collectors 112 of the separate batteries 802 are electrically coupled to one another and electrically coupled to the electrical device 120 by traces 128 extending therebetween along the second surface 118 of the glass core 102. In this example, where cathode current collectors 112 extend along the longitudinal axis 804 of the batteries 802 and are surrounded by the anode current collector 104, the traces 128 connected to the cathode current collectors 112 necessarily need to cross over the paths of the anode current collectors 104 to connect to adjacent components beyond the outer circumference of the anode current collectors 104. Accordingly, to maintain electrical isolation between the anode current collector 104 and the cathode current collector 112, the traces 128 extend along the second surface 118 are not directly adjacent the surface 118 but separated therefrom by a dielectric 122. In the example IC package 800, the second surface 118 faces away from the electrical device 120. Accordingly, to enable the cathode current collectors 112 of the batteries 802 to be electrically coupled with the electrical device 120 through the traces 128, a separate through-glass via or plane (TGV, TGP) 806 extends through the glass core 102 with a first end electrically coupled to the traces 128 on the second surface 118 of the glass core 102 and a second end electrically coupled to the electrical device 120.
Turning to
Turning to
The example process of
The stage of fabrication following completion of block 1104 of
The stage of fabrication following completion of block 1106 of
The stage of fabrication following completion of block 1108 of
The stage of fabrication following completion of block 1110 of
The stage of fabrication following completion of block 1112 of
As noted above,
The stage of fabrication following completion of block 1202 of
The stage of fabrication following completion of both blocks 1206 and 1208 of
The stage of fabrication following completion of block 1210 of
The stage of fabrication following completion of block 1212 of
The stage of fabrication following completion of block 1214 of
The stage of fabrication following completion of block 1216 of
Although the example method of implementing block 1106 of
Additionally or alternatively, in some examples, the series of materials 1606, 1802, 1902, 2002, 2102 can be deposited in an order different from the process described in
The example IC packages 100, 400, 500, 600, 800 disclosed herein may be included in any suitable electronic component.
The IC device 2600 may include one or more device layers 2603 disposed on the substrate 2602. The device layer 2604 may include features of one or more transistors 2640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2602. The device layer 2604 may include, for example, one or more source and/or drain (S/D) regions 2620, a gate 2622 to control current flow in the transistors 2640 between the S/D regions 2620, and one or more S/D contacts 2624 to route electrical signals to/from the S/D regions 2620. The transistors 2640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 2640 are not limited to the type and configuration depicted in
Each transistor 2640 may include a gate 2622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 2640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate 2602 and two sidewall portions that are substantially perpendicular to the top surface of the substrate 2602. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate 2602 and does not include sidewall portions substantially perpendicular to the top surface of the substrate 2602. In other examples, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 2620 may be formed within the substrate 2602 adjacent to the gate 2622 of each transistor 2640. The S/D regions 2620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 2602 to form the S/D regions 2620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 2602 may follow the ion-implantation process. In the latter process, the substrate 2602 may first be etched to form recesses at the locations of the S/D regions 2620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 2620. In some implementations, the S/D regions 2620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 2620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 2620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 2640) of the device layer 2604 through one or more interconnect layers disposed on the device layer 2604 (illustrated in
The interconnect structures 2628 may be arranged within the interconnect layers 2606-2610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 2628 depicted in
In some examples, the interconnect structures 2628 may include lines 2628a and/or vias 2628b filled with an electrically conductive material such as a metal. The lines 2628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 2602 upon which the device layer 2604 is formed. For example, the lines 2628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 2606-2610 may include a dielectric material 2626 disposed between the interconnect structures 2628, as shown in
A first interconnect layer 2606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 2604. In some examples, the first interconnect layer 2606 may include lines 2628a and/or vias 2628b, as shown. The lines 2628a of the first interconnect layer 2606 may be coupled with contacts (e.g., the S/D contacts 2624) of the device layer 2604.
A second interconnect layer 2608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 2606. In some examples, the second interconnect layer 2608 may include vias 2628b to couple the lines 2628a of the second interconnect layer 2608 with the lines 2628a of the first interconnect layer 2606. Although the lines 2628a and the vias 2628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 2608) for the sake of clarity, the lines 2628a and the vias 2628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 2610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 2608 according to similar techniques and configurations described in connection with the second interconnect layer 2608 or the first interconnect layer 2606. In some examples, the interconnect layers that are “higher up” in the metallization stack 2619 in the IC device 2600 (i.e., further away from the device layer 2604) may be thicker.
The IC device 2600 may include a solder resist material 2634 (e.g., polyimide or similar material) and one or more conductive contacts 2636 formed on the interconnect layers 2606-2610. In
The IC package 2700 may include a die 2706 coupled to the package substrate 2702 via conductive contacts 2704 of the die 2706, first-level interconnects 2708, and conductive contacts 2710 of the package substrate 2702. The conductive contacts 2710 may be coupled to conductive pathways 2712 through the package substrate 2702, allowing circuitry within the die 2706 to electrically couple to various ones of the conductive contacts 2714 (or to other devices included in the package substrate 2702, not shown). The first-level interconnects 2708 illustrated in
In some examples, an underfill material 2716 may be disposed between the die 2706 and the package substrate 2702 around the first-level interconnects 2708, and a mold compound 2718 may be disposed around the die 2706 and in contact with the package substrate 2702. In some examples, the underfill material 2716 may be the same as the mold compound 2718. Example materials that may be used for the underfill material 2716 and the mold compound 2718 are epoxy mold materials, as suitable. Second-level interconnects 2720 may be coupled to the conductive contacts 2714. The second-level interconnects 2720 illustrated in
In
Although the IC package 2700 illustrated in
In some examples, the circuit board 2802 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2802. In other examples, the circuit board 2802 may be a non-PCB substrate.
The IC device assembly 2800 illustrated in
The package-on-interposer structure 2836 may include an IC package 2820 coupled to an interposer 2804 by coupling components 2818. The coupling components 2818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2816. Although a single IC package 2820 is shown in
In some examples, the interposer 2804 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 2804 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 2804 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2804 may include metal interconnects 2808 and vias 2810, including but not limited to through-silicon vias (TSVs) 2806. The interposer 2804 may further include embedded devices 2814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2804. The package-on-interposer structure 2836 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2800 may include an IC package 2824 coupled to the first face 2840 of the circuit board 2802 by coupling components 2822. The coupling components 2822 may take the form of any of the examples discussed above with reference to the coupling components 2816, and the IC package 2824 may take the form of any of the examples discussed above with reference to the IC package 2820.
The IC device assembly 2800 illustrated in
Additionally, in various examples, the electrical device 2900 may not include one or more of the components illustrated in
The electrical device 2900 may include a processing device 2902 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2902 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 2900 may include a memory 2904, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 2904 may include memory that shares a die with the processing device 2902. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 2900 may include a communication chip 2912 (e.g., one or more communication chips). For example, the communication chip 2912 may be configured for managing wireless communications for the transfer of data to and from the electrical device 2900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 2912 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2912 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2912 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2912 may operate in accordance with other wireless protocols in other examples. The electrical device 2900 may include an antenna 2922 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 2912 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2912 may include multiple communication chips. For instance, a first communication chip 2912 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2912 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 2912 may be dedicated to wireless communications, and a second communication chip 2912 may be dedicated to wired communications.
The electrical device 2900 may include battery/power circuitry 2914. The battery/power circuitry 2614 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 2900 to an energy source separate from the electrical device 2900 (e.g., AC line power).
The electrical device 2900 may include a display device 2906 (or corresponding interface circuitry, as discussed above). The display device 2906 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 2900 may include an audio output device 2908 (or corresponding interface circuitry, as discussed above). The audio output device 2908 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 2900 may include an audio input device 2924 (or corresponding interface circuitry, as discussed above). The audio input device 2924 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 2900 may include a GPS device 2918 (or corresponding interface circuitry, as discussed above). The GPS device 2918 may be in communication with a satellite-based system and may receive a location of the electrical device 2900, as known in the art.
The electrical device 2900 may include any other output device 2910 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2910 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 2900 may include any other input device 2920 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2920 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 2900 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 2900 may be any other electronic device that processes data.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements or method actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
Example 1 includes an apparatus comprising a glass core layer having opposing first and second surfaces, the glass core layer including a cavity extending from the first surface toward the second surface, and a battery including a first conductive material positioned in the cavity, a second conductive material positioned in the cavity, and an electrolyte to separate the first conductive material from the second conductive material.
Example 2 includes the apparatus of example 1, wherein the first conductive material corresponds to an anode current collector of the battery and the second conductive material corresponds to a cathode current collector of the battery, the battery further including an anode layer between the anode current collector and the electrolyte, and a cathode layer between the cathode current collector and the electrolyte.
Example 3 includes the apparatus of example 2, wherein the electrolyte is a solid state electrolyte that enables ion diffusion between the anode layer and the cathode layer.
Example 4 includes the apparatus of example 1, wherein the first conductive material is positioned on and extends across a surface of the cavity in the glass core layer.
Example 5 includes the apparatus of example 4, wherein the surface of the cavity corresponds to a wall of the cavity, the wall extending in a direction transverse to the first surface of the glass core layer, the second conductive material positioned within the cavity such that the first conductive material on the wall of the cavity surrounds the second conductive material.
Example 6 includes the apparatus of example 1, wherein the cavity is one of multiple cavities in the glass core layer, the multiple cavities distributed along the first surface of the glass core layer with different ones of the multiple cavities separated by portions of the glass core layer, the first conductive material positioned in different ones of the multiple cavities.
Example 7 includes the apparatus of example 6, wherein the first conductive material extends between the different ones of the multiple cavities over the first surface of the glass core layer.
Example 8 includes the apparatus of example 7, wherein the second conductive material is to cover the first conductive material in the different ones of the multiple cavities, the second conductive material to extend continuously in a straight line across the different ones of the multiple cavities.
Example 9 includes the apparatus of example 6, wherein the battery is a first battery, the apparatus further including a second battery, the first battery associated with a first one of the multiple cavities and the second battery associated with a second one of the multiple cavities.
Example 10 includes the apparatus of example 9, wherein the first battery is electrically coupled to the second battery in series.
Example 11 includes the apparatus of example 9, wherein the first battery is electrically coupled to the second battery in parallel.
Example 12 includes the apparatus of example 1, wherein the cavity extends through the glass core layer from the first surface to the second surface.
Example 13 includes the apparatus of example 12, wherein the cavity is defined by a circular via including a longitudinal axis extending from the first surface to the second surface, the first conductive material circumferentially surrounding the second conductive material along the longitudinal axis.
Example 14 includes an integrated circuit (IC) package comprising a substrate including a glass core, an electrical device supported by the substrate, and a battery embedded in the glass core, the battery electrically coupled to the electrical device.
Example 15 includes the battery of example 14, wherein the battery includes a series of layers of materials disposed within an opening in the glass core, the series of layers of materials including at least one of an anode current collector, an anode layer, an electrolyte layer, a cathode layer, or a cathode current collector.
Example 16 includes the battery of example 15, wherein the glass core includes a first surface and a second surface opposite the first surface, the series of layers of materials to overlap one another on the first surface of the glass core.
Example 17 includes the battery of example 14, wherein the glass core includes an opening extending into the glass core from a first surface of the glass core, the first surface facing toward the electrical device, the battery disposed within the opening.
Example 18 includes the battery of example 17, wherein the opening extends through the glass core from the first surface to a second surface of the glass core, the second surface facing away from the electrical device, the electrical device electrically coupled to a first one of an anode of the battery or a cathode of the battery at the first surface of the glass core, the electrical device electrically coupled, through a conductive via extending through the glass core, to a second one of the anode or the cathode at the second surface of the glass core.
Example 19 includes the battery of example 14, wherein the glass core includes multiple openings spaced apart along a first surface of the glass core, a first one of an anode or a cathode of the battery lining walls of different ones of the openings, the first one of the anode or the cathode to be electrically coupled across the different ones of the openings by extending across the first surface of the glass core.
Example 20 includes the battery of example 19, wherein a second one of the anode or the cathode is positioned within the multiple openings between portions of the first one of the anode or the cathode lining the walls of the different ones of the openings.
Example 21 includes a method for manufacturing an integrated circuit (IC) package with an embedded battery, the method comprising forming a cavity in a glass substrate, and depositing a series of materials in successive layers within the cavity, the series of materials arranged to define the battery, the series of materials including an anode layer material, an electrolyte, and a cathode layer material, the electrolyte positioned between the anode layer material and the cathode layer material.
Example 22 includes the method of example 21, wherein the cavity is a via that extends through the glass substrate.
Example 23 includes the method of example 21, further including depositing a dielectric laminate to enclose the series of materials.
Example 24 includes the method of example 21, wherein the forming of the cavity includes forming multiple cavities in the glass substrate, the depositing of the series of materials includes depositing the series of materials in different ones of the multiple cavities.
Example 25 includes the method of example 21, further including attaching a semiconductor device to the glass substrate, and electrically coupling the semiconductor device to the battery.
From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that enable integrated circuit packaged to embed batteries within glass substrates and/or cores. Embedding batteries within a package substrate based on thin film battery technology eliminates the need for large and/or bulky batteries or associated electrical connections to be added on the surface of the substrate, which can take up space on the surface of the substrate, thereby leading to the need for packages with larger footprints. Further, embedding batteries within a glass core of a package substrate mitigates against concerns associated with high temperature fabrication processes because of the improved material properties of glass relative to traditional organic cores.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.
