Patent Application
20100277201
Programmable logic devices, such as field programmable gate arrays (FPGA) are typically used as prototype platforms but have been commonly replaced by application specific integrated circuits (ASIC), mainly for reasons of cost and power as the product ramps into high volume. Vendors typically provide for a migration path for customers to prototype in FPGAs and then reduce cost and power by converting the design into a structured ASIC when the design has stabilized. Alternatively, hard macros representing large blocks of digital logic directly inside the FPGA, e.g., PCI-Express 2.0 standard blocks, are embedded into the programmable logic devices once the standard is mature.
In either event, as emerging protocols are being developed to facilitate new high bandwidth applications, there is a need to quickly prototype the functionality and release a viable product into the market. Time-to-market is crucial for product adoption. Cost and power is also a concern for developers to make their product feasible for mass production. Emerging protocols have not matured to the required level of stability and there is high risk of having to make additional significant changes after committing to a design when proceeding directly to standard cell implementation. Thus, both the migration path and embedding hard macros have shortcomings with respect to emerging protocols because of the tension between the need for certainty in order to migrate or provide hard macros and the requirement for flexibility as the emerging protocol is developed.
It is in this context that embodiments of the invention arise.
Embodiments of the present invention provide circuits and methods for an integrated circuit having a hybrid platform that accommodates the flexibility required by emerging protocols, yet minimizes area and power requirements for the accommodation of the emerging protocol. It should be appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, a device or a method on a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, an integrated circuit (IC) is provided. The IC includes a core region having an array of programmable logic cells. The IC also includes a digital strip incorporated into the IC and in communication with the core region. The digital strip includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known or mature protocols. The base cells are composed of configurable logic cells to adapt to modifications to emerging communication protocols, which are supported by the base cells. The digital strip can be embedded in the core region in one embodiment. In another embodiment, the digital strip is defined around a perimeter (or a portion of the perimeter) of the core region. The configurable logic cells may be composed of hybrid logic elements that have modifiable interconnections that may require metal layer changes to the routing structure. Thus, as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In one embodiment, the base layers of the digital IP strip are similar to a gate array and therefore are not touched during a metal layer re-spin. In this embodiment, the digital strip is layered upon gate array technology by adding a few metal layers to build logic cells that include multiple simple function cells. It should be appreciated that the simple functions cells can be configured through minimal metal layer programmability to build complex functions. Accordingly, the digital strip logic cells can potentially support multiple independent functions by stitching together simple function cells. In turn, protocol changes can be accommodated through routing changes programmed into the IC. It should be noted that the modifiable interconnections may be referred to as programmable interconnections, in that a specific set of cells are bypassed and the corresponding function of the bypassed cells is replaced by an implementation in the FPGA core region, or alternatively a secondary implementation in the structured ASIC cells. In one embodiment, the hybrid logic elements consume less area than the programmable logic elements of a field programmable gate array because of fixed routing between cells and hard wired functions of the cell function.
In another embodiment, a method for designing an integrated circuit (IC) is provided. The method includes performing a timing analysis on a generated design of the IC and identifying a critical timing path for the generated design. Programmable logic cells along the critical timing path are replaced in the design. The programmable logic cells from the core region of the IC are replaced with standard cells located within the digital strip, which is separate from the core region. The digital strip includes base cells that may be referred to as hybrid logic elements. Within the digital strip there may be heterogeneous regions consisting of a mixture of hybrid logic elements (base cells) and standard cells and homogeneous regions of just hybrid logic elements (base cells) or standard cells. The embodiments described herein endeavor to make the digital strip as homogeneous as possible for the hybrid logic elements to allow the most flexibility. In one embodiment, the hybrid logic element could be built upon a gate array where the digital strip cell may be stripped down to the base layers and replaced with smaller gate array cells. For example, the digital strip may have two programmable metal layers and the gate array may have four layers of metal for both routing and transistor configuration in the cell function. The design of the IC is re-generated with the standard cells disposed within a digital IP strip. The digital IP strip interfaces with the core region of the IC. In one embodiment, the re-generated design may be stored for production of an actual IC. In another embodiment, hybrid logic elements are substituted for the programmable logic elements of the previous design. The hybrid logic elements are located within a digital strip region that is defined separately from the core region. The hybrid logic elements consume less area and metallization layers for the IC, but are configurable to support modifications to any emerging communication protocols. In one embodiment, there could be potentially three iterations of the design where first a hybrid logic element (course iteration) is defined, followed by gate array cell (medium iteration), and then followed by a standard cell (fine iteration).
Other aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The invention may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
An integrated circuit having a digital strip region is provided. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
The embodiments described herein provide for an integrated circuit having a hybrid platform. In one embodiment, the integrated circuit has a programmable logic device (PLD) core region, such as a field programmable gate array (FPGA) core region, and a digital Intellectual Property (IP) strip or block, which may also be referred to as a structured application specific integrated circuit (ASIC) strip or array. The digital strip includes base cells whose digital functionality can be modified with a limited number of metal masks and standard cell macros that accommodate mature functions/protocols. In one embodiment, the digital strip resides between the analog block and the FPGA core region. In another embodiment, the digital strip is incorporated into or embedded within the core region to encapsulate timing critical circuits such as memory controllers. As will be explained in more detail below, the digital strip is built as a customizable platform to allow users to migrate proprietary logic functions from the core region into this region with low overhead costs. In one embodiment, the “metal-programmable” technology or digital strip is defined as an array of logic cells with routing options provided in the first one-to-five (1-5 LM) metal layers with metal six and above (6-11 LM) used for global signals including routing, clocks, resets, etc. Accordingly, the logic cells of the digital strip are not field configurable in the sense of the Field Programmable Gate Array, i.e., the logic cells of the digital strip are non-user configurable. However, the logic cells of the digital strip may be metal mask programmable by the owner of the chip, which will incur a non-recurring expense, as one skilled in the art will appreciate.
In the embodiments described below it should be appreciated that block functions are parameterized and have the option of being enabled or disabled in the data path. Transferring data between digital IP strip 104 and core region 108 may require bonding of two clock networks using a phase compensation first-in first-out (FIFO) buffer, and thus can be considered a common feature to be implemented in standard cell technology. In one embodiment, this implementation may be designed with standard cell technology or built using custom memories to reduce the area and power. Alternatively, a gate array base layer cell configured as a memory bit consuming 12 transistors may be utilized for this feature. In another embodiment, an HLE could be split into two memory bits instead of using a register cell that consumes two HLEs (48 transistors). With the decrease in transistor size, the area consumed by digital functions shrinks, causing regions of unused silicon or areas of only routing that can be utilized for the digital IP strip. As described further below, link-wide functions found in many emerging protocols can be considered candidates for implementation within the digital IP strip discussed herein. Multiple lanes are bonded together for high bandwidth applications requiring complex state machines to coordinate first the individual lane based functions and then link wide functions. Data path convergence points such as link wide cyclic redundancy checks (CRC), scramblers and barrel shifters stress both routing and look up table (LUT) resources of the core region as the computation ripples across the data path width. Accordingly, these link wide functions may be migrated to digital IP strip 104, by incorporating standard cells, base cells and/or HLE into the digital IP strip 104, thereby freeing up the programmable logic elements of the core region. One skilled in the art will appreciate that by reducing the datapath width and removing unnecessary pipeline stages reduces the latency for that function, which is beneficial for functions, such as memory controllers and high performance applications that require low round trip latency, e.g., PCI Express, HyperTransport (HT) and QuickPath Interconnect (QPI).
In digital IP strip 104 of integrated circuit 100, metal mask programmable cells 120 are provided. A number of standard cells 122 within digital IP strip 104 are provided in order to efficiently process data and handle tasks, while maintaining the flexibility through core region 108. For example, standard cells 122 may include the CRC and scrambler functionality referred to above. In addition, physical coding sublayer (PCS) channels 125 may be constructed from a clustered set of standard cells. In essence, digital IP strip 104 commingles standard cells with metal mask programmable cells. Thus, within digital IP strip 104 a heterogeneous mixture of cells reside, e.g., standard cells, hybrid logic elements, and base cells. Digital IP strip 104 supports known communication standards, and is configurable to adapt to emerging communication standards, e.g., communication standards not known or still being developed. Digital IP strip 104 also includes analog/digital interface 128 and FIFO register region 126, which may be referred to as a phase compensation region and functions as a bridge clock structure between core region 108 and digital IP strip 104. Analog/digital interface 128 enables communication between the analog and digital interface, e.g., between regions 102 and 104. Similarly FIFO region 126 enables communication between digital IP strip 104 and the analog components of I/O region 106. Within core region 108, adaptable look-up table modules (ALM) are provided, as well as random access memory blocks 134. One skilled in the art will appreciate that ALM 132 provides user programmable functions, e.g., through a six-input LUT in one embodiment. I/O banks 134 are disposed within region 106.
In one embodiment, the standard cells, represented by HLE 150a and 150b of
One skilled in the art will appreciate that the functionality defined for lanes 170, frames 174, and process nodes 178 of
A static timing analysis is performed in operation 312 of
Through the embodiments described above, enhancements and errata to an emerging protocol may be implemented with minimal impact as only a few metal masks need to be modified. In addition, increased performance is achieved as the interconnect delay has been reduced. The addition of the digital IP strip enables more functionality to be provided inside the core region of a given device. In one embodiment, the device has reduced power associated due to the reduced die area.
The circuits and methods associated with the digital strip described herein, may be incorporated into any suitable integrated circuit. For example, the method and system may be incorporated into other types of programmable logic devices such as programmable array logic (PAL), programmable logic array (PLA), field-programmable gate array (FPGA), field programmable logic array (FPLA), electrically programmable logic devices (EPLD), electrically erasable programmable logic device (EEPLD), logic cell array (LCA), just to name a few. The programmable logic device may be a part of a data processing system that includes one or more of the following components: a processor, memory; I/O circuitry, and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system.
Embodiments of the present invention may be practiced with various computer system configurations including hand-held devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a wire-based or wireless network. In addition, the embodiments described above may be incorporated into any commercially available electronic design automation (EDA) tool, including the Quartus® EDA tool of the assignee.
With the above embodiments in mind, it should be understood that the invention can employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
Although the method operations were described in a specific order, it should be understood that other housekeeping operations may be performed in between operations, or operations may be adjusted so that they occur at slightly different times, or may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in the desired way.
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
