Patent Application
20250185291
The present invention generally relates to semiconductor devices and processing methods, and more particularly to jumper connections employed to route signal lines in a semiconductor device.
Stacked transistor devices may be used to increase areal density of devices on a chip. Additionally, the close proximity of the overlying and underlying devices can be useful when forming paired devices, such as complementary semiconductor devices that include two devices of opposing polarity. However, positioning transistors in close proximity places spatial and electrical constraints that can make it challenging to provide required performance.
An additional challenge arises in providing electrical connections to these transistors. Contact and wire routing density have increasingly less space and therefore fewer options. To increase routability of wires, all available space needs to be considered.
Therefore, a need exists for new wiring structures that permit circuit routing without displacing earlier formed wiring components, e.g., contacts, metal lines, etc. A further need exists for new wiring structures that provide additional wiring options for increasingly dense metal structures on semiconductor devices.
In accordance with an embodiment of the present invention, a semiconductor device includes at least one active region layer having source/drain regions laterally disposed relative to one another in a row and having a zone bounded between adjacent source/drain regions. An embedded jumper is electrically connected to two adjacent source/drain regions within the zone. The embedded jumper provides a new wiring structure that permits circuit routing without displacing earlier formed wiring components, e.g., contacts, metal lines, etc. The embedded jumper is disposed on an active device layer and can permit wiring access between a top side and a bottom side of the device. The embedded jumper provides flexibility and opens up additional wiring options for increasingly dense metal structures on semiconductor devices.
The embedded jumper replaces a gate structure and/or device channels between source/drain regions within the zone. A new wiring structure is provided that permits circuit routing without displacing earlier formed wiring components, e.g., contacts, metal lines, etc. The embedded jumper is disposed on an active device layer and can permit wiring access between a top side and a bottom side of the device. The embedded jumper provides flexibility and opens up additional wiring options for increasingly dense metal structures on semiconductor devices.
In accordance with another embodiment of the present invention, a semiconductor device includes a row of source/drain regions laterally disposed relative to one another to provide a zone between adjacent source/drain regions. A top metallization region of the semiconductor device is positioned over the row of source/drain regions, and a bottom metallization region of the semiconductor device is positioned below the row of source/drain regions. An embedded jumper is electrically connected between two source/drain regions within the zone.
In accordance with another embodiment of the present invention, a semiconductor device, includes a row of source/drain regions laterally disposed relative to one another to provide a zone between adjacent source/drain regions. An embedded jumper is connected between adjacent source/drain regions within a zone. A single diffusion break is disposed in another zone between adjacent source/drain regions.
In some embodiments, the embedded jumper connects two adjacent source/drain regions and conducts charge in accordance with a transistor disposed within the row. The embedded jumper can electrically connect at least one component in the top metallization region of the semiconductor device to at least one component in the bottom metallization region of the semiconductor device. The embedded jumper can electrically connect a component in the top metallization region of the semiconductor device to another component in the top metallization region of the semiconductor device. The embedded jumper can electrically connect a component in the bottom metallization region of the semiconductor device to another component in the bottom metallization region of the semiconductor device. A series of embedded jumpers can be disposed between a plurality of adjacent source/drain regions within respective zones to arrange an electrical connection across multiple adjacent source/drain regions. The embedded jumper can replace a gate structure or semiconductor channels in the zone. A nonconducting diffusion break can be formed in another zone between the adjacent source/drain regions.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following description will provide details of preferred embodiments with reference to the following figures wherein:
In accordance with embodiments of the present invention, devices and methods are described which include embedding jumper connections within components of a semiconductor device to enable additional wire routing possibilities. The embedded jumpers can connect components laterally without interfering with source/drain region contacts, gate contacts or other structures. Embedded jumpers can be located within or below a gate electrode and can connect a source region and a drain region, two source regions, two drain regions or can be employed to bypass components and connect with other non-adjacent components.
In useful embodiments, a semiconductor structure includes an embedded jumper disposed within a gate region. The embedded jumper can include a conducting medium. A non-conducting medium, e.g., a diffusion break can be placed instead of or in addition to an embedded jumper. The embedded jumper can be employed in a single-sided or double-sided device. The embedded jumper can connect a top or upper metallization tier or region to a bottom or lower metallization tier or region. The embedded jumper can connect between top or upper metallization tier components, connect between bottom or lower metallization tier components or any combination thereof. The embedded jumper can occupy a space of a removed semiconducting channel or a removed gate electrode. The embedded jumper can connect across components resulting in at least two embedded jumper regions connected in series through, e.g., source/drain (S/D) regions or gate electrode regions.
The embedded jumper can be employed in middle of the line (MOL) structures to increase routability without getting in the way of gate or source/drain region contacts. The embedded jumpers in accordance with embodiments of the present invention provide new structures to enable circuit routing without displacing existing contact routing options.
In one illustrative semiconductor structure, a stacked channel field effect transistor device can employ embedded jumpers. In one embodiment, a method includes nanosheet device formation to build gate structures. Semiconductor placeholder regions are formed in deep S/D trenches. A backside substrate is removed and a backside interlevel dielectric layer (BILD) is formed. Semiconductor placeholder regions are recessed, and a dielectric cap (protection cap) is deposited and planarized in the recessed space. A mask, e.g., an organic planarizing layer (OPL) mask is deposited and opened up over select devices. A self-aligned BILD etch, bottom dielectric interface (BDI) etch, and gate nanosheet removal are performed. Embedded jumpers are formed in regions opened up for the selected devices. This can include a fill, planarization and an etch back to locate the embedded jumpers in between S/D regions or within a gate electrode region. The embedded jumper is then isolated by a dielectric fill and planarization process. Self-aligned backside contacts can be formed and processing can continue with backside power distribution network (BSPDN) formation.
In one embodiment, a semiconductor device includes at least one active region layer having source/drain regions laterally disposed relative to one another in a row and having a zone bounded between adjacent source/drain regions. An embedded jumper is electrically connected to two adjacent source/drain regions within the zone. The embedded jumper provides a new wiring structure that permits circuit routing without displacing earlier formed wiring components, e.g., contacts, metal lines, etc. The embedded jumper is disposed on an active device layer and can permit wiring access between a top side and a bottom side of the device. The embedded jumper provides flexibility and opens up additional wiring options for increasingly dense metal structures on semiconductor devices.
The embedded jumper replaces a gate structure and/or device channels between source/drain regions within the zone. A new wiring structure is provided that permits circuit routing without displacing earlier formed wiring components, e.g., contacts, metal lines, etc. The embedded jumper is disposed on an active device layer and can permit wiring access between a top side and a bottom side of the device. The embedded jumper provides flexibility and opens up additional wiring options for increasingly dense metal structures on semiconductor devices.
In accordance with another embodiment of the present invention, a semiconductor device includes a row of source/drain regions laterally disposed relative to one another to provide a zone between adjacent source/drain regions, a top metallization region of the semiconductor device positioned over the row of source/drain regions and a bottom metallization region of the semiconductor device positioned below the row of source/drain regions. An embedded jumper is electrically connected between two source/drain regions within the zone.
In accordance with another embodiment of the present invention, a semiconductor device, includes a row of source/drain regions laterally disposed relative to one another to provide a zone between adjacent source/drain regions. An embedded jumper is connected between adjacent source/drain regions within a zone. A diffusion break is disposed in another zone between adjacent source/drain regions.
In some embodiments, the embedded jumper connects two adjacent source/drain regions and conducts charge in accordance with a transistor disposed within the row. The embedded jumper can electrically connect at least one component in the top metallization region of the semiconductor device to at least one component in the bottom metallization region of the semiconductor device. The embedded jumper can electrically connect a component in the top metallization region of the semiconductor device to another component in the top metallization region of the semiconductor device. The embedded jumper can electrically connect a component in the bottom metallization region of the semiconductor device to another component in the bottom metallization region of the semiconductor device. A series of embedded jumpers can be disposed between a plurality of adjacent source/drain regions within respective zones to arrange an electrical connection across multiple adjacent source/drain regions. The embedded jumper can replace a gate structure and/or semiconductor channels in the zone. A nonconducting diffusion break can be formed in another zone between the adjacent source/drain regions.
In another embodiment, a method of forming a semiconductor device includes forming transistor structures with placeholders on a bottom of the source/drain regions. A substrate region of the backside of the device is replaced with a dielectric, and a capping layer is formed on the backside of the placeholders. A self-aligned backside etch is performed between two placeholders, to remove a channel region. An etch cavity formed by the self-aligned backside etch is filled to form the embedded jumper. The remaining portion of the etch cavity opening is filled with a non-conducting material. In this way, the transistor structure has the embedded jumper connecting directly between the source and drain regions, displacing a pre-existing channel region. Processing continues by forming back end of the line (BEOL) structures and layers.
Referring now to the drawings in which like numerals represent the same or similar elements and initially to
A wafer 100 includes a substrate 105 having multiple layers on which the semiconductor device will be fabricated. The substrate 105 can include any suitable substrate structure or material, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and preferably includes a monocrystalline semiconductor. In one example, the substrate 105 can include a substrate portion 102, etch stop layer 104 and semiconductor portion 106. Substrate portion 102 and semiconductor portion 106 include silicon-containing material. Illustrative examples of Si-containing materials suitable for the portions 102, 106 can include, but are not limited to, Si, SiGe, SiGeC, SiC and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.
An etch stop layer 104 is formed on the substrate portion 102. The etch stop layer 104 can include an epitaxially grown crystal structure. The etch stop layer 104 includes a material that permits the selective etching and removal of the substrate portion 102 in later steps. In one embodiment, the etch stop layer 104 includes SiGe although depending on the material of the portions 102, 106, other materials can be selected, e.g., SiGeC, SiC, etc.
Semiconductor portion 106 is provided on the etch stop layer 104. The semiconductor portion 106 can include a same material as the substrate portion 102, although other semiconductor materials can be employed, e.g., SiGe, SiGeC, SiC, etc.
A layer stack or stacks are applied to or formed on the semiconductor portion 106. In one embodiment, one or more nanosheets (NS) are applied to the semiconductor portion 106. In another embodiment, the layer stacks can be epitaxially grown using different chemistries to form layers having different properties. In an embodiment, a layer stack includes semiconductor layers 112, which function as channels between source/drain regions 114. The S/D regions 114 have associated placeholders 130 formed in trenches within the semiconductor portion 106. In one embodiment, the semiconductor portion 106 includes Si, and the placeholders 130 include SiGe, to provide selectable etching between the semiconductor portion 106 and the placeholders 130.
In useful embodiments, active region layers include S/D regions 114 laterally disposed relative to one another in a row. Intermittent regions (zones 135,
The gate structures 128 are formed between S/D regions 114. The gate structures 128 can include high dielectric constant (high-K) gate dielectric (not shown) in contact with semiconductor layers 112 which form the device channels, in this illustrative example. A gate metal 116 is provided to form a gate electrode. The gate structures 128 can include High-K Metal Gate (HKMG) structures, which selectively activate FETs that employ S/D regions 114. The gate metal 116 is electrically isolated from semiconductor portion 106 by a bottom dielectric interface (BDI) 108. The gate metal 116 is also electrically isolated by dielectric sidewall spacers 110 and 118.
A dielectric layer 120, such as, e.g., an interlevel dielectric layer (ILD) is formed. The dielectric layer 120 can include any suitable material, e.g., selected from the group consisting of silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C: H). The dielectric layer 120 can be deposited using chemical vapor deposition (CVD), although other deposition methods can be employed.
Middle of the line (MOL) contacts 122 are formed to make connections with the active regions (S/D regions 114). In useful embodiments, a silicide liner (not shown), such as Ti, Ni, NiPt is deposited first, then a diffusion barrier (not shown) can be formed in the trenches prior to a conductive fill. The diffusion barrier can include, e.g., TiN, TaN, or similar materials. The contacts 122 can include materials, such as, e.g., Cu, Ru, Mo, Rh, W, Ir, and alloys or combinations of these and other conductive materials.
A back end of the line (BEOL) layer 124, which can include metal structures and dielectric layers to complete a top region and provide electrical access to the devices formed. A carrier wafer 126 can be bonded to the BEOL layer 124. The carrier wafer 126 provides support and transportability to the wafer 100 for further processing which can include flipping the wafer 100 and removing portions of a bottom side of the stacked FET device.
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The opening 140 formation removes a portion of the semiconductor portion 106, the gate metal 116 that forms a gate electrode, insulation structures, such as, BDI 108, sidewall spacers 110 and semiconductor layers 112 (channels). A gate resistor 142 can be left or removed depending on the embodiment. The protection caps 134 protect the placeholders 130 during the etch.
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After the conductive fill, a metal recess process is performed to etch back the conductive fill to form an embedded jumper 144. The embedded jumper 144 is etched back to a position within S/D regions 114. The embedded jumper 144 makes electrical contact with and between adjacent S/D regions 114 and includes at least one conducting material. The embedded jumper 144 is embedded within front end of the line (FEOL) structures. In this way, the location and position of the embedded jumper 144 does not interfere with the routing of contacts 122 or other metal structures or wiring in the device. In one embodiment, the embedded jumper 144 is placed in a position where gate components and/or device channels of existing devices would have existed.
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The dielectric layer can be deposited using CVD, although other deposition methods can be employed. The dielectric layer and protective caps 134 are planarized, e.g., by CMP, to level a backside surface and form a dielectric plug 146.
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Processing continues with the formation of a backside interconnect layer 156, which can include metal structures and dielectric layers to complete the bottom side of the stacked FET device and provide electrical access to the devices formed. The backside interconnect layer 156 is formed on the dielectric layer 148 and the backside contacts 154.
The embedded jumper 144 can be employed in many configurations. Some of these non-limiting configurations will be illustratively described; however, other configurations and combinations of these configurations are contemplated. In one example, the embedded jumper 144 can include two or more conducting materials.
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The connection through the embedded jumper 144 in this embodiment is selectively controlled by activation of the channel 162 (semiconductor layer 112) using a gate structure to turn on the FET device (associated with the channel 162) within the electrical path 160. In other words, a FET (with channel 162) formed in a space adjacent to the embedded jumper 144 in accordance with the FET disposed within the same row as the embedded jumper 144. The switching on or off of this transistor will control the conduction of charge through the embedded jumper 144.
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In some embodiments, the SDB 180 can be employed in some selected devices while the embedded jumpers 144 can be employed with other selected devices on a single chip or wafer. In an embodiment, a gate resistor 142 can be included with the SDB 180. The SDB 180 can be employed in many configurations. Some of these non-limiting configurations will be illustratively described; however, other configurations and combinations of these configurations are contemplated. In one example, the SDB 180 can include two or more non-conducting materials. In another example, SDB 180 can include an airgap.
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Exemplary applications/uses to which the present invention can be applied include, but are not limited to semiconductor devices. Semiconductor devices can include processors, memory devices, application specific integrated circuits (ASICs), logic circuits or devices, combinations of these and any other circuit device. In such devices, one or more semiconductor devices can be included in a central processing unit, a graphics processing unit, and/or a separate processor- or computing element-based controller (e.g., logic gates, etc.). The semiconductor devices can include one or more on-board memories (e.g., caches, dedicated memory arrays, read only memory, etc.). In some embodiments, the semiconductor devices can include one or more memories that can be on or off board or that can be dedicated for use by a hardware processor subsystem (e.g., ROM, RAM, basic input/output system (BIOS), etc.).
In some embodiments, the semiconductor devices can include and execute one or more software elements. The one or more software elements can include an operating system and/or one or more applications and/or specific code to achieve a specified result. In still other embodiments, the semiconductor devices can include dedicated, specialized circuitry that perform one or more electronic processing functions to achieve a specified result. Such circuitry can include one or more field programmable gate arrays (FPGAs), and/or programmable applications programmable logic arrays (PLAs).
It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements of features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
Having described preferred embodiments of devices and methods (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
