Claims
- 1. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks arranged in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and a second embedded array block is in a column j+1, wherein j is an integer, wherein the RAM block includes at least 2048 bits of memory.
- 2. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; a plurality of embedded array blocks arranged in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and a second embedded array block is in a column j+1, wherein j is an integer; and a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks, wherein the first address comprises five bits.
- 3. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; a plurality of embedded array blocks arranged in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and a second embedded array block is in a column j+1, wherein j is an integer; and a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks, wherein two or more of the plurality of programmable interconnect lines are coupled to provide a second address to address inputs of the embedded array blocks, and the second address comprises eleven bits.
- 4. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks arranged in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and a second embedded array block is in a column j+1, wherein j is an integer, wherein a row of embedded array blocks comprises thirty-two embedded array blocks.
- 5. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks [between rows and columns of the programmable interconnect lines, wherein the embedded array blocks are arranged in a row and each embedded array block includes a RAM block] arranged in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and a second embedded array block is in a column j+1, wherein j is an integer, wherein a row of embedded array blocks is programmably configurable to be at least one of one 30K×1 memory, two 14K×1 memories, three 10K×1 memories, five 6K×1 memories, or seven 4K×1 memories.
- 6. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block, wherein the RAM block includes at least 2048 bits of memory.
- 7. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block; and a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks, wherein the first address comprises five bits.
- 8. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block; and a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks, wherein two or more of the plurality of programmable interconnect lines are coupled to provide a second address to address inputs of the embedded array blocks, and the second address comprises eleven bits.
- 9. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block, wherein a row of embedded array blocks comprises thirty-two embedded array blocks.
- 10. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block, wherein a row of embedded array blocks is programmably configurable to be at least one of one 30K×1 memory, two 14K×1 memories, three 10K×1 memories, five 6K×1 memories, or seven 4K×1 memories.
- 11. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks arranged,in a row, programmably coupled to the programmable interconnect lines, wherein each embedded array block includes a RAM block, a first embedded array block is in a column j, and, a second embedded array block is in a column j+1, wherein j is an integer.
- 12. The programmable logic integrated circuit of claim 11 wherein the logic array blocks include logic elements.
- 13. The programmable logic integrated circuit of claim 11 wherein two embedded array blocks of a row can be programmably combined to provide a larger memory than available with a single embedded array block.
- 14. The programmable logic integrated circuit of claim 11 further comprising:
a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks.
- 15. The programmable logic integrated circuit of claim 14 wherein two or more of the plurality of programmable interconnect lines are coupled to provide a second address to address inputs of the embedded array blocks.
- 16. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a plurality of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the embedded array blocks are arranged in adjacent columns of a single row and each embedded array block includes a RAM block.
- 17. The programmable logic integrated circuit of claim 16 wherein the logic array blocks include logic elements.
- 18. The programmable logic integrated circuit of claim 16 wherein two embedded array blocks of a row can be programmably combined to provide a larger memory than available with a single embedded array block.
- 19. The programmable logic integrated circuit of claim 16 further comprising:
a decoder coupled to receive a first address and generating a plurality of output control signals, each coupled to an enable input of one of the embedded array blocks.
- 20. The programmable logic integrated circuit of claim 19 wherein two or more of the plurality of programmable interconnect lines are coupled to provide a second address to address inputs of the embedded array blocks.
- 21. The programmable logic integrated circuit of claim 16 wherein programmable interconnect lines traveling in a direction perpendicular to the embedded array blocks do not pass through the row of embedded array blocks.
- 22. The programmable logic integrated circuit of claim 16 wherein programmable interconnect lines traveling in a direction perpendicular to the of embedded array blocks do not pass between two adjacent embedded array blocks though the single row of the embedded array blocks.
- 23. A programmable logic integrated circuit comprising:
a plurality of programmable interconnect lines arranged in rows and columns; a plurality of logic array blocks between rows and columns of the programmable interconnect lines, wherein the logic array blocks are arranged in rows and columns and programmably coupled to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions; and a first row of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the first row of embedded array blocks are formed along a first edge of the integrated circuit and each embedded array block includes a RAM block.
- 24. The programmable logic integrated circuit of claim 23 further comprising:
a second row of embedded array blocks, programmably coupled to the programmable interconnect lines, wherein the second row of embedded array blocks are formed along a second edge of the integrated circuit, opposite of the first edge, and each embedded array block includes a RAM block.
- 25. The programmable logic integrated circuit of claim 23 wherein each row of embedded array blocks further comprises a grid of stitching conductors to programmably stitch one embedded array block to other embedded array blocks in the row to form a larger-sized memory.
- 26. The programmable logic integrated circuit of claim 23 further comprising:
a plurality of IO bands comprising input and output circuitry, formed between the first and second rows of memory blocks.
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. nonprovisional application Ser. No. 09/609,102, filed Jun. 30, 2000, which claims the benefit of U.S. provisional application No. 60/142,141, filed Jul. 2, 1999, which are incorporated by reference along with all references cited in this application.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60142141 |
Jul 1999 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09609102 |
Jun 2000 |
US |
Child |
10177785 |
Jun 2002 |
US |