Patent Application
20080126753
1. Field of the Invention
The invention relates to embedded systems, and in particular, to a programmable co-processor architecture.
2. Description of the Related Art
Embedded systems are provided. An exemplary embodiment of an embedded system comprises a micro-processor and a co-processor. The co-processor processes only non-interruptible instructions. The micro-processor is powered by an operating system to control the embedded system. When task requires completing, the micro-processor appoints the co-processor to execute at least one batch command block. The batch command block is compiled with a sequence of non-interruptible instructions. When the task is complete, the co-processor outputs a response signal to the micro-processor.
The embedded system may further comprise a memory device storing a plurality of batch command blocks corresponding to at least one task. When a task is assigned to the co-processor, the corresponding batch command block(s) is/are fetched by the co-processor for execution.
The co-processor comprises a command queue, an execution engine and a support engine. The command queue queues non-interruptible instructions to be executed. The execution engine sequentially executes the non-interruptible instructions queued in the command queue. The support engine is accessed by the micro-processor to control the execution engine's execution flow.
Initially, the micro-processor sets a starting address of a batch command block corresponding to the task and sends an initial signal to the support engine. The support engine may comprise an address register for storage of the starting address, and the support engine fetches the batch command block according to the starting address. The execution engine is triggered to execute the non-interruptible instructions as long as the command queue is not empty. The support engine sends a response signal to the micro-processor upon completion of the task.
The micro-processor compiles the non-interruptible instructions or fetches the non-interruptible instructions from non-volatile memory to generate the batch command block and stores it in the memory device before sending the initial signal to the support engine. The response signal indicates an execution result or an exception event of the task. The micro-processor is interrupted by the response signal to take over the co-processor.
The non-interruptible instructions may comprise fundamental arithmetic instructions, memory access instructions and flow control instructions. The execution engine executes the fundamental arithmetic instructions, memory access instructions and flow control instructions. The embedded system may be a DVD-ROM, and the task may be a mechanic control operation thereof Alternatively, the embedded system may be an audio device, and the task may be a decoding process comprising arithmetic operations of adding, subtracting, multiplying and dividing.
A further embodiment provides an operating method based on the embedded system. A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The batch command blocks 302 are stored in the memory device 240. The memory device 240 may be a DRAM device for storing batch command blocks 302 dynamically compiled from the micro-processor 310. Alternatively, the memory device 240 may also be a read only memory such as firmware, with predefined batch command blocks 302 burned therein. In other case, the batch command blocks 302 may be provided externally, or instantly generated by the micro-processor 310 when needed. The co-processor 320 comprises a command queue 322, an execution engine 324 and a support engine 326. The support engine 326 is accessed by the micro-processor 310 to control the execution engine's execution flow. For example, execution flow comprises trigger start, pause execution and/or reset macro. When the micro-processor 310 delivers initial signal #IN to the support engine 326, appointing the signal to a batch command block 302, the command queue 322 fetches the batch command block 302 and extracts the non-interruptible instructions. As long as the command queue 322 is not empty, the execution engine 324 sequentially executes the non-interruptible instructions queued in the command queue 322. The initial signal #IN triggers the start of the execution engine 324, and the support engine 326 comprises an address register for storage of the starting address. According to the starting address, the command queue 322 can precisely locate the batch command block 302 and fetch it from the memory device 240. The support engine 326 determines whether the task is complete when the command queue 322 is empty. If the command queue 322 is empty, and the task is not complete, the co-processor is idle and waiting for the command queue being filled. When the task is complete, the support engine 326 sends a response signal #OUT to the micro-processor 310.
The response signal #OUT may be an interrupt or a polling signal to indicate the micro-processor 310 an execution result is available, or an exception is occurring in the co-processor 320. When the micro-processor 310 receives the response signal #OUT, its normal operation is interrupted to take over the co-processor 320. For example, the co-processor 320 may put an execution result in the memory device 240, and delivers the response signal #OUT to inform the micro-processor 310 to fetch it.
The non-interruptible instructions may be categorized into fundamental arithmetic instructions, memory access instructions and flow control instructions. The fundamental arithmetic instructions are typically adding, subtracting, multiplying and dividing. The memory access instructions are read and write of memory unit, and the flow control instructions may include simply jump or loop. The fundamental arithmetic instructions, the memory access and flow control are executed by the execution engine 324. Thus, when the non-interruptible instructions are extracted into the command queue 322, the execution engine 324 executes them. As an example, if the task is a mechanical control operation of a DVD-ROM, the co-processor 320 becomes a temporary ASIC when programmed by the predefined batch command block 302. If the embedded system 300 is an mp3 player, and the task is audio decoding, the co-processor 320 becomes a decoder performing arithmetic operations on the audio data when programmed by the corresponding context block 202. Various applications may be defined by compiling non-interruptible instructions into the batch command block 302, and the embedded system is not limited to the described embodiments.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
