Encapsulated metal resistor

Abstract

The method provides a semiconductor structure and method for forming such a structure that provides for protection for resistive layers formed within the structure from contamination from adjacent layers. By encapsulating the resistive layer in a material that is resistant to the diffusion of contaminants it is possible to protect the resistive material during the processing required to manufacture the structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described with reference to the accompanying drawings in which:

FIG. 1 is a cross section through a known metal film.

FIG. 2 is a graph showing in schematic form the relationship between observed TCR and resistivity of a deposited metal film with variations in deposition and substrate conditions.

FIG. 3 is a schematic showing a semiconductor stack formed in accordance with the teaching of the invention.

FIG. 4 shows one example of a process flow according to the teaching of the invention.

FIG. 5 shows an example of a dual deposition technique that may be employed to provide side fillets of the barrier material with FIG. 5a showing the stack with the deposition layers provided and FIG. 5b the same stack after a first etch back process.

FIG. 6 shows how a stack may be formed on a thermally isolated region within the substrate according to the teaching of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

The teaching of the invention will now be explained with reference to FIGS. 3 to 6 which are provided for explanation purposes. It is not intended that the invention be limited in any way except as may be deemed necessary in the light of the appended claims.

As shown in FIG. 3 a multi-layer semiconductor structure 300 in accordance with the teaching of the invention includes a plurality of layers 305 or levels. Where elements have been described with reference to FIG. 1, the same reference numerals will be used. Specific layers are used for different purposes such as conductive layers or insulating layers, as will be appreciated by the person skilled in the art. Within the context of the present invention as part of the fabrication process for such a multi-layer structure a resistive layer 110 formed from a bulk material 115 bounded above and below by a surface 115a, 115b, is formed as an intermediary layer within the structure. The resistive layer 110 is bounded above and below by a barrier layer 310a, 310b, and collectively the three layers form a stack arrangement. The barrier layer serves to encapsulate the resistive layer 110 and is preferably formed of a material which is resistant to the diffusion of oxygen or other contaminants from the neighbouring layers. A typical metal chosen for the resistive layer is titanium (Ti) and it is found that a suitable barrier material is titanium nitride (TiN). TiN is a known as a semiconductor compatible film and as part of this process is converted into a dense ceramic like film that is resistant to the diffusion of other materials. Although it is obviously a source of nitrogen within the stack, it is found that the presence of the nitrogen is less detrimental to the performance of the resistive layer than for example the diffusion of oxygen into contact with the Ti metal layer. TiN is particularly effective for blocking the diffusion of oxygen.

Within the multilayer structure 300, two or more metal interconnect layers are typically provided, shown in FIG. 3 as a first metal layer 315 and a second metal layer 320. The metal layers are located below and above the resistive stack arrangement respectively and are insulated from the stack by providing inter-metal dielectric layers 325a, 325b.

When forming the structure according to the teaching of the invention desirably, as shown in FIG. 4, conventional integrated circuit processing steps are completed up to the formation of the first metal layer (Step 400). An inter-metal dielectric, such as a layer of about 1 micron of a variety of chemically vapour deposited (CVD) silicon dioxides are provided above the first metal layer (Step 410). The stack arrangement is then formed using a sputtering technique (Step 420). A second inter-metal dielectric layer (Step 430) and a second metal layer (Step 440) are then provided above the stack arrangement.

Using the teaching of the invention it has been observed that with an appropriate choice of TiN material thickness and deposition conditions that it is possible to ensure that the Ti resistor TCR characteristics stay above 0.25%C⁻¹ even after heat cycles of about 460° C. for 10 minutes. Thicker Ti films will serve to improve the resilience of the film to heat exposure but there is a cost in the overall sheet resistance being reduced, as the conductivity of the interior material is generally considered better than that of the surface layers.

While FIGS. 3 and 4 have been used to illustrate in generality the arrangement of a metal restive layer with barrier layers located above and below, it is usual that such fabrication will only be a small part of the overall fabrication processing steps. The following examples are illustrative of the fact that depending on the specifics of the desired application, differing combinations of steps will be employed. Where process steps employed are of the conventional and well known variety they are not discussed in detail but the specifics will be well known to the person skilled in the art. While the metal film layers may be referenced as being an intermediary layer within the context of a larger stack arrangement it will be understood that such an intermediary layer may be considered as forming whole or part of an entire layer within the stack.

1/ Formation of TiN/Ti/TiN Stack

Step                            Comments
Main IC process steps up to     Completes all transistors, etc. up to
and including Metal 1           formation of metal interconnect
Deposit inter metal dielectric  Typically ~1 μm of a variety of CVD
(IMD-1)                         silicon dioxides
RF Sputter                      Smoothens region where resistors will
                                be formed
Sputter TiN/Ti/TiN stack        Typically 25 nm/150 nm/25 nm
Photo mask resistor             Defines shape of resistor
Etch Resistor                   Defines shape of resistor
Deposit Resistor cap dielectric Typically 100–200 nm, provides insulation
                                between resistor and Metal 2
Photo mask Via 1                Creates via holes in the Resistor cap
                                layer and the underlying IMD-1 to allow
                                Metal 1 to Metal 2 interconnection.
Etch Via 1                      Typically an RIE etch penetrating these
                                dielectric layers. It must have high
                                selectivity to TiN and Ti so the etch will
                                not penetrate these layers during the
                                extended time required to etch the
                                underlying IMD-1.
Sputter Metal 2                 Typically 400 nm of various Aluminium
                                alloys
Photo mask Metal 2              Etc.

While the steps outlined above may be practical in many instances, the resultant structure has a high selectivity to TiN. There are a number of possible alternatives that may be employed including those as follows:

2/ Move Ti Stack Downwards to Reduce VIA Over-Etch Time.

Step                            Comments
Main IC process steps up to and Completes all transistors, etc. up to
including Metal 1               formation of metal interconnect
Deposit 100–200 nm bed oxide    Insulates subsequent Ti stack from M1
RF Sputter                      Smoothens region where resistors will
                                be formed
Sputter TiN/Ti/TiN stack        Typically 25 nm/150 nm/25 nm
Photo mask resistor             Defines shape of resistor
Etch Resistor                   Defines shape of resistor
Deposit IMD-1                   Typically ~1 μm of a variety of CVD
                                silicon dioxides
Photo mask Via 1                Creates via holes in the Resistor cap
                                layer and the underlying IMD-1 to
                                allow Metal 1 to Metal 2
                                interconnection.
Etch Via 1                      Typically an RIE etch penetrating these
                                dielectric layers. As most of the etching
                                is done before hitting the Ti stack the
                                selectivity requirement is lower.
Sputter Metal 2                 Typically 400 nm of various Aluminium
                                alloys
Photo mask Metal 2              Etc.

It is often difficult to guarantee adequate selectivity to Ti compounds as they have high volatility in etch atmospheres so the following sequence is also useful at the cost of another masking step.

3/ Separate Via Etch for Resistors from Main via Etch

Step                            Comments
Main IC process steps up to     Completes all transistors, etc. up to
and including Metal 1           formation of metal interconnect
Deposit inter metal dielectric  Typically ~1 μm of a variety of CVD
(IMD-1)                         silicon dioxides
RF Sputter                      Smoothens region where resistors will
                                be formed
Sputter TiN/Ti/TiN stack        Typically 25 nm/150 nm/25 nm
Photo mask resistor             Defines shape of resistor
Etch Resistor                   ”
Deposit Resistor cap dielectric Typically 100–200 nm, provides insulation
                                between resistor and Metal 2
Photo mask Via 1a               Creates via holes only in the Resistor
                                cap layer
Etch Via 1a                     Typically an RIE etch penetrating these
                                dielectric layers. Selectivity
                                requirements are very relaxed as the
                                etch can be set-up to stop more or less
                                as soon as the TiN top layer is
                                encountered.
Photo mask Via 1b               Creates holes only in the IMD-1 layer to
                                allow Metal 1 to Metal 2 interconnection.
Etch Via 1b                     Slight increase in etch time required to
                                overcome added Resistor cap thickness.
Sputter Metal 2                 Typically 400 nm of various Aluminium
                                alloys
Photo mask Metal 2              Etc.

4/ Another version arises if there is still too much ingress of oxygen or nitrogen at the sidewalls of the stack. The schemes presented above leave the Ti sidewall exposed during the subsequent processing. Nitrogen or oxygen may penetrate the film sufficiently to impact the resistivity and TCR. In this situation it is possible to deposit and pattern the stack in two steps as shown below.

Step                            Comments
Main IC process steps up to     Completes all transistors, etc. up to
and including Metal 1           formation of metal interconnect
Deposit inter metal dielectric  Typically ~1 μm of a variety of CVD
(IMD-1)                         silicon dioxides
RF Sputter                      Smoothens region where resistors will
                                be formed
Sputter TiN/Ti only             Typically 25 nm/150 nm
Photo mask resistor             Defines shape of resistor
Etch Resistor                   Defines shape of resistor
Sputter TiN top cap             Typically 25 nm to seal top and edges of
                                Ti film
Photo mask TiN top cap          Overlay requirement around TiN/Ti main
                                track
Etch TiN top cap
Deposit Resistor cap dielectric Typically 100–200 nm, provides
                                insulation between resistor and Metal 2
Photo mask Via 1                Creates via holes in the Resistor cap
                                layer and the underlying IMD-1 to allow
                                Metal 1 to Metal 2 interconnection.
Etch Via 1                      Typically an RIE etch penetrating these
                                dielectric layers. It must have high
                                selectivity to TiN and Ti so the etch will
                                not penetrate these layers during the
                                extended time required to etch the
                                underlying IMD-1.
Sputter Metal 2                 Typically 400 nm of various Aluminium
                                alloys
Photo mask Metal 2              Etc.

Clearly this method has the disadvantage of increased complexity and the resistor width has increased due to the overlapping cap and its overlay tolerance to the Ti line beneath it. However it is particularly useful for high sensitivity applications where there is a possibility of contaminant ingress through the side walls and it is important that this be minimised.

5/ Another important variation can be defined, an example of which is shown in FIG. 5 in which the top TiN layer is deposited in two stages with an etch back in between to define a sidewall protection layer which will restrict contaminants from diffusing into the resistor from the side while still allowing narrow lines and spaces with no additional spacing for misalignment needed.

Step                            Comments
Main IC process steps up to     Completes all transistors, etc. up to
and including Metal 1           formation of metal interconnect
Deposit inter metal dielectric  Typically ~1 μm of a variety of CVD
(IMD-1)                         silicon dioxides
RF Sputter                      Smoothens region where resistors will
                                be formed
Sputter TiN/TiTiN               Typically 25 nm/150 nm/35 nm (note
                                increased top TiN layer thickness to
                                allow for later over etch; this top TiN
                                layer must be deposited so that there is
                                good coverage of the previously etched
                                and exposed TiN/Ti/TiN sidewall.
Photo mask resistor             Defines shape of resistor
Etch Resistor                   Defines shape of resistor
Sputter TiN top cap             Typically 25 nm to seal top and edges of
                                Ti film
Etch back TiN top layer in      Stop when underlying IMD surface is
directional etch (e.g. RIE)     exposed leaving sidewall protection
                                layer of TiN.
Deposit Resistor cap dielectric Typically 100–200 nm, provides insulation
                                between resistor and Metal 2
Photo mask Via 1                Creates via holes in the Resistor cap
                                layer and the underlying IMD-1 to allow
                                Metal 1 to Metal 2 interconnection.
Etch Via 1                      Typically an RIE etch penetrating these
                                dielectric layers. It must have high
                                selectivity to TiN and Ti so the etch will
                                not penetrate these layers during the
                                extended time required to etch the
                                underlying IMD-1.
Sputter Metal 2                 Typically 400 nm of various Aluminium
                                alloys
Photo mask Metal 2              Etc.

Other variations and sequences are possible if the resistor is to be located elsewhere in the metal interconnection stack or if there are via plugs used in the process. However it will be understood that the overall plan is the same.

The use of TiN as a semiconductor compatible film is recognised and the present inventors have taken advantage of the properties of the TiN, which is converted into a dense ceramic-like film which is relatively resistant to the diffusion of other materials, to provide a protective barrier adjacent to the resistive material which is chosen in this exemplary arrangement to be Ti. While TiN is obviously a heavy source of nitrogen in the stack of materials this seems to be of less importance than its ability to exclude other materials such as oxygen. It will be understood however that the TiN/Ti stack that is described is purely exemplary of the type of barrier arrangement that could be used within the context of the teaching of the invention and that other barrier materials may offer similar or improved performance.

In accordance with the teaching of the invention it is found that with appropriate choice of the TiN (or other barrier material) thickness and deposition conditions we can ensure that the Ti resistor TCR stays above 0.25%/C even after heat cycles of 460 C for 10 minutes. Thicker Ti films improve the resilience of the film to heat exposure but at a cost of reducing the sheet resistance.

The provision of a stack arrangement in accordance with the teaching of the invention is advantageous for a number of applications but specifically for applications where the small changes in the resistance of the formed resistors are indicative of actual measurements that require sensing. A resistor formed with barrier layers according to the teaching of the invention has improved sensitivity to incident signals and can therefore be used in environments where such sensitivity is required. As such it will be appreciated that the resistors formed using the teaching of the invention using metal films are configured to have high resistivity such that they are sensitive to small changes in an incident signal. Such a signal will typically be provided by irradiation of the resistor, with the output of the resistor being indicative of changes in the thermal radiation incident on the resistor.

One such application or environment is in thermally sensitive environments where the overall signal output of the resistive material is based on a temperature fluctuation. In such applications it is known to use the thermal properties of the resistive material as an indicator of a change in the environment being sensed. With improvements offered in the response characteristics of the resistive material it is important that the response provided in not based on a spurious signal arising from the actual substrate in which the resistor is embedded. The present invention addresses this problem by providing the resistive stack in a substrate region that is thermally isolated from the remaining portions of the substrate.

FIG. 6 shows an example of such a structure. In FIG. 6a a plan view of a substrate including two resistors formed in accordance with the teaching of the invention is shown while FIG. 6b shows a sectional view.

As shown in the views of FIG. 6 one way to provide for thermal isolation between the resistive stack structure and remaining portions of the electrical circuit with which it is coupled is to provide a thermally isolated table 610 which is formed by etching a cavity 605 in the silicon substrate 105. The extent of the cavity may be defined by the use of trenches 611 which can control the extent of the etch process. The cavity serves to insulate the table 610 from the substrate below. Slots 615 can be provided to insulate the table from any thermal gradient in portions of the chip beside the table. In the example of FIG. 6, first 620 and second 625 resistors are provided on the table, and while not shown in either view it will be understood that the resistors are fabricated in a stack arrangement such as was described in FIG. 4. In this illustrated exemplary embodiment the resistors are patterned and etched such that their final configuration is a meander configuration, specifically a snake (S) configuration. It will be appreciated that the actual configuration of the resistors is not important, what is important is that the main portion of the fabricated resistor is provided on a thermally insulated table.

Each of the two resistors is provided with contact points 630, to facilitate connection of the resistors to the remaining portions of the electrical circuit (not shown).

It will be understood that in this embodiment while FIG. 6 shows the formation of a table with two resistors, that any number of resistors could be provided, and what is important is that the table provides a level of thermal isolation for the resistor(s) provided thereon. If the circuit employs additional thermally sensitive components these too could be provided on dedicated thermally isolate regions, each of which are desirably formed using MEMS fabrication techniques. In the context of a thermal radiation sensor, the provision of the resistive elements on a thermally isolated region within the substrate ensures that the output of the resistor is dependent on given input radiation flux density as opposed to thermal effects from other elements located on the substrate.

As was mentioned above heat sensitive resistors are characterized by having a known temperature coefficient of resistance (TCR), and will absorb heat from the incoming radiation if they are illuminated by it. Using a stack arrangement where the TCR parameters of the resistive elements are not degraded through the fabrication process and then having that formed stack located on a thermally isolated region serves to improve the response characteristics of the resistive element and the circuit of which it forms a part.

The construction of a table and location of the radiation sensitive element thereon ensures that the table is poorly coupled thermally while ensuring the radiation sensitive resistor response can be linked back to the quantity that it is designed to sense. Where two or more resistors are provided on a table, their environment is isothermal. It will be understood that although the thermal isolation of the table slightly degrades the use of such arrangements for high performance devices, that this can be modified by varying the aspect ratio of the table legs. The thermal conductance of the table is dominated by the aspect ratio of the table legs and thus, widening the legs to accommodate two resistors will cause a decrease in the achievable thermal resistance from the table to the substrate (the main heat sink in such systems). It will therefore be understood that as the legs affect the total DC response and the time constant of response of the sensor, that there is a certain trade-off possible where the designer of the system may choose different dimensions of legs depending on the speed of response versus accuracy required for the system

While this embodiment has been described with reference to a preferred implementation where two resistive elements are provided on a thermally isolated table it will be understood that this illustration is exemplary of the type of is benefit that may be achieved using the teaching of the invention. Such teaching may be considered as providing a thermally sensitive electrical element on a first region which is thermally isolated from the remainder of the substrate. Such thermal isolation has been described with reference to the embodiment where the table is fabricated in the substrate, but it will be understood that equivalently a table could be fabricated on a substrate. Such a structure could be provided by for example, depositing a sacrificial layer on an upper surface of the substrate, then the sensor element layers, including support layers, and then removing the sacrificial layer, leaving a freestanding table. Alternative implementations where instead of the sacrificial layer, a deposited layer is provided having high thermal coefficients such that it serves to thermally isolate the formed sensor elements located thereabove from thermal effects present in the substrate. These and other modifications will be apparent to the person skilled in the art as a means to provide a thermal barrier under the electrical elements where high degrees of thermal isolation are required.

It will be appreciated that as the present invention teaches the provision of a multilayer arrangement that the words upper and lower have been used extensively within the present specification to illustrate relative positions of layers within the multi-layer structure. Such language is used for exemplary descriptive purposes and it is not intended that the invention be limited in any fashion except as may be deemed necessary in the light of the appended claims.

While the invention has been described with reference to the exemplary embodiments of FIGS. 3 to 6, it will be understood that these are provided for an understanding of the teaching of the invention and it is not intended to limit the invention in any way except as may be deemed necessary in the light of the appended claims. The person skilled in the art will understood that where integers or components are described with reference to any one embodiment that these integers or components may be interchanged for others without departing from the spirit or scope of the invention which is to be construed as limiting only insofar as is deemed necessary in the light of the appended claims.

The words comprises/comprising when used in this specification are to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers , steps, components or groups thereof.

Claims

1. A multilayer semiconductor structure including a metal film resistive element formed as an intermediary layer within the structure, the resistive element being encapsulated within a barrier material, the barrier material protecting the resistive element from diffusion of contaminants from adjacent layers.

2. The structure as claimed in claim 1 wherein the encapsulation of the resistive element within the barrier material defines a stack within the structure, the stack having a first and second layer formed from the barrier material, the first and second layers sandwiching the resistive element therebetween, the resistive element being a third layer within the stack.

3. The structure as claimed in claim 2 wherein the depth of each of the first and second layers is significantly less than the depth of the third layer.

4. The structure as claimed in claim 3 wherein the depth of each of the first and second layers is an order of magnitude less than that of the third layer.

5. The structure as claimed in claim 4 wherein the depth of the third layer is of the order of hundreds of nanometres.

6. The structure as claimed in claim 1 wherein the resistive element is formed from a titanium film.

7. The structure as claimed in claim 6 wherein the barrier material is formed from titanium nitride.

8. The structure as claimed in claim 2 wherein the stack is formed using sputtering techniques.

9. The structure as claimed in claim 1 wherein the resistive metal is thermally sensitive.

10. The structure as claimed in claim 2 wherein the stack is provided between a first metal interconnect layer and a second metal interconnect layer.

11. A thermal sensor including a semiconductor structure as claimed in claim 1.

12. The structure as claimed in claim 2 wherein the structure forms part of an electrical circuit fabricated on a semiconductor substrate, the resistive element being a thermally sensitive electrical element providing an output which contributes to the overall output of the circuit and wherein the structure is located on a first region of the substrate which is thermally isolated from the remainder of the substrate.

13. The structure as claimed in claim 12 wherein the first region is formed in the substrate.

14. The structure as claimed in claim 12 wherein the first region is formed on the substrate.

15. The structure as claimed in claim 12 wherein the first region is thermally isolated from the substrate by providing an evacuated cavity below the first region.

16. The structure as claimed in claim 12 wherein the first region is thermally isolated from the substrate by providing an insulating layer between the first region and the substrate below.

17. The structure as claimed in claim 12 wherein the first region is suspended relative to the substrate.

18. The structure as claimed in claim 12 wherein the first region provides a substantially isothermal structure.

19. The structure as claimed in claim 12 wherein the first region is coupled at one or more edge portions to the substrate.

20. The structure as claimed in claim 19 wherein the first region is provided as a table, the table being supported relative to the substrate by the provision of one or more legs, the leg(s) being provided at edge portions of the table.

21. A thermal sensor fabricated on a semiconductor substrate, the sensor including a resistive element provided in a stack structure, the resistive element including a metal film resistive element formed as an intermediary layer within the structure, the resistive element being encapsulated within a barrier material, the barrier material protecting the resistive element from diffusion of contaminants from adjacent layers of the stack, the resistive element providing an output which contributes to the overall output of the thermal sensor and wherein the stack structure is formed on a first region which is thermally isolated from the semiconductor substrate.

22. A method of forming a multilayer semiconductor structure, the method including sequential steps of: a) processing the semiconductor to form a first metal interconnect layer,b) providing a stack arrangement above the first metal interconnect layer, the stack arrangement including a resistive element encapsulated within a barrier material, the barrier material serving to protect the resistive element from diffusion of contaminants from adjacent layers of the multilayer structure,c) providing a second metal interconnect layer above the stack arrangement.

23. The method as claimed in claim 22 wherein prior to providing the second metal interconnect layer, the method includes the steps of: a) masking and etching the stack arrangement to provide a resistor of a predefined configuration.

24. The method as claimed in claim 22 wherein the provision of the stack arrangement is effected using sputtering deposition techniques.

25. The method as claimed in claim 22 wherein the stack arrangement is formed from a first film of a barrier material, a film of resistive material located thereabove and a second film of the barrier material located above the film of resistive material.

26. The method as claimed in claim 25 wherein the barrier material is formed from titanium nitride and the resistive material from titanium.

27. The method as claimed in claim 26 wherein prior to the provision of the stack arrangement, the method includes the step of smoothening the surface of the semiconductor structure in the region where the stack is to be formed.

28. The method as claimed in claim 27 wherein the smoothening is achieved using an RF sputtering technique.

29. The method as claimed in claim 22 wherein subsequent to the formation of the stack arrangement and prior to the formation of the second metal interconnect layer, the method includes the steps of forming a dielectric layer above the stack and below the interconnect.

30. The method as claimed in claim 22 including one or more etch steps, the etch steps being effected to provide one or more vias between the two metal layers so as to allow subsequent metal to metal interconnection.

31. The method as claimed in claim 30 wherein the etch technique used has high selectivity to the materials used in the stack arrangement such that the etch does

32. The method as claimed in claim 31 wherein the etch is a reactive ion etch (RIE).

33. The method as claimed in claim 22 wherein the structure is formed on a semiconductor substrate, the method including the additional step of thermally isolating the stack from other portions of the substrate.

34. The method as claimed in claim 33 wherein the step of thermally isolating the stack includes an etching of the substrate below the stack so as to define a cavity below the stack.

35. The method as claimed in claim 34 wherein the etching defines a table having located thereon the stack, the table being coupled to the substrate by one or more legs.

36. The method as claimed in claim 23 wherein the predetermined configuration is a meander pattern.