Enhanced diagnosis with limited failure cycles

Abstract

Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary software-based chain diagnosis method.

FIG. 2 shows a first exemplary method of ordering production scan patterns.

FIG. 3 shows a second exemplary method of ordering production scan patterns.

FIG. 4 shows a third exemplary method of ordering production scan patterns.

FIG. 5 shows an example of per-cycle-based failure logging.

FIG. 6 shows an example of per-pin-based failure logging.

FIG. 7 shows a first exemplary method of per-pin based diagnosis.

FIG. 8 shows a second exemplary method of per-pin based diagnosis.

FIG. 9 shows a third exemplary method of per-pin based diagnosis.

FIG. 10 is exemplary pseudocode showing an exemplary diagnosis method that was used to produce some of the experimental results reported in this disclosure.

FIG. 11 is a graph of exemplary experimental results involving static pattern ordering diagnosis and conventional diagnosis.

FIG. 12 is a graph of exemplary experimental results involving dynamic pattern ordering diagnosis and conventional diagnosis.

FIG. 13 is a graph of exemplary experimental results involving per-pin based diagnosis and per-cycle based diagnosis.

FIG. 14 is a diagram illustrating an exemplary client-server network environment.

FIG. 15 is a diagram illustrating an exemplary method of performing an embodiment of the disclosed technology using a client-server network, such as the one illustrated in FIG. 14.

Claims

1. A method for diagnosing defects in a circuit, the method comprising: receiving failure log data from a test of the circuit;identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains or observed at one or more primary outputs after application of a test pattern during the test;applying a per-pin based diagnosis technique to the truncated failure data to identify one or more fault candidates in the circuit; andstoring a list of the fault candidates.

2. The method of claim 1, wherein the fault candidate is a faulty scan cell candidate.

3. The method of claim 1, wherein the fault candidate is a logic fault candidate.

4. The method of claim 1, wherein applying the per-pin based diagnosis technique further comprises: identifying a last observed failure cell of the scan chains or a last observed failure cycle of the primary outputs from the truncated failure data; andmasking, during simulations performed as part of the per-pin based diagnosis technique, one or more scan cells of the one or more scan chains after the last observed failure cell or one or more cycles from the one or more primary outputs after the last observed failure cycle.

5. The method of claim 4, wherein applying the per-pin based diagnosis technique further comprises identifying from the failure log data a fault type, and wherein masking comprises masking the one or more scan cells or primary outputs after the last observed failure cell or last observed failure cycle.

6. The method of claim 5, wherein one or more fault types are identified in two or more scan chains or in two or more system logic sections.

7. The method of claim 1, wherein the failure log data indicates a last observed failure cell for the one or more scan chains, wherein the scan chains comprise a last scan cell, and wherein applying the per-pin based diagnosis technique comprises masking one or more scan cells of the scan chains between the last observed failure cell and the last scan cell during simulations performed as part of the per-pin based diagnosis technique.

8. The method of claim 1, wherein applying the per-pin based diagnosis technique further comprises determining a fault range based at least in part on a last-logged failure cycle in the truncated failure data.

9. The method of claim 8, wherein determining the fault range comprises loading the one or more scan chains with at least some masked values during simulations performed as part of the per-pin based diagnosis technique.

10. The method of claim 8, further comprising injecting faults into one or more cells of the one or more scan chains during simulations performed as part of the per-pin based diagnosis technique.

11. The method of claim 1, wherein the test of the circuit comprises loading test patterns into the one or more scan chains and applying the test patterns to one or more system logic sections, the test patterns being arranged by a pattern ordering method that orders the test patterns based at least in part on their diagnostic metrics.

12. The method of claim 11, wherein the pattern ordering method is applied before the one or more fault candidates are identified.

13. The method of claim 11, wherein the pattern ordering method is applied after a faulty scan chain is identified, and wherein the pattern ordering method orders the test patterns based at least in part on their diagnostic coverage of the faulty scan chain.

14. The method of claim 11, wherein the pattern ordering method is applied after one or more faulty scan cells or primary outputs are identified, and wherein the pattern ordering method orders the test patterns based at least in part on their diagnostic coverage of logic fault candidates that explain the one or more faulty scan cells or primary outputs.

15. The method of claim 1, wherein the number of failure cycles recorded in the failure log data for a respective test pattern applied during testing is determined at least in part by user input.

16. The method of claim 1, wherein the failure log data is associated with compressed test responses captured during the test.

17. An electronic design automation system configured to perform the method of claim 1.

18. A computer-readable medium containing instructions for causing a computer to perform the method of claim 1.

19. A computer-readable medium comprising the list of faulty scan cell candidates determined according to the method of claim 1.

20. A method for an electronic circuit design, the design comprising one or more scan chains with a plurality of scan cells, the method comprising: receiving one or more coverage scores for one or more of the scan cells, the coverage scores being associated with one or more scan patterns;determining, according to the one or more coverage scores, a diagnosis coverage figure for the scan chain in relation to the one or more scan patterns; andstoring the diagnosis coverage figure.

21. The method of claim 20, further comprising ordering at least some of the scan patterns according to their respective diagnosis coverage figures.

22. The method of claim 21, further comprising: loading at least some of the scan patterns into the one or more scan chains; andtesting the one or more scan chains using the loaded patterns.

23. The method of claim 22, further comprising providing results of the testing to a per-pin based tester.

24. The method of claim 22, further comprising providing results of the testing to a per-cycle based tester.

25. The method of claim 20, further comprising identifying one or more failing scan chains and thereafter determining one or more diagnostic coverage figures for the failing scan chains.

26. The method of claim 20, wherein determining one or more diagnosis coverage figures comprises averaging two or more of the coverage scores.

27. The method of claim 20, wherein the scan chain is a first scan chain with a first plurality of scan cells, the design further comprising a second scan chain with a second plurality of scan cells, wherein the coverage scores are for at least one scan cell of the first plurality of scan cells and at least one scan cell of the second plurality of scan cells, and wherein the diagnosis coverage score is determined for both the first scan chain and the second scan chain.

28. A method for an electronic circuit design, the design comprising one or more system logic sections, the method comprising: determining one or more diagnosis coverage figures for one or more test patterns in a set of test patterns, wherein the diagnosis coverage figure is based at least in part on a number of fault pairs in the one or more system logic sections distinguished by the one or more patterns;ordering at least some of the patterns based at least in part on the one or more diagnosis coverage figures; andstoring the ordered patterns.

29. A method for diagnosing defects in a circuit, comprising: receiving information from multiple tester channels indicative of failing test responses produced by the circuit in response to one or more test patterns, the information including an indication that test response data from one or more of the test channels is truncated for one or more of the test patterns;simulating one or more of the test patterns being loaded into scan chains and applied to system logic sections of the circuit, the simulation comprising modifying values in scan cells associated with the one or more truncated test channels;determining a range of one or more fault candidates based at least in part on the simulation; andstoring the range of the one or more fault candidates.

30. The method of claim 29, wherein at least some of the values are modified based at least in part on a determined fault type.

31. The method of claim 29, wherein at least some of the values are modified to unknown values.

32. The method of claim 29 wherein the range includes the last scan cell in a corresponding scan chain.

33. The method of claim 29 further comprising repeating the act of simulating but modifying only values within the range.

34. The method of claim 33, further comprising: determining a revised range of one or more fault candidates based at least in part on the repeated simulation; andstoring the fault candidates from the revised range.

35. The method of claim 29, wherein the information received comprises a pin-based failure log.

36. A computer-readable medium comprising computer-executable instructions for causing a computer to perform the method of claim 29.

37. A diagnostic system configured to perform the method of claim 29.

38. A method for diagnosing defects in one or more scan chains of a circuit, the scan chains respectively comprising one or more scan cells, the method comprising: receiving failure log data from a test of the circuit;identifying truncated failure data in the failure log data, the truncated failure data being associated with test results captured in one or more scan chains after application of a test pattern during test;applying a per-pin based diagnosis technique to the truncated failure data to identify one or more faulty scan cell candidates in the scan cell chains; andstoring a list of the faulty scan cell candidates.