"High-Voltage Regulation and Process Considerations for High-Density 5 V-Only E.sup.2 PROM's", by Duane H. Oto, Vinod K. Dham, Keith H. Gudger, Michael J. Reitsma, Geoffrey S. Gongwer, Yaw Wen Hu, Jay F. Olund, H. Stanley Jones, Jr., and Sidney K. Nieh, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 532-537. |
"EPROM-based Logic Chip Opens its Gates to All Flip-Flop Types, Clocks," by Robert Hartman and Sau-Ching Wong, Electronic Design, Jul. 11, 1985, pp. 109-118. |
"A 9-Nanosecond, Low-Standby-Power CMOS PLD with a Single-Poly EPROM Cell," by S. Frake, M. Knecht, P. Cacharelis, M. Hart, M. Manley, R. Zeman, IEEE Intl. Sol. St. Ccts. Conf., Feb. 1989. |
"Novel Circuit Techniques for Zero-Power 25-ns CMOS Erasable Programmable Logic Devices (EPLD's)" by Sau-Ching Wong, Hock-Chuen So, Chuan-Yung Hung, and Jung-Hsing Ou, Oct. 1986, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, pp. 766-744. |
"A 90ns 4Mb CMOS EPROM, " by George Canepa, Hernan Castro, Peter Hazen, Sandy Lee, Mark Holer, Sherif Sweha, and R. K. Wallace, IEEE International Solid-State Circuits Conference, Feb. 18, 1988, pp. 120-121, 323. |
"A 16K E.sup.2 PROM Employing New Array Architecture and Designed-In Reliability Features," by Gioria Yaron, S. Jayasimha Prasad, Marsk S. Eble, and Bruce M. K. Leong, Oct. 1982, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, pp. 833-839. |
"16-K EE-PROM Relies on Tunneling for Byte-Eraseable Program Storage," by W. S. Johnson, G. L. Kuhn, A. L. Renninger, and G. Perlegos, Electronics, Feb. 28, 1980, p. 113-117. |
"Reliability Aspects of a Floating Gate E.sup.2 PROM," by Bruce Euzent, Nick Boruta, Jimmy Lee and Ching Jeng (1981), IEEE Proc. IRPS, pp. 11-16. |
"A 19-ns 250 mW CMOS Erasable Programmable Logic Device," by Jagdish Pathak, Hal Kurkowski, Robert Pugh, Ritu Shrivasstave and Frederick B. Jenne, Oct. 1986, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, pp. 775-783. |