This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0001735, filed on Jan. 4, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concept relates to a memory device, and more particularly, to an error correction circuit, a memory system, and an error correction method.
Error correction circuits may perform error correction coding (ECC) to correct error bits in information data.
As the communication speed increases and the data throughput increases, the number of error bits in information data may increase. Due to the increase in error bits, the error correction latency required from when an error correction decoder receives information data until when the error correction decoder outputs correction data may increase.
The inventive concept provides an error correction decoder including an error correction device correcting an error in units of two consecutive symbols, thereby reducing the error correction latency.
According to some embodiments of the inventive concept, there is provided an error correction device including a syndrome generation circuit configured to receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data that are determined by substituting powers of primitive elements of a Galois field into a reception polynomial based on the data. Respective exponents of the powers of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome sequentially increase, and respective exponents of the powers of respective ones of the primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome sequentially increase. The error correction device includes an error location determination circuit configured to determine a coefficient of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine a coefficient of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain locations of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial, an error value determination circuit configured to predetermine values of the errors in units of two consecutive symbols, based on the first syndrome and the second syndrome, and an error correction circuit configured to correct the errors included in the data, based on the locations of the errors and the values of the errors.
According to some embodiments of the inventive concept, there is provided a memory system including a memory device including a plurality of memory cells, and a memory controller configured to correct data that has been read from the memory device. The memory controller includes an error correction device. The error correction device includes a syndrome generation circuit configured to receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data that are determined by substituting powers of primitive elements of a Galois field into a reception polynomial based on the data. Respective exponents of the powers of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome sequentially increase, and respective exponents of the powers of respective ones of the primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome sequentially increase. The memory controller includes an error location determination circuit configured to determine a coefficient of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine a coefficient of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain locations of errors included in the data in units of two consecutive symbols, based on the first error location polynomial and the second error location polynomial The memory controller includes an error value determination circuit configured to predetermine values of the errors in units of two consecutive symbols, based on the first syndrome and the second syndrome, and an error correction circuit configured to correct the errors included in the data, based on the locations of the errors and the values of the errors.
According to some embodiments of the inventive concept, there is provided an error correction method including receiving data and outputting a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data that are determined by substituting powers of primitive elements of a Galois field into a reception polynomial based on the data. Respective exponent of the power of respective ones of the primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome sequentially increases, and exponents of the powers of respective ones of the primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome sequentially increase, determining a coefficient of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determining a coefficient of a second error location polynomial, based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtaining locations of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial, pre-calculating values of errors in units of two consecutive symbols based on the first syndrome and the second syndrome, and correcting the errors included in the data, based on the locations of the errors and the values of the errors.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, various embodiments of the inventive concept will be described with reference to the accompanying drawings.
Referring to
The memory device 20 may include a memory cell array including a plurality of memory cells. The memory cell array may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at points where the word lines and the bit lines cross each other. The memory cells of the memory cell array may be volatile memory cells (e.g., dynamic random access memory (DRAM) cells, static RAM (SRAM) cells, nonvolatile memory cells (e.g., flash memory cells, Resistive RAM (ReRAM) cells, Phase change RAM (PRAM) cells, Magnetic RAM (MRAM) cells, or any other types of memory cells.
In some embodiments, the memory system 1 may be implemented as an embedded or removable memory in an electronic device and, for example, may be implemented in various forms such as an embedded universal flash storage (UFS) memory device, embedded multi-media card (eMMC), solid state drive (SSD), UFS memory card, compact flash (CF) memory, secure digital (SD) memory, Micro Secure Digital (Micro-SD) memory, Mini Secure Digital (Mini-SD) memory, extreme Digital (xD) memory, or memory stick.
The memory controller 10 may control the memory device 20 to read data stored in the memory device 20 or write data to the memory device 20 in response to a write/read request from a host HOST. Specifically, the memory controller 10 may control write, read, and erase operations on the memory device 20 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 20. In addition, the data DATA to be stored in the memory device 20 and the data DATA read from the memory device 20 may be transmitted and received between the memory controller 10 and the memory device 20.
The memory controller 10 may include a decoder 100.
The decoder 100 may perform decoding using an error correction code (hereinafter, referred to as ECC) on data read from the memory device 20. The decoder 100 may perform decoding to correct an error in the read data.
That is, the decoder 100 may correct data read from the memory cell array of the memory device 20.
According to some embodiments, the decoder 100 includes an error correction device that corrects errors in units of two consecutive symbols other than a Reed-Solomon (RS) decoder, thereby reducing the time required for RS decoding. Accordingly, the read latency may be improved.
Referring to
First, when the data DATA is input from the host HOST (see
That is, the encoder 200 may perform RS code encoding on data to generate a codeword of an RS code. In addition, the encoded data (e.g., codewords of a plurality of RS codes) may be written to the memory device 20 as write data WD.
In addition, when a read command is received, the memory system 1 may read data stored in the memory device 20 as read data RD. At this time, the read data RD may include errors E that occurred for various reasons. For example, the errors E may occur due to a malfunction when the write data WD is programmed or a data loss while the write data WD is stored in the memory device 20. According to some embodiments, the errors E may occur due to a malfunction in a read operation of reading the read data RD.
The decoder 100 may perform RS code decoding on the read data RD to eliminate the errors E. Here, the read data RD may be referred to as a read codeword. A decoding result may be output as corrected data DATA′.
Hereinafter, a method, performed by the encoder 200, of generating a codeword encoded with an RS code is described.
The RS code is a non-binary error correction code, and error correction using the RS code may be performed in unit of a symbol rather than in unit of a bit. Here, the symbol may refer to information represented by a predetermined number of bits.
When one symbol is expressed as m bits, the RS code may be defined by GF(2m), which is a Galois field having the size of 2m. The Galois field is a finite field and has a finite number of elements.
In the finite field GF(2m) having a size of 2m, GF(2m)={0, 1, α1, . . . , α2
In addition, 2m symbols, which are all case numbers that m-bits may express, and all 2m elements of GF(2m) may have a one-to-one mapping relationship.
This will be explained assuming the RS code having a total of N symbols. At this time, a decoded RS code may include K data symbols and P parity symbols. The assumed RS code may correct up to P/2 errors. That is, when N=K+P and one symbol is m-bit, the maximum code length of a symbol unit is 2m−1. Here, N, K, and P are positive integers.
Codewords encoded with the RS code may be N-dimensional vectors c0, c1, . . . , cN-1 obtained from coefficients of a code polynomial c(x). Here, the code polynomial c(x) may be an N-order polynomial for x having no constant term, and the codewords encoded in the RS code may be the N dimensional vectors c0, c1, . . . , cN-1 obtained from a code polynomial c(x)=c0x+c1x2+c2x3+ . . . +cN-1xN.
In addition, the code polynomial c(x) may be expressed as the product of an information polynomial m(x) and a generative polynomial g(x). In other words, it may be c(x)=m(x)*g(x)
Here, the information polynomial m(x) may correspond to K data symbols and may be a K-order polynomial for x. In addition, it may be a generative polynomial g(x)=Πi=0P-1(x+αi), and the generative polynomial g(x) may be a P-order polynomial for x.
When x is an element of the Galois field GF(2m), a value of the generating polynomial g(x) may be 0. In addition, when x is a power of α which is the primitive element of the Galois field GF(2m), the value of the generating polynomial g(x) may be 0. That is, in the generative polynomial g(x), it may be g(α0)=0, g(α1)=0 . . . , g(αP-1)=0.
Therefore, because c(x)=m(x)*g(x) and g(α0)=0, g(α1)=0, . . . , g(αP-1)=0, it may be c(α0)=0, c(α1)=0, . . . , c(αP-1)=0.
At this time, powers of a which are P primitive elements may be substituted into x in the code polynomial c(x)=c0X+c1x2+c2x3+ . . . +cN-1xN, and a result of substituting the powers of Q- which are P primitive elements into the code polynomial c(x) may be expressed as a matrix product as shown in Equation 1 below.
Here
may denote the primitive element of the Galois field GF(2m).
In addition,
may be a matrix that defines rules for generating a parity symbol for the RS code including K data symbols and P parity symbols and having a total of N symbols. The matrix may be referred to as an H matrix.
In addition, columns multiplied by 0th to K−1 coefficients c0 to ck-1 of a code polynomial in the H matrix may be defined as HK, columns multiplied by Kth to N−1 coefficients cx to cN-1 of the code polynomial in the H matrix may be defined as HP, a K dimensional vector
may be defined as CK, and a P-dimensional vector
may be defined as CP. At this time, the right side of Equation 1 may be expressed as
In this case, because it is c(α0)=0, c(α1)=0, . . . c(αP-1)=0,
may be satisfied. Therefore, it may be CP=HP−1(HKCK).
That is, the encoder 200 may calculate CK by using K data symbols and may generate a codeword including K data symbols and P parity symbols by using the calculated CK and CP=HP−1(HKCK). Here, the codeword encoded with the RS code may be the N-dimensional vectors c0, c1, . . . , cN-1 obtained from the coefficients of the code polynomial c(x).
Hereinafter, a method of operating a decoder 300, according to some embodiments, is described.
Referring to
The error correction device 310 and the RS code decoder 320 may receive the data RD read from a memory cell array.
The error correction device 310 may determine locations and sizes of errors included in the data RD in units of two consecutive symbols, and correct the errors included in the data RD based on the determined locations and sizes of errors. The error correction device 310 may output the error corrected data DATA′.
That is, the error correction device 310 may determine the locations and sizes of errors in parallel for each of a plurality of groups including two consecutive symbols without overlapping. For example, when the read data RD includes N symbols, the error correction device 310 may determine in parallel locations and sizes of errors included in 0th and first symbols, locations and sizes of errors included in second and third symbols, and locations and sizes of errors included in N−2 and N−1 symbols.
The RS code decoder 320 may determine locations and sizes of all errors included in the data RD, and correct the errors included in the data RD based on the determined locations and sizes of the errors. The RS code decoder 320 may output the error corrected data DATA′.
That is, the RS code decoder 320 may determine the locations and sizes of the errors included in the 0th to N−1 symbols at one time.
Furthermore, in parallel with an error correction operation of the error correction device 310, an error correction operation of the RS code decoder 320 may be performed. That is, the error correction device 310 and the RS code decoder 320 may simultaneously start the error correction operation.
Since the error correction device 310 determines the locations and sizes of errors in parallel for each of the plurality of groups including two consecutive symbols without overlapping, the error correction device 310 may have less operations than the RS code decoder 320 that needs to determine the locations and sizes of all the errors included in the data RD.
Therefore, the error correction operation of the error correction device 310 may be performed faster than the error correction operation of the RS code decoder 320.
When the error correction operation of the error correction device 310 is successful, because the error correction operation of the RS code decoder 320 does not need to be performed, the error correction device 310 may output, to the RS code decoder 320, a signal TERMINATION indicating termination of the error correction operation of the RS code decoder 320.
That is, when the error correction operation of the error correction device 310 is successful, the corrected data DATA′ may be output by the error correction device 310, and when the error correction operation of the error correction device 310 fails, the corrected data DATA′ may be output by the RS code decoder 320.
Before describing the error correction operation of the error correction device 310, the error correction operation of the RS code decoder 320 is described in detail.
This will be explained assuming the RS code having a total of N symbols. At this time, a decoded RS code may include K data symbols and P parity symbols. The assumed RS code may correct up to P/2 errors. That is, when N=K+P and one symbol is m-bit, the maximum code length of a symbol unit is 2m−1. Here, N, K, and P are positive integers.
Referring to
The RS code decoder 400 may receive the read codeword RCW and correct errors included in the read codeword RCW. The RS code decoder 400 may output an error corrected codeword CCW.
Data may be the codeword RCW read from the memory cell array. The read codeword RCW may be N-dimensional vectors R0, R1, . . . , RN-1. Coefficients of a reception polynomial R(x) may be obtained from the N-dimensional vectors R0, R1, . . . , RN-1 of the read codeword RCW. Here, the reception polynomial R(x) may be an N-order polynomial for x and may determine coefficients of a reception polynomial R(x)=R0x+R1x2+R2x3+ . . . +RN-1xN from the N-dimensional vectors R0, R1, . . . , RN-1 of the read codeword RCW.
The error corrected codeword CCW may be the same as the N-dimensional vectors c0, c1, . . . , cN-1 obtained from the coefficients of the code polynomial c(x) described with reference to
Here, the code polynomial c(x) may be an N-order polynomial for x having no constant term, and the error corrected codeword CCW may be the same as the N dimensional vectors c0, c1, . . . , cN-1 obtained from the code polynomial c(x)=c0X+c1x2+c2x3+ . . . +cN-1xN.
In addition, an error polynomial E(x) may be defined as the difference between the receiving polynomial R(x) and the code polynomial c(x). That is, when x is a power of α, which is a primitive element of the Galois field GF(2m), when an error occurs, it may be an error polynomial E(x)=R(x)−c(x), and when there is no error, R(x)=c(x)=0 may be satisfied.
The syndrome generation circuit 410 may receive the read codeword RCW and calculate a plurality of syndromes. The syndrome generation circuit 410 may identify whether an error exists in the read codeword RCW according to values of the calculated syndromes.
For example, values of first to Pth syndromes may be calculated as Equation 2 below.
Here, Sp denotes the value of Pth syndrome and Ct denotes the primitive element of the Galois field GF(2m).
That is, the values of the first to Pth syndromes may be calculated by sequentially substituting P powers of α into x in the reception polynomial R(x)=R0x+R1x2+R2x3+ . . . +RN-1xN. Here, when x is the power of CL, which is the primitive element of the Galois field GF(2m), when an error occurs, it may be an error polynomial E(x)=R(x)−c(x), and when there is no error, may be satisfied.
When all values of the first to P syndromes are 0, no error may be in the read codeword RCW. When all values of the first to Pth syndromes are not 0, an error may be in the read codeword RCW.
When all values of the first to Pth syndromes are 0, the read codeword RCW temporarily stored in the data buffer 450 may be output to the outside of the RS code decoder 400 without a separate error correction.
When all values of the first to Pth syndromes are not 0, the plurality of syndromes may be transmitted to the error location polynomial generation circuit 420.
The error location polynomial generation circuit 420 may generate an error location polynomial Λ(x) used to search for a location of an error included in the read codeword RCW based on the plurality of syndromes.
The error location polynomial generation circuit 420 may be referred to as a key equation solver. The error location polynomial generation circuit 420 may generate the error location polynomial Λ(x) by using a Berlekamp-Massey algorithm, a Peterson-Gorenstein-Zierler (PGZ) algorithm, a Step-By-Step (SBS) algorithm, a Euclidean algorithm, or a modified Euclidean algorithm. The error location may be obtained by taking a reciprocal of the root of the error location polynomial Λ(x). In some embodiments, the error location may be obtained by taking the reciprocal of the root of the error location polynomial Λ(x) by using a chien-search algorithm.
The error location determination circuit 430 may calculate error locations based on the error location polynomial and output flag signals e1, e2, . . . , eN-1 indicating the error locations according to a calculation result. The error location determination circuit 430 may transmit the flag signals e1, e2, . . . , eN-1 indicating the error locations to the error correction circuit 440.
The error correction circuit 440 may correct errors of the read codeword RCW received from the data buffer 450 based on the flag signals e1, e2, . . . , eN-1 indicating the error locations, and output the error corrected codeword CCW.
In some embodiments, the error correction circuit 440 may identify a symbol in which an error has occurred among a plurality of symbols included in the codeword based on the flag signals e1, e2, . . . , eN-1 indicating the error locations and may calculate an error value of the symbol in which the error has occurred by using a Forney algorithm, etc. The error correction circuit 440 may output the error corrected codeword CCW, based on the read codeword RCW provided from the data buffer 450, the error locations, and the error values.
The data buffer 450 may receive the read codeword RCW, temporarily store the read codeword RCW, and provide the read codeword RCW to the error correction circuit 440.
In some embodiments, when the values of the flag signals e1, e2, . . . , eN-1 are all 0, the error correction circuit 440 may output the read codeword RCW received from the data buffer 450 as is without a separate correction.
In some embodiments, when the values of the flag signals e1, e2, . . . , eN-1 are all 0, the error correction circuit 440 may output the read codeword RCW received from the data buffer 450 as it is without a separate correction.
In some embodiments, when the values of the flag signals e1, e2, . . . , eN-1 are not all 0, the error correction circuit 440 may correct errors of the read codeword RCW received from the data buffer 450, based on the error locations and the error values, and output the error corrected codeword CCW.
Referring to
In operation S120, the syndrome generation circuit 410 may calculate the plurality of syndromes for the read codeword RCW. The syndromes may be data indicating whether an error exists in data. When values of all syndromes are 0, no error may be in the data. When the values of all syndromes are not 0, errors may be in the data.
In operation S130, the error location polynomial generation circuit 420 may determine the error location polynomial Λ(x) based on the plurality of syndromes, and the error location determination circuit 430 may obtain error locations. The error locations may be obtained by taking the reciprocal of the root of the error location polynomial Λ(x). The error location determination circuit 430 may output the flag signals e1, e2, . . . , eN-1 indicating the error locations.
In operation S140, the error correction circuit 440 may identify a symbol in which an error has occurred among the plurality of symbols included in the read codeword RCW based on the flag signals e1, e2, . . . , eN-1 indicating the error locations and may calculate an error value of the symbol in which the error has occurred by using the Forney algorithm, etc. The error correction circuit 440 may output the error corrected codeword CCW, based on the read codeword RCW provided from the data buffer 450, the error locations, and the error values.
In addition, the RS code decoder 400 requires the most operations in operation S130 among operations S110 to S140. For example, when the Berlekamp-Massey algorithm is used in operation S130, the RS code decoder 400 performs a predetermined number of repetitive operations (e.g., the number P of parity symbols) regardless of the number of errors that have actually occurred, and the amount of operations performed per repetitive operation is also large. In addition, when the PGZ algorithm is used in operation S130, matrix reverse transformation and matrix multiplication are required, which has high complexity, and this complexity increases the time required for RS decoding.
According to some embodiments, the decoder 300 includes the error correction device 310 (
Hereinafter, an error correction operation of the error correction device 310 is described in detail.
Referring to
The syndrome generation circuit 510 may receive data and output first to sixth syndromes with respect to the data. Here, the first to sixth syndromes may be calculated by substituting powers of the primitive elements α of the Galois field GF(2m) into the reception polynomial R(x) based on the data, an exponent of the power of each of the primitive elements used to calculate the first to third syndromes may sequentially increase, and an exponent of the power of each of the primitive elements used to calculate the fourth to sixth syndromes may sequentially increase. For example, the exponent of the power of each of the primitive elements used to calculate the first to third syndromes may sequentially increase by 1, and the exponent of the power of each of the primitive elements used to calculate the fourth to sixth syndromes may sequentially increase by 1.
In addition, for example, the data may be the codeword RCW read from a memory cell array. The read codeword RCW may be the N-dimensional vectors R0, R1, . . . , RN-1. Coefficients of the reception polynomial R(x) may be obtained from the N-dimensional vectors R0, R1, . . . , RN-1 of the read codeword RCW. Here, the reception polynomial R(x) may be an N-order polynomial for x and may determine coefficients of the reception polynomial R(x)=R0x+R1x2+R2x3+ . . . +RN-1xN from the N-dimensional vectors R0, R1, . . . , RN-1 of the read codeword RCW. The syndrome generation circuit 510 may calculate the syndromes by substituting the powers of the primitive elements α of the Galois field GF(2m) into the reception polynomial R(x)=R0x+R1x2+R2x3+ . . . +RN-1xN in which the coefficients are determined based on the data.
Referring to
For example, when the first syndrome S1 is R(α0), the second syndrome S2 may be R(α1) and the third syndrome S3 may be R(α2). In addition, when the fourth syndrome S2 is R(α1), the fifth syndrome S3 may be R(α2) and the sixth syndrome S4 may be R(α3).
However, the inventive concept is not limited thereto, and unlike
The syndrome generation circuit 510 may provide the calculated syndromes to the error location determination circuit 520 and the error value determination circuit 540. Referring to
The error location determination circuit 520 may determine a coefficient of a first error location polynomial, based on the first syndrome S1, the second syndrome S2, and the third syndrome S3, and determine a coefficient of a second error location polynomial, based on the fourth syndrome S2, the fifth syndrome S3, and the sixth syndrome S4. In addition, the error location determination circuit 520 may obtain locations of errors included in the data in units of two consecutive symbols, based on the first error location polynomial and the second error location polynomial.
A method, performed by the error location determination circuit 520, of obtaining the locations of the errors included in the data in units of two consecutive symbols is described in detail with reference to
The error location determination circuit 520 may include a plurality of sub error location determination circuits. The plurality of sub error location determination circuits may receive first to sixth syndromes, and each of the plurality of sub error location determination circuits may output an error flag signal indicating whether there are errors in two consecutive symbols. Here, each of the plurality of sub error location determination circuits may match two consecutive symbols without overlapping, and each of the plurality of sub error location determination circuits may output an error flag signal indicating whether there are errors in the two matching symbols.
That is, the error location determination circuit 520 may in parallel determine whether there are errors in each of a plurality of groups including two consecutive symbols without overlapping.
Referring to
The first sub error location determination circuit 520-1 may receive a first syndrome Sd, a second syndrome Sd+1, a third syndrome Sd+2, a fourth syndrome Sf, a fifth syndrome Sf+1, and a sixth syndrome Sf+2, and output a 0&1 error flag signal e0,1 indicating whether there are errors in a 0th symbol and a first symbol. The second sub error location determination circuit 520-2 may receive the first syndrome Sd, the second syndrome Sd+1, the third syndrome Sd+2, the fourth syndrome Sf, the fifth syndrome Sf+1, and the sixth syndrome Sf+2 and may output a 2&3 error flag signal e2,3 indicating whether there are errors in a second symbol and a third symbol. The Qth sub error location determination circuit 520-Q may receive the first syndrome Sd, the second syndrome Sd+1, the third syndrome Sd+2, the fourth syndrome Sf, the fifth syndrome Sf+1, and the sixth syndrome Sf+2 and may output an N−2&N−1 error flag signal eN-2,N-1 indicating whether there are errors in an N−2 symbol and an N−1 symbol.
In some embodiments, when errors are in in the two consecutive symbols, each of the sub error location determination circuits may output an error flag signal indicating whether there are errors in the two consecutive symbols such that a value of the error flag signal is 1. When there is no error in the two consecutive symbols, each of the sub error location determination circuits may output an error flag signal indicating whether there are errors in the two consecutive symbols such that a value of the error flag signal is 0.
For example, when there is no error in 0th and first symbols, the first sub error location determination circuit 520-1 may output the 0&1 error flag signal e0,1 indicating 0. In addition, when there are errors in second and third symbols, the second sub error location determination circuit 520-2 may output the 2&3 error flag signal e2,3 indicating 1.
The first to Qth sub error location determination circuits 520-1 to 520-Q may have the same configuration. Therefore, hereinafter, the configuration and operation of the i&i+1 sub error location determination circuit 520-i&i+1 determining whether the i-th symbol and the i+1 symbol include errors shown in
The i&i+1 sub error location determination circuit 520-i&i+1 may receive the first syndrome Sd, the second syndrome Sd+1, the third syndrome Sd+2, the fourth syndrome Sf, the fifth syndrome Sf+1, and the sixth syndrome Sf+2 and may output an i&i+1 error flag signal ei,i+1 indicating whether there are errors in the i-th symbol and the i+1 symbol.
The i&i+1 sub error location determination circuit 520-i&i+1 may include an error location polynomial generation circuit 521 and an error location checker circuit 523.
The error location polynomial generation circuit 521 may receive the first syndrome Sd, the second syndrome Sd+1, the third syndrome Sd+2, the fourth syndrome Sf, the fifth syndrome Sf+1, and the sixth syndrome Sf+2. In addition, the error location polynomial generation circuit 521 may determine a coefficient of a first error location polynomial, based on the first syndrome Sd, the second syndrome Sd+1, and the third syndrome Sd+2. In addition, the error location polynomial generation circuit 521 may determine a coefficient of a second error location polynomial, based on the fourth syndrome Sf, the fifth syndrome Sf+1, and the sixth syndrome Sf+2.
In some embodiments, the error location polynomial generation circuit 521 may determine the coefficient of the first error location polynomial based on Equation 3 below. In addition, the error location polynomial generation circuit 521 may determine the coefficient of the second error location polynomial based on Equation 4 below.
Here, α denotes the primitive element of the Galois field GF(2m), Λ1(αi) denotes the first error location polynomial, Λ2(αi) denotes the second error location polynomial, Sd, Sd+1, Sd+2 respectively denote the first to third syndromes, Sf, Sf+1, and Sf+2 respectively denote the fourth to sixth syndromes, and d and f are positive integers and may be different from each other.
In addition, in some embodiments, the second syndrome may be the same as the fourth syndrome, the third syndrome may be the same as the fifth syndrome, and an exponent of power of each of primitive elements used to calculate the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome may sequentially increase by 1.
At this time, the error location polynomial generation circuit 521 may determine the coefficient of the first error location polynomial based on Equation 5 below. In addition, the error location polynomial generation circuit 521 may determine the coefficient of the second error location polynomial based on Equation 6 below. For example, d may be 1 and f may be 2.
Here, α may denote the primitive element of the Galois field GF(2m), Λ1(αi) may denote the first error location polynomial, Λ2(αi) may denote the second error location polynomial, S1 may denote the first syndrome, S2 may denote the second syndrome, S3 may denote the third syndrome, and S4 may denote the sixth syndrome.
With respect to Equations 5 and 6, it is assumed that errors are included in the i-th symbol and the i+1 symbol, which are consecutive symbols, an error value of the i-th symbol is defined as vi, and an error value of the i+1 symbol is defined as vi+1.
In this case, the first syndrome S1 satisfies S1=R(α0)=c(α0)+E(α0)=vi(α0)′+vi+1(α0)t+1, the second syndrome S2 satisfies S2=R(α1)=c(α1)+E(α1)=vi(α1)′+vi+1(α1)t+1, and the third syndrome S3 satisfies S3=R(α2)=c(α2)+ε(α2)=vi(α2)′+vi+1(α2)t+1. When the error value vi of the i-th symbol and the error value vi+1 of the i+1 symbol are erased using the first syndrome S1, the second syndrome S2, and the third syndrome S3, Λ1(αi)=0 may be derived. Similarly, when the error value vi of the i-th symbol and the error value vi+1 of the i+1 symbol are erased using the second syndrome S2, the third syndrome S3, and the fourth syndrome S4, Λ2(αi)=0 may be derived.
Because Λ1(αi)=0 and Λ2(αi)=0 are quadratic equations for αi, errors may be included in the i-th symbol and the i+1 symbol when there is αi (i.e., a common root) satisfying both Λ1(αi)=0 and Λ2(αi)=0.
The error location polynomial generation circuit 521 may provide the first error location polynomial Λ1(αi) and the second error location polynomial Λ2(αi) to the error location checker circuit 523.
The error location checker circuit 523 may output the i&i+1 error flag signal ei,i+1 indicating whether there are errors in the i-th symbol and the i+lth symbol based on the first error location polynomial Λ1(αi) and the second error location polynomial Λ2(αi).
In some embodiments, the error location checker circuit 523 may output the i&i+1 error flag signal ei,i+1 indicating that “errors are included in the i-th symbol and the i+1 symbol” when there is an exponent i satisfying Λ1(αi)=0 and Λ2(αi)=0. In addition, the error location checker circuit 523 may output the i&i+1 error flag signal ei,i+1 indicating that “there are no errors in the i-th symbol and the i+1 symbol” when there is no exponent i satisfying Λ1(αi)=0 and Λ2(αi)=0.
For example, the error location checker circuit 523 may output the error flag signal ei,i+1 indicating 1 when there is exponent i satisfying Λ1(αi)=0 and Λ2(αi)=0. In addition, the error location checker circuit 523 may output the i&i+1 error flag signal ei,i+1 indicating 0 when there is no exponent i satisfying Λ1(αi)=0 and Λ2(αi)=0.
In some embodiments, the first error location polynomial and the second error location polynomial may be polynomials related to a power αi of the primitive element of the Galois field having the exponent i, and the error location determination circuit 520 may output the i&i+1 error flag signal ei,i+1 indicating that “errors are included in the i-th symbol and the i+1 symbol” when there is the exponent i that determines a value of the first error location polynomial Λ1(αi) and a value of the second error location polynomial Λ2(αi) to be 0.
In some embodiments, in the Galois field GF(28) defined by the primitive polynomial p(x)=1+x2+x3+x4+x8, α+1=α25 may be satisfied. Here, m above may be 8. That is, in the finite element GF(28) having a size of 28, it may be GF(28)={0, 1, α1, . . . , α254}. 256 symbols, which are all case numbers that an 8-bit symbol may express, and all 156 elements of GF(28) may have a one-to-one mapping relationship.
Error location polynomial generation circuits included in the first to Qth sub error location determination circuits 520-1 to 520-Q may have the same configuration. Therefore, hereinafter, the configuration and operation of the error location polynomial generation circuit 521 included in the i&i+1 sub error location determination circuit 520-i&i+1 determining whether the i-th symbol and the i+1 symbol include errors shown in
In this case, the second syndrome may be the same as the fourth syndrome, the third syndrome may be the same as the fifth syndrome, and an exponent of power of each of primitive elements used to calculate the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome may sequentially increase by 1.
Referring to
As described above, because it is α+1=α25, the first error location polynomial may be expressed as Λ1(αi)=S1α2i+1+S2α25+i+S3 and the second error location polynomial may be expressed as Λ2(αi)=S2α2i+1+S3α25+i+S4.
Accordingly, the error location polynomial generation circuit 521 may receive the first syndrome S1, the second syndrome S2, the third syndrome S3, and, as shown in
For example, when i=2, the error location polynomial generation circuit 521 included in the 2&3 sub error location determination circuit corresponding to the second sub error location determination circuit 520-2 shown in
When the value of the first error location polynomial Λ1(α2)=S1α5+S2α27+S3 and the values of Λ1(αi) and the second error location polynomial Λ2(α2)=S2α5+S3α27+S4 are 0, the error location checker circuit 523 may output an error flag signal e2,3 indicating that “there are errors are in the second symbol and the third symbol”.
When the value of the first error location polynomial Λ1(α2)=S1α5+S2α27+S3 and the values of Λ1(αi) and the second error location polynomial Λ2(α2)=S2α5+S3α27+S4 are not 0, the error location checker circuit 523 may output the error flag signal e2,3 indicating that “there are errors in the second symbol and the third symbol”.
Referring back to
That is, the error location determination circuit 520 may output an error flag signal indicating whether two consecutive symbols include errors, and the error location determination circuit 520 may output an error flag signal for each of a plurality of groups including two consecutive symbols without overlapping.
Referring to
The adjacent two-symbol error check circuit 530 may receive a plurality of error flag signals and check whether errors have occurred in two actually consecutive symbols.
When errors occur in two actually consecutive symbols, only one of the 0&1 to N−2&N−1 error flag signals e0,1˜eN-2,N-1 needs to indicate 1, and the remaining error flag signals need to indicate 0.
That is, when all error flag signals indicate 0, it may correspond to a case where the error location determination circuit 520 may not find location of the errors. When errors are included in the data but do not occur in two consecutive symbols, all error flag signals may have 0.
When the 0&1 to N−2&N−1 error flag signals e0,1˜eN-2,N-1 all indicate 0, the adjacent two-symbol error check circuit 530 may output a fail signal FAIL to the error correction circuit 550 and the re-syndrome generation circuit 560 to terminate a decoding operation. At this time, the error correction circuit 550 and the re-syndrome generation circuit 560 may terminate the decoding operation in response to the fail signal FAIL.
The error value determination circuit 540 may pre-calculate values of errors that data may have in units of two consecutive symbols based on two syndromes. In addition, the error value determination circuit 540 may provide the pre-calculated values of errors to the error correction circuit 550.
Referring to
A method, performed by the error value determination circuit 540, of pre-calculating values of errors that data may have in units of two consecutive symbols will be described in detail with reference to
The error value determination circuit 540 may include a plurality of sub error value determination circuits. The error value determination circuit 540 may output two error values in units of two consecutive symbols by using two syndromes under the assumption that errors are included in consecutive symbols.
Each of the plurality of sub error value determination circuits may receive a first syndrome and a second syndrome, and may output two error value signals indicating error values for two consecutive symbols. Here, each of the plurality of sub error value determination circuits may match two consecutive symbols without overlapping, and may output two error value signals indicating error values for the two matching symbols.
That is, the error value determination circuit 540 may determine values of errors in parallel assuming that an error has occurred for each of a plurality of groups including two consecutive symbols without overlapping.
Referring to
The first sub error value determination circuit 540-1 may receive the first syndrome S1 and the second syndrome S2, and output a 0th error value signal V0 indicating the magnitude of an error for a 0th symbol and a first error value signal V1 indicating the magnitude of an error for a first symbol. The second sub error value determination circuit 540-2 may receive the first syndrome S1 and the second syndrome S2, and output a second error value signal V2 indicating the magnitude of an error for a second symbol, and a third error value signal indicating the magnitude of an error for a third symbol. The Qth sub error value determination circuit 540-Q may receive the first syndrome S1 and the second syndrome S2, and output an N−2 error value signal VN-2 indicating the magnitude of an error for an N−2 symbol and an N−1 error value signal VN-1 indicating the magnitude of an error for an N−1 symbol.
An i/2+1 sub error value determination circuit outputting an i+1th error value signal vi indicating the magnitude of an error for an i+1 symbol and an i+1 error value signal vi+1 indicating the magnitude of an error for an i+1 symbol will be described. Here, i may be one of 0, 2, . . . , and/or N−2. For convenience, the i/2+1 sub error value determination circuit is referred to as an i&i+1 sub error value determination circuit 540-i&i+1.
It is assumed that errors are included in the i-th symbol and the i+1 symbol, which are consecutive symbols, an error value of the i-th symbol is defined as vi, and an error value of the i+1 symbol is defined as vi+1.
When the first syndrome S1 and the second syndrome S2 are calculated by substituting α0 and α1 with x in the reception polynomial R(x)=R0x+R1x2+R2x3+ . . . +RN-1xN, Equation 7 below is satisfied.
Here, α denotes the primitive element of the Galois field GF(2m), S1 denotes the first syndrome, S2 denotes the second syndrome, vi denotes the error value of the i-th symbol, and vi+1 denotes the error value of the i+1 symbol.
That is, because the first syndrome S1 satisfies S1=R(α0)=c(α0)+E(α0), the sum of a code polynomial and an error polynomial satisfies c(α0)+E(α0)=(c0α0+c1(α0)2+c2(α0)3+ . . . +cn-t(α0)+vi(α0)+vi+1(α0)i+1, and a right curly bracket term satisfies 0, Equation 7 may be derived. Similarly, because the second syndrome S2 satisfies S2=R(α1)=c(α1)+E(α1) the sum of the code polynomial and the error polynomial satisfies c(α1)+E(α1)=(c0α1+c1(α1)2+c2(α1)3+ . . . +cn-t(α1)+vi(α1)+vi+1(α1)i+1, and the right curly bracket term satisfies 0, Equation 7 may be derived.
The error value vi of the i-th symbol and the error value vi+1 of the i+1 symbol of Equation 7 may be summarized as in Equation 8 below.
Here, α denotes the primitive element of the Galois field GF(2m), S1 denotes the first syndrome, S2 denotes the second syndrome, vi denotes the error value of the i-th symbol, and vi+1 denotes the error value of the i+1 symbol.
That is, the i&i+1 sub error value determination circuit 540-i&i+1 may output the i-th error value signal vi indicating the magnitude of the error for the i-th symbol and the i+1th error value signal Vi+1 indicating the magnitude of the error for the i+1 symbol based on the first syndrome S1, the second syndrome S2, and Equation 8 described above.
Referring to
The i&i+1 sub error value determination circuit 540-i&i+1 may receive the first syndrome Si and the second syndrome S2, and output the i+1 error value signal vi indicating the magnitude of the error for the i-th symbol and the i+1th error value signal vi+1 indicating the magnitude of the error for the i+1 symbol by using the first, second, third, and fourth multipliers 71-1, 71-2, 71-3, and 71-4 and the first and second adders 73-1 and 73-2, as shown in
For example, when i=2, the 2&3 sub error location determination circuit corresponding to the second sub error value determination circuit 540-2 shown in
and a second error value signal V3 for the second symbol indicating
Referring back to
Referring to
In some embodiments, the error correction circuit 550 may correct the errors included in the data based on the locations of the errors and the values of the errors as shown in Equation 9 below.
Here, Ric denotes the i-th symbol of the error-corrected codeword CCW, Ri+1c denotes the i+1 symbol of the error-corrected codeword CCW, Ri denotes the i-th symbol of the read codeword RCW, Ri+1 denotes the i+1 symbol of the read codeword RCW, ei,i+1 denotes the i&i+1 error flag signal, vi denotes the error value of the i-th symbol, and vi+1 denotes the error value of the i+1 symbol.
That is, the error correction circuit 550 may correct the i-th symbol and the i+1 symbol of the read codeword RCW according to the value of the i&i+1 error flag signal ei,i+1.
When the value of the i&i+1 error flag signal ei,i+1 is 0, the error correction circuit 550 may output the i-th symbol and i+1 symbol of the read codeword RCW as the i-th symbol and the i+1 symbol of the error-corrected codeword CCW without correction.
When the value of the i&i+1 error flag signal ei,i+1 is 1, by adding the error value vi of the i-th symbol to the i-th symbol of the read codeword RCW and adding the error value vi+1 of the i+1 symbol to the i+1 symbol of the read codeword RCW, the error correction circuit 550 may output the i-th symbol and the i+1 symbol of the error-corrected codeword CCW.
The error correction circuit 550 may output an error-corrected codeword CCW based on the 0&1 to N−2&N−1 error flag signals e0,1˜eN-2,N-1, the 0th to N−1 error value signals v0˜VN-1, and the read codeword RCW.
Here, the data buffer 570 may receive the read codeword RCW, temporarily store the read codeword RCW, and provide the read codeword RCW to the error correction circuit 550.
That is, the error correction circuit 550 may correct the error of the read codeword RCW received from the data buffer 570 based on the 0&1 to N−2&N−1 error flag signals e0,1˜eN-2,N-1 and the 0th to N−1 error value signal V0˜VN-1, and output the error-corrected codeword CCW.
The error correction circuit 550 may provide the error-corrected codeword CCW to the re-syndrome generation circuit 560.
The re-syndrome generation circuit 560 may receive the error-corrected codeword CCW and re-calculate syndromes for the error-corrected codeword CCW to determine whether the error correction operation is successful. The syndromes may be re-calculated using Equation 2 described above. For example, when the syndromes are S1=S2= . . . =SP=0, the re-syndrome generation circuit 560 may determine that the error correction operation is successful.
When the error correction operation is successful, the re-syndrome generation circuit 560 may output the error-corrected codeword CCW to the outside. In addition, the re-syndrome generation circuit 560 may output, to the RS code decoder 320 (
Referring to
In addition, the first to sixth syndromes may be calculated by substituting powers of the primitive elements Q of the Galois field GF(2m) into the reception polynomial R(x) based on the data, an exponent of the power of each of the primitive elements used to calculate the first to third syndromes may sequentially increase, and an exponent of the power of each of the primitive elements used to calculate the fourth to sixth syndromes may sequentially increase. For example, the exponent of the power of each of the primitive elements used to calculate the first to third syndromes may sequentially increase by 1, and the exponent of the power of each of the primitive elements used to calculate the fourth to sixth syndromes may sequentially increase by 1.
Operations S220 and S230 may simultaneously start, and are not limited to the precedence relationship shown in
In operation S220, the error correction device 310 may determine a coefficient of a first error location polynomial based on the first to third syndromes, may determine a coefficient of a second error location polynomial based on the fourth to sixth syndromes, and may obtain locations of errors included in data in units of two consecutive symbols, based on the first error location polynomial and the second error location polynomial.
In operation S230, the error correction device 310 may pre-calculate values of errors that the data may have in units of two consecutive symbols, based on the first syndrome and the second syndrome.
In operation S240, the error correction device 310 may correct the errors included in the data based on the locations of the errors and the values of the errors.
In operation S250, the error correction device 310 may re-calculate a plurality of syndromes for the error-corrected data to determine whether an error correction operation is successful, and when the error correction operation is successful, may output the signal TERMINATION indicating termination of the error correction operation of the RS code decoder 320.
Referring to
Unlike the error correction device 310 and the RS code decoder 320 described with reference to
That is, when the error correction operation of the error correction device 610 fails, the error correction operation of the RS code decoder 620 may start.
Referring to
That is, when the error correction operation of the error correction device 610 is successful, the corrected data DATA′ may be output by the error correction device 610, and when the error correction operation of the error correction device 610 fails, the corrected data DATA′ may be output by the RS code decoder 620.
Referring to
The syndrome generation circuit 710, the error location determination circuit 720, the adjacent two-symbol error check circuit 730, the error value determination circuit 740, the error correction circuit 750, and the data buffer 770 described with reference to
That is, operations of the re-syndrome generation circuit 560 shown in
The re-syndrome generation circuit 760 may receive the error-corrected codeword CCW and re-calculate syndromes for the error-corrected codeword CCW to determine whether an error correction operation is successful. The syndromes may be re-calculated using Equation 2 described above. For example, when the syndromes are S1=S2= . . . =SP=0, the re-syndrome generation circuit 760 may determine that the error correction operation is successful. When the syndromes are not S1=S2= . . . =SP=0, the re-syndrome generation circuit 760 may determine that the error correction operation fails. In addition, when the re-syndrome generation circuit 760 receives the fail signal FAIL of the adjacent two-symbol error check circuit 730, the re-syndrome generation circuit 760 may determine that the error correction operation fails.
When the error correction operation is successful, the re-syndrome generation circuit 560 may output the error-corrected codeword CCW to the outside.
When the error correction operation fails, the re-syndrome generation circuit 560 may output, to the RS code decoder 620 (
Referring to
Operations S320 and S330 may simultaneously start, and are not limited to the precedence relationship shown in
In operation S320, the error correction device 610 may determine a coefficient of a first error location polynomial based on the first to third syndromes, may determine a coefficient of a second error location polynomial based on the fourth to sixth syndromes, and may obtain locations of errors included in data in units of two consecutive symbols, based on the first error location polynomial and the second error location polynomial.
In operation 5330, the error correction device 610 may pre-calculate values of errors that the data may have in units of two consecutive symbols, based on the first syndrome and the second syndrome.
In operation 5340, the error correction device 610 may correct the errors included in the data based on the locations of the errors and the values of the errors.
In operation 5350, the error correction device 610 may re-calculate a plurality of syndromes for the error-corrected data to determine whether an error correction operation is successful, and, when the error correction operation is successful, may output the signal START indicating the start of the error correction operation of the RS code decoder 620.
Here, the RS code decoder 620 may start the error correction operation in response to the signal START instructing the start of the error correction operation.
Referring to
The memory cell array may include first, second, third, and fourth bank arrays 980a, 980b, 980c, and 980d. The row decoder may include first, second, third, and fourth bank row decoders 960a, 960b, 960c, and 960d respectively connected to the first, second, third, and fourth bank arrays 980a, 980b, 980c, and 980d. The column decoder may include first, second, third, and fourth bank column decoders 970a, 970b, 970c, and 970d respectively connected to the first, second, third, and fourth bank arrays 980a, 980b, 980c, and 980d. The sense amplification unit may include first, second, third, and fourth bank sense amplifiers 985a, 985b, 985c, and 985d respectively connected to the first, second, third, and fourth bank arrays 980a, 980b, 980c, and 985d. The first, second, third, and fourth bank arrays 980a, 980b, 980c, and 980d, the first, second, third, and fourth bank row decoders 960a, 960b, 960c, and 960d, the first, second, third, and fourth bank column decoders 970a, 970b, 970c, and 970d, and the first, second, third, and fourth bank sense amplifiers 985a, 985b, 985c, and 985d may respectively constitute first, second, third, and fourth banks. An example of the memory device 900 including four banks is shown in
In addition, according to some embodiments, the memory device 900 may be dynamic random access memory (DRAM) such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR) SDRAM, or Rambus Dynamic Random Access Memory (RDRAM) or any volatile memory device that requires a refresh operation.
The control logic 910 may control operations of the memory device 900. For example, the control logic 910 may generate control signals for the memory device 900 to perform a write operation or a read operation. The control logic 910 may include a command decoder 911 decoding a command CMD received from a memory controller and a mode register 912 setting an operation mode of the memory device 900. For example, the command decoder 911 may decode a write enable signal/WE, a row address strobe signal/RAS, a column address strobe signal/CAS, and a chip selection signal/CS to generate control signals corresponding to the command CMD.
The control logic 910 may further receive a clock CLK and a clock enable signal CKE for driving the memory device 900 in a synchronous manner. The control logic 910 may control the refresh address generator 915 to perform an auto refresh operation in response to a refresh command, or control the refresh address generator 915 to perform a self-refresh operation in response to a self-refresh entry command.
The refresh address generator 915 may generate a refresh address REF_ADDR corresponding to a memory cell row in which the refresh operation is to be performed. The refresh address generator 915 may generate a refresh address REF_ADDR at a refresh rate of a period longer than a refresh period defined in the standard or conventional parameters of the memory device 900. Accordingly, refresh current and refresh power of the memory device 900 may be reduced.
The address buffer 920 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller. In addition, the address buffer 920 may provide the received bank address BANK_ADDR to the bank control logic 930, provide the received row address ROW_ADDR to the row address multiplexer 940, and provide the received column address COL_ADDR to the column address latch 950.
The bank control logic 930 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address BANK_ADDR among the first, second, third, and fourth bank row decoders 960a, 960b, 960c, and 960d may be activated, and a bank column decoder corresponding to the bank address BANK_ADDR among the first, second, third, and fourth bank column decoders 970a, 970b, 970c, and 970d may be activated.
The bank control logic 930 may generate bank group control signals in response to the bank address BANK_ADDR determining a bank group. In response to the bank group control signals, row decoders of a bank group corresponding to the bank address BANK_ADDR among the first, second, third, and fourth bank row decoders 960a, 960b, 960c, and 960d may be activated, and column decoders of a bank group corresponding to the bank address BANK_ADDR among the first, second, third, and fourth bank column decoders 970a, 970b, 970c, and 970d may be activated.
The row address multiplexer 940 may receive the row address ROW_ADDR from the address buffer 920 and the refresh row address REF_ADDR from the refresh address generator 915. The row address multiplexer 940 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR. The row address ROW_ADDR output from the row address multiplexer 940 may be applied to each of the first, second, third, and fourth bank row decoders 960a, 960b, 960c, and 960d.
The bank row decoder activated by the bank control logic 930 among the first, second, third, and fourth bank row decoders 960a, 960b, 960c, and 960d may decode the row address ROW_ADDR output from the row address multiplexer 940 to activate a word line corresponding to the row address ROW_ADDR. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address ROW_ADDR.
The column address latch 950 may receive the column address COL_ADDR from the address buffer 920 and temporarily store the received column address COL_ADDR. The column address latch 950 may gradually increase the column address COL_ADDR received in a burst mode. The column address latch 950 may apply the temporarily stored or gradually increased column address COL_ADDR to each of the first to fourth bank column decoders 970a, 970b, 970c, and 970d.
The bank column decoder activated by the bank control logic 930 among the first to fourth bank column decoders 970a, 970b, 970c, and 970d may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input/output gating circuit 990.
The input/output gating circuit 990 may include an input data mask logic, read data latches storing data output from the first, second, third, and fourth bank arrays 980a, 980b, 980c, and 980d, and a write driver writing data to the first, second, third, and fourth bank arrays 980a, 980b, 980c, and 980d, along with circuits gating input/output data.
Data DQ to be read from one of the first to fourth bank arrays 980a, 980b, 980c, and 980d may be sensed and amplified by the sense amplifier and stored in the read data latches. The data DQ stored in the read data latches may be provided to the memory controller through the data input/output buffer 995. The data DQ to be written in one of the first to fourth bank arrays 980a, 980b, 980c, and 980d may be provided from the memory controller to the data input/output buffer 995. The data DQ provided to the data input/output buffer 995 may be written to one bank array through the write driver.
The ECC engine 1000 may correspond to the decoders 100, 300, and 600 shown in
In addition,
Referring to
Referring to
The main processor 2100 may control the overall operations of the system 2000, more specifically, operations of other components included in the system 2000. The main processor 2100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.
The main processor 2100 may include one or more CPU cores 2110, and may further include a controller 2120 for controlling the memories 2200a and 2200b and/or the storage devices 2300a and 2300b. According to some embodiments, the main processor 2100 may further include an accelerator 2130, which is a dedicated circuit for high-speed data operation such as an artificial intelligence (AI) data operation. Such an accelerator 2130 may include a graphics processing unit (GPU), a natural processing unit (NPU), and/or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other components of the main processor 2100.
The memories 2200a and 2200b may be used as main memory devices of the system 2000, may include volatile memories such as SRAM and/or DRAM, but may include nonvolatile memories such as flash memory, PRAM and/or RRAM. The memories 2200a and 2200b may be implemented in the same package as the main processor 2100.
The storage devices 2300a and 2300b may function as nonvolatile storage devices that store data regardless of whether power is supplied, and may have a relatively large storage capacity compared to the memories 2200a and 2200b. The storage devices 2300a and 2300b may include storage controllers 2310a and 2310b and nonvolatile memories (NVMs) 2320a and 2320b that store data by the control of the storage controllers 2310a and 2310b. The NVMs 2320a and 2320b may each include flash memory of a 2-dimensional (2D) structure or a 3-dimensional (3D) vertical NAND (V-NAND) structure, but may include other types of NVMs such as PRAM and/or RRAM.
The storage devices 2300a and 2300b may be included in the system 2000 while being physically separated from the main processor 2100, or may be implemented in the same package as the main processor 2100. In addition, the storage devices 2300a and 2300b may have a form such as a solid state device (SSD) or a memory card so as to be detachably combined with other components of the system 2000 through an interface such as the connecting interface 2480 to be described below. Such storage devices 2300a and 2300b may be devices to which standard conventions such as universal flash storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) are applied, but are not limited thereto.
The image capturing device 2410 may capture a still image or a moving image, and may be a camera, a camcorder, and/or a webcam.
The user input device 2420 may receive various types of data input from a user of the system 2000, and may be a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.
The sensor 2430 may detect various types of physical quantities that may be obtained from the outside of the system 2000, and convert the detected physical quantities into electrical signals.
The sensor 2430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a location sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.
The communication device 2440 may transmit and receive signals with other devices outside the system 2000 according to various communication protocols. The communication device 2440 may be implemented by including an antenna, a transceiver, and/or a modem (MODEM).
The display 2450 and the speaker 2460 may function as output devices that respectively output visual information and auditory information to the user of the system 2000.
The power supplying device 2470 may appropriately convert power supplied from a battery (not shown) and/or an external power source embedded in or connected to the system 2000 and supply the power to each of the components of the system 2000.
The connecting interface 2480 may provide a connection between the system 2000 and an external device connected to the system 2000 and capable of transmitting and receiving data to and from the system 2000. The connecting interface 2480 may be implemented in various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), eMMC, UFS, embedded UFS (eUFS), and compact flash (CF) card interfaces.
Referring to
While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Number | Date | Country | Kind |
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10-2024-0001735 | Jan 2024 | KR | national |