Error correction code decoder

Abstract

An ECC decoder for correcting a coded signal received, which includes a syndrome calculation and errata evaluation device to receive a code word of the coded signal for performing a syndrome calculation to thereby output a syndrome polynomial, and to receive an erasure and errata evaluator polynomial and an errata position for performing an errata evaluation to thereby output an errata and erasure value and correct the coded signal; a key equation solving device to receive the syndrome for generating an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; and an errata position search device to receive the erasure and errata locator polynomial for searching and outputting the errata position. Evaluating the errata and erasure value and calculating the syndrome are performed in pipeline, thereby sharing the hardware and relatively reducing the hardware cost.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional decoder capable of processing erasure and errata correction in parallel;

FIG. 2 is a block diagram of a conventional syndrome calculation device;

FIG. 3 is a block diagram of a conventional key equation solving device;

FIG. 4 is a block diagram of an ECC decoder in accordance with the invention;

FIG. 5 is a block diagram of a syndrome calculation and errata evaluation device in accordance with the invention;

FIG. 6 is a block diagram of a multiplier-accumulator in accordance with the invention;

FIG. 7 is a schematic view of applying an ECC decoder in a CD player in accordance with the invention;

FIG. 8 is a schematic view of applying a typical CD player for decoding;

FIG. 9 is a schematic view of applying a CD player containing an ECC decoder for decoding in accordance with the invention;

FIG. 10 is a schematic view of applying an ECC decoder in a DVD player in accordance with the invention;

FIG. 11 is a diagram of an ECC data block in a DVD player in accordance with the invention;

FIG. 12 is a schematic diagram of applying a typical DVD player for decoding; and

FIG. 13 is a schematic diagram of applying a DVD player containing an ECC decoder for decoding in accordance with the invention.

Claims

1. An error correction code decoder, which uses a data channel to receive a coded signal obtained by channel coding, the coded signal containing redundancy information for correction, the decoder comprising: a syndrome calculation and errata evaluation device, which receives a code word of the coded signal to thereby output a syndrome polynomial according to a syndrome calculation, and receives an erasure and errata evaluator polynomial and an errata position to output an errata and erasure value according to an errata evaluation in order to correct the code word of the coded signal;a key equation solving device, which receives the syndrome polynomial, and generates an erasure and errata locator polynomial and the erasure and errata evaluator polynomial; andan errata position search device, which receives the erasure and errata locator polynomial, and uses a trial-and-error process to output the errata position.

2. The decoder as claimed in claim 1, further comprising a syndrome modification device, which modifies the syndrome polynomial for the key equation solving device to generate the erasure and errata locator polynomial and the erasure and errata evaluator polynomial.

3. The decoder as claimed in claim 2, wherein the error correction code decoder is implemented to be a decoding configuration having a first pipeline and a second pipeline.

4. The decoder as claimed in claim 3, wherein the syndrome calculation and errata evaluation device and the errata position search device are operated in the first pipeline to calculate a syndrome, search an errata and erasure position, and evaluate an errata and erasure value.

5. The decoder as claimed in claim 4, wherein the key equation solving device is operated in the second pipeline to modify the syndrome and solve a key equation.

6. The decoder as claimed in claim 1, wherein the trial-and-error process is a Chein search.

7. The decoder as claimed in claim 1, wherein the data channel is a wireless channel.

8. The decoder as claimed in claim 1, wherein the data channel is a wired channel.

9. The decoder as claimed in claim 1, wherein the coded signal is a cyclic code.

10. The decoder as claimed in claim 9, wherein the cyclic code is a BCH code.

11. The decoder as claimed in claim 9, wherein the cyclic code is a Reed-Solomon code.