The present invention relates to forward error correction (FEC), and more particularly to FEC using a Reed-Solomon decoder.
Many communications systems perform forward error correction (FEC) to improve data transmission accuracy and to ensure data integrity. FEC helps reduce bit error rates (BER) in applications such as data storage, digital video broadcasts, and wireless communications. Reed-Solomon (RS) error-correcting codes are commonly used for FEC.
Referring now to
Referring now to
In step 28, the RS decoder finds error locations. For example, Chien's search algorithm, which will be described below, can be used. In step 30, error values are found. For example, Forney's algorithm, which will be described below, is often used to find the error values. Steps 24 and 28 may be performed in parallel in hardware implementations.
Referring now to
In “High-speed Decoding of BCH Codes Using a New Error-Evaluation Algorithm,” T. Horiguchi, Electronics and Comm. in Japan, vol. 72, no. 12, (1989), an error evaluator for RS codes is computed during the BMA iterations. In “On the Determination of Error Values For Codes From a Class of Maximal Curves”, R. Koetter, Proc. 35th Annual Allerton Conference on Communications, Control and Computing, Univ. of Illinois at Urbana-Champaign (1997), an error evaluator for algebraic geometry codes is disclosed. The error evaluator in Koetter reduces to the error evaluator in, Horiguchi for RS codes.
The error evaluators in Horiguchi and Koetter require the BMA to be formulated in a manner that cannot be implemented in hardware easily. Berlekamp's formulation of the BMA has a more regular structure and can be readily implemented in hardware. A variation of the error evaluator for Berlekamp's formulation of the BMA is also disclosed in “On Decoding Reed-Solomon Codes up to and beyond the Packing Radii”, W. Feng, Ph. D. dissertation, Univ. of Illinois at Urbana-Champaign (1999).
A typical BMA employs a Galois field inverter, which computes a multiplicative inverse of Galois field elements. An inversionless (or division-free) BMA (iBMA) eliminates the Galois field inverter. One advantage of iBMA is the reduced delay of a critical path of a VLSI implementation.
RS codes operate on finite fields (GF(2m)). GF(q) is a Galois field with q elements. c=(cO, c1, . . . , cn−1) is a vector of length n over GF(q) where n=q−1. The Fourier transform of the vector c is C=(C0, C1, . . . , Cn−1), where
and α is a primitive element of GF(q). A t-error-correcting RS code is the collection of all vectors c with a Fourier transform satisfying Cm
A vector c=(c0, c1, . . . , cn−1) can also be represented as a polynomial
The Fourier transform is a polynomial evaluation at x=α0,α1, . . . ,αn−1. In other words, Cj=c(αj). A t-error-correcting RS code is the collection of all vectors c such that c(αm
g(x)=(x−αm
The polynomial g(x) is a generator polynomial of the Reed-Solomon code.
v=c+e is the received vector where e=(e0, e1, . . . , en−1) is the error vector and ei≠0 when there is an error at the ith position. The codeword c and the error vector e are not known. The received vector v and the Fourier transform of c satisfy Cm
Vi=Ci+Ei for i=0, 1, . . . , n−1.
Because Ci=0 for i=m0, m0+1, . . . , m0+2t−1, it follows that:
Ei=Vi for i=m0, m0+1, . . . , m0+2t−1.
Therefore, the decoder can compute Ei from the received vector for i=m0, . . . , m0+2t−1. Ei are denoted as Si=El+m
The RS decoder computes e from the 2t syndromes. The task can be divided into two parts. First, the error locations are found. In other words, the decoder finds all i such that ei≠0. Second, the error values ei are found for all of the error locations. Then, c can be recovered by subtracting e from v.
The RS decoder finds the error locator polynomial, which is defined as a polynomial Λ(x) satisfying:
Λ(0)=1; and Λ(α−1)=0 if and only if ei≠0.
The error locations are obtained by finding the zeros of Λ(x). To determine the error values, a decoder usually computes the error evaluator polynomial, which is given by Γ(x)=Λ(x)S(x) mod x2t where
is syndrome polynomial.
If there are at most t errors, the error values can be determined (as set forth in G. D. Forney, Jr., “On Decoding BCH Codes”, IEEE Trans. Inform. Theory, vol. 11, pp. 547–557 (1965), which is hereby incorporated by reference):
where Λ′(x) is the formal derivative of Λ(x). This formula is known as the Forney algorithm.
In a first decoding step, assuming the received vector is fed into the decoder symbol by symbol, Homer's rule can be used to reduce complexity. In other words, Ej is evaluated as
Ej=( . . . ((vn−1αjvn−2)αj)+ . . . +v1)αj+v0.
Note that αn=1 and that only Sj=Em
In a third decoding step, two approaches are generally used for computing the error evaluator polynomial if the BMA is used. A first approach computes the error evaluator polynomial simultaneously with the error locator polynomial using an iteration algorithm similar to the BMA. For example, see E. R. Berlekamp, Algebraic Coding Theory, New York, McGraw-Hill (1968). The cost of implementing this approach is high. A second approach computes the error evaluator polynomial after computing the error locator polynomial. The second approach is less complex than the first approach. However, decoding latency of the second approach is higher than the first approach.
In a fourth decoding step, Λ(x) and Γ(x) are known. The error values are determined using Forney's algorithm. Chien's search, which is used to find the zeros of the error locator polynomial Λ(x), is typically performed in parallel with the error evaluation in hardware implementations.
When using the BMA, a linear-feedback shift register (Λ, L) with length L and coefficients Λ0=1, Λ1, . . . , ΛL produces the sequence S0, S1, S3, . . . if:
If (Λ, L) produces S0, . . . , Sr−1 but does not produce S0, . . . , Sr−1, Sr, then (Λ,L) has a discrepancy Δr at Sr, where
is the feedback polynomial. Note that the degree of Λ(x) is less than or equal to L because ΛL might be zero.
The BMA finds the shortest linear feedback shift register that produces a given sequence. If the number of errors is less than or equal to t, the error locator polynomial is the polynomial of lowest degree that produces the syndrome sequence S0, S1, . . . , S2t−1. If the number of errors is more than t, the BMA still finds the polynomial of lowest degree that generates the syndrome sequence. However, this polynomial is usually not a locator polynomial and the decoding algorithm fails.
Referring now to
is computed in step 60.
If Δ=0 in step 62, then p←p+1 in step 64 and control continues with step 68. Otherwise, if Δ≠0 and 2L>r as determined in step 70, then Λ(x)←Λ(x)−ΔΔB−1 xp B(x) in step 72 and control continues with step 64. If Δ≠0 and 2L≦r as determined in step 76, then T(x)←Λ(x), Λ(x)←Λ(x)−ΔΔB−1xpB(x), B(x)←T(x), a←r−2L, ΔB←Δ, L←r+1−L, and p←1 in step 80. Control continues from steps 64, 76 and 80 with step 68 where r←r+1. Control continues from step 68 to step 54 until control ends in step 58. The parameter a in this algorithm is not disclosed in Massey. Parameter a was introduced by Horiguchi and is used for error evaluation.
u≦t is the number of errors. Xl=αi
{circumflex over (B)}(x)=ΔB−1xαB(x).
The error values are given by Horiguchi as follows:
The structure of this formulation is not easily implemented in register-based VLSI in which the coefficients of Λ(x) and B(x) are stored in registers. When updating the polynomial Λ(x) in steps 76 and 80, the relationship between the coefficients of Λ(x) and B(x) depends on the variable p. In other words, Λi=Λi−ΔΔB−1Bi−p, where p could be 1, or 2, or 3, . . . x. This means that the circuit connections are not fixed. While multiplexers can be used to avoid this problem, this approach is not sufficiently cost effective.
Referring now to
The syndrome sequence S0, S1, . . . , S2t−1 and t are used as inputs. In step 100, initialization of variables is performed (Λ(x)←1, B(x)←1, r←0, L←0). In step 104, if r=2t, control ends in step 108. Otherwise, the discrepancy
is computed in step 110. If Δ≠0 and 2L≦r in step 112, then δ←1, L←r+1−L in step 114. Otherwise, δ←0 in step 116. In step 120, the polynomials are updated as follows:
In step 124, r←r+1 and control continues with step 104.
At each clock cycle, the register bank for B(x) either shifts right Bi←Bi−1 corresponding to B(x)←xB(x), or parallel loads Bi←Δ−1Λi corresponding to B(x)←Δ−1Λ(x). The register bank for Λ(x) is updated by Λi←Λi−ΔBi−1. Note that this algorithm does not provide an error evaluator. In W. Feng, “On Decoding Reed-Solomon Codes Up to and Beyond the Packing Radii”, Reading, Ph.D. dissentation, Univ. of IL at Urbana-Champaign (1999), which is hereby incorporated by reference, an error evaluator for this BMA formulation was derived as follows:
or equivalently
where B(2t)(x) is the scratch polynomial at the end of 2t iterations of the algorithm shown in
Referring now to
is computed. If Δ≠0 as determined in step 142, Λ(x)←ΔBΛ(x)+ΔxB(x) in step 144. Otherwise, Λ(x)←Λ(x) in step 146. If Δ≠0 and 2 L≦r as determined in step 146, B(x)←Λ(x), L←r+1−L and ΔB←Δ in step 148. Otherwise, B(x)←xB(x) in step 150. In step 154, r←r+1. Control continues from step 154 to step 134.
Note that the Λ(x) produced by the algorithm in
As can be appreciated from the forgoing, the steps performed by RS decoders can be complex and can involve a large number of calculations. Reducing the number of calculations and increasing the speed of RS decoding would be desirable.
An error correcting Reed-Solomon decoder according to the present invention includes a syndrome calculator that calculates syndrome values. An error locator polynomial generator communicates with the syndrome calculator and generates an error locator polynomial. An error location finder communicates with at least one of the syndrome calculator and the error locator polynomial generator and generates error locations. An error values finder communicates with at least one of the syndrome calculator, the error location finder and the error locator polynomial generator and generates error values without calculating an error evaluator polynomial.
In other features, the error locator polynomial generator is an inversionless Berlekamp-Massey algorithm (iBMA). The error location finder finds zeros in the error locator polynomial. The iBMA calculates an error locator polynomial and a scratch polynomial. The error values are calculated using an error value relationship that is based on the error locator polynomial and the scratch polynomial.
An error correcting Reed-Solomon decoder according to the present invention includes an error locator polynomial generator that generates an error locator polynomial and a scratch polynomial based on an inversionless Berlekamp-Massey algorithm (iBMA). An error location finder communicates with the error locator polynomial generator and generates error locations. An error values finder communicates with at least one of the error location finder and the error locator polynomial generator and generates error values using an error value relationship that is based on the error locator polynomial and the scratch polynomial.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:
The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements.
The calculation of the traditional error evaluator polynomial increases the amount of time and/or more hardware that is required to perform RS decoding. The present invention discloses a RS decoder that eliminates the need for the error evaluator polynomial. As a result, the error evaluator need not be calculated and the amount of time that is required to perform RS decoding is significantly reduced.
The RS decoder according to the present invention calculates error values based on the error-locator polynomial and the scratch polynomial that are generated by the inversionless Berlekamp-Massey (iBMA) algorithm. In addition to reduced decoding time, the hardware that is required to implement the RS decoder according to the present invention is significantly reduced.
Referring now to
In step 218, the RS decoder finds error locations. For example, Chien's search algorithm can be used. If the degree of ^(x) is small, the roots of ^(x) can be found directly without doing a search. In step 222, error values are found using an error value relationship according to the present invention that will be described further below.
At the end of iBMA algorithm in
or equivalently
where Λ0 is the coefficient of the 0-th degree term of Λ(x), m0 and t are integers defining the Reed-Solomon code, ΔB is a discrepancy value, α is a primitive element of GF(q), B(2t)(x) is the scratch polynomial at the end of iBMA, and Λ′(x) is the formal derivative of the error locator polynomial Λ(x).
Referring now to
An error values finder 248 locates errors using the error value relationship according to the present invention. The error values finder 248 is not based on the error evaluator polynomial and therefore does not require the error evaluator polynomial to be calculated. Control 250 coordinates and controls decoding and storage 252 (such as registers, latches, memory or other electronic storage) stores data values for use by the RS decoder 230.
The RS decoder 230 can be a register-based VLSI circuit, software and a processor, an application specific integrated circuit (ASIC) and/or combinations thereof. One suitable register-based implementation of the error value relationship disclosed above and the iBMA is disclosed in “Efficient High-Speed Reed-Solomon Decoder”, U.S. patent application Ser. No. 10/305,091, filed Nov. 26, 2002, which is hereby incorporated by reference. As can be appreciated, some of the components of the RS decoder 230 can share multipliers and/or other elements to reduce cost.
Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.
This application claims the benefit of U.S. Provisional Application No. 60/371,898, filed Apr. 11, 2002, which is hereby incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
4839896 | Glover et al. | Jun 1989 | A |
6092233 | Yang | Jul 2000 | A |
6119262 | Chang et al. | Sep 2000 | A |
6122766 | Fukuoka et al. | Sep 2000 | A |
6209115 | Truong et al. | Mar 2001 | B1 |
6256763 | Oh et al. | Jul 2001 | B1 |
6286123 | Kim | Sep 2001 | B1 |
6317858 | Cameron | Nov 2001 | B1 |
6347389 | Boyer | Feb 2002 | B1 |
6374384 | Ohta et al. | Apr 2002 | B1 |
6378104 | Okita | Apr 2002 | B1 |
Number | Date | Country |
---|---|---|
WO9909694 | Feb 1999 | WO |
Number | Date | Country | |
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60371898 | Apr 2002 | US |