The disclosed circuit and method relate to integrated circuits. More particularly, the disclosed system and method relate to electrostatic discharge (“ESD”) protection for integrated circuits.
With the continued miniaturization of integrated circuit (“IC”) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (“LDD”) structures, shallow trench isolation (“STI”) structures, and self-aligned silicide (“salicide”) processes, all of which are used in advanced sub-quarter-micron complementary metal oxide semiconductor (“CMOS”) technologies. All of these processes cause the related CMOS IC products to become more susceptible to damage due to ESD events. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits on the IC from ESD damage.
As semiconductor processing technology advances, the gate dielectric of MOS transistors becomes thinner and increasingly susceptible to damage caused by ESD current. This issue becomes more serious when the MOS transistor is used in a multi-power domain circuitry. where a diode module is typically connected to an I/O ground bus between two power domains. When the ESD occurs, the diode module may induce the ESD current to flow through a damaging path other than the I/O ground bus as a desired path, thereby damaging the thin-gate-dielectric MOS transistors.
According to the ESD Association's Charge Device Model (CDM) roadmap, with the advent of larger capacitance IC packages, the higher capacitance will lead to relatively higher magnitude discharge peak current levels, creating new challenges.
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivative thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
In various embodiments, an ESD protection circuit of a cross-power-domain interface is provided as a standard cell of a cell library. The protection cell may have the same height as the receiver (driven) domain circuit cells. The ESD protection cell may be readily incorporated into IC designs. The layout of the ESD protection cell saves area on the IC, and provides great flexibility. For increased protection, plural ESD protection cells may be connected in series and laid out in a horizontal chain, or arranged vertically in two or more rows.
The protection circuit 100 may be an ESD clamp circuit between the Vdd2 and Vss2 power rail, comprising a resistor and a pair of devices. In the embodiment of
The protection circuit design is to be incorporated into a standard cell library, to be selected by IC designers as a building block for IC designs.
In
The protection circuit 100 has a first power bus 150 connected to Vdd2. The circuit 100 has a first ground bus 170 connected to a ground supply voltage VSS.
As best seen in
Thus, the protection cell 100 can be included in IC designs and automatically placed by a place and route tool of an electronic design automation (EDA) system.
Referring now to
The substrate has a first device, which in this embodiment is a P-diode 100a. The P-diode is coupled between the first power bus 150 (Vdd2) and the input I of the driven device 60. The input I of the driven device 60 is coupled by way of a resistor R (
The substrate has a second device 100b corresponding to the first device 100a. That is, if the first device 100a is a P diode, the second device 100b is an N diode (Alternatively, if the first device is a GDPMOS, the second device is a GGNMOS). In
N diode 100b has a P well 190 (
The anode (P+ region) 105 of the P diode is connected to the cathode (N+ region) 115 of the N diode by way of contact vias 106, contact vias 116 and a connecting line pattern 160 in the M1 layer. The pattern 160 is in turn connected to the input of the driven device by way of another interconnect pattern (not shown) in the same metal layer or another metal layer. Thus, the P diode anode 105 and N diode cathode 115 are both connected to the input of the receiving (driven) device 60.
Optionally, the protection circuit 100 further comprises at least one dummy pattern 130 adjacent the first or second N+ region 101, 102 of the first device 100a and/or the first or second P+ region 111, 112 of the second device 100b. The dummy patterns are not connected to any other devices. For example, dummy conductors may be formed in the gate electrode layer to maintain a desired polysilicon density. Polysilicon density is controlled in advanced technologies to prevent dishing and erosion in subsequently formed layers. The dummy pattern 130 is arranged in a direction extending from the power bus to the ground bus. In the example, a respective dummy pattern 130 is arranged vertically on each side of each of the P diode 100a and N diode 100b. This is just one example. Other dummy configurations (or no dummy patterns) may be used as desired to maintain any target polysilicon density.
In the example of
In
The protection cells 100, 100L, 100R occupy a much smaller footprint than a diode clamp formed of multiple devices not contained within a single library cell. Further, the left protection cell 100L and right protection cell 100R occupy a substantially smaller horizontal width (and area) than protection cell 100. This enables the designer to adjust the number of CDM protection unit cells depending on the internal core circuitry available area. The designer can select the number of CDM protection unit cells to maximize protection, minimize area, or optimize the number to improve both the protection and area relative to other designs. Thus, given an available area on the substrate, several protection devices may be abutted together. The designer can abut one or more additional second protection cells 100L, 100R to the second protection cell 100L, 100R (as shown in
Left protection cell 100L (
As shown in
As shown in
When a second unit protection cell 100, 100L or 100R is included in the protection circuit, the second unit cell has a second power bus Vdd2 connected to the first power bus Vdd2 of the first unit protection cell. Also, the second unit cell 100, 100L or 100R has a second ground bus Vss connected to the first ground bus. The protection cell 100 is configured so that the first device (P diode 100a) is positioned near a PMOS of the driven device 60. The second device (N diode 100b) is positioned near an NMOS of the driven device 60. The PMOS of the driven device and the NMOS of the driven device are both connected to the input of the driven device. This configuration simplifies routing.
Thus, the layouts of the unit protection cells 100, 100L or 100R ensure that the power and ground buses of the unit protection cells are aligned for direct abutment. The second unit cell is connected similarly to the first unit cell 100, and has a P diode 100a coupled between the second power bus Vdd2 and the input I of the driven device. The second unit cell has an N diode coupled between the input I of the driven device and the ground bus Vss. The anode (P+ region) 105 of the P diode and cathode (N+ region) 115 of the N diode of the second unit protection cell are connected to patterns 160, which are in turn connected to the input I of the receiving (driven) circuit 60 by a conductive pattern (not shown) in the M1 layer or another interconnect layer.
In the embodiment of
The second device 200b is a GGNMOS having first and second P+ regions 211, 212 connected by a third P+ region 213, and a plurality of N+ regions 220, 220C between the first and second P+ regions 211, 212. The P+ regions 211, 212 are connected to the ground bus VSS by contact vias 214 and the ground bus pattern 270 in the M1 layer. And the cathode (inner N+ region 220C) are connected to ground by way of contact via 219 and the ground bus pattern 270. Outer N+ regions 220 are connected to the input of the driven device 60 by way of contact vias 216 and the pattern 260 in M1. A gate electrode 215 is coupled to ground by way of contact vias 217 and the ground bus pattern 270 in the M1 layer. The gate electrode 215 has portions between and above ones of the plurality of N+ regions 220, 220C.
The gate coupling technique is used to control the gates of the GDPMOS 200a and GGNMOS 200b to speed up the turn on (breakdown under reverse-biased) speed of these devices under negative-to-Vdd ESD stress for the GDPMOS 200a and positive-to-VS S ESD stress for GGNMOS 200b.
The at least one persistent machine readable storage medium stores data 2014 and instructions 2016 used by the processor. The medium stores at least one cell library 2000. The cell library contains a plurality of standard function cells 2002. Each standard cell includes transistor and interconnect structures to provides a respective logic function (e.g., AND, OR, XOR, XNOR, inverters), a storage function (flipflop or latch) or more complex circuit functions. The library also contains at least one ESD protection cell 2004. In some libraries, the ESD protection cell contains the clamping diode pair 100 of
Although not limited to such applications, the protection circuits shown and described herein provide protection suitable for CDM applications (e.g., a large die with a thin gate insulating layer). The protection circuit provides an area efficient layout which can readily be incorporated into logic designs.
In some embodiments, an integrated circuit has a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2 lower, equal to, or higher than the first supply voltage Vdd1. A protection circuit comprises: a first power bus connected to Vdd2. A first ground bus is connected to a ground supply voltage. The first ground bus is arranged so that a distance between the first power bus and the first ground bus matches a distance between a power bus of the driven device and a ground bus of the driven device. A first device is provided from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between the first power bus and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provide from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and the ground bus.
In some embodiments, a persistent, computer readable storage medium is encoded with a cell library for an electronic design automation (EDA) tool. The cell library has a plurality of cell designs for implementing respective logic functions. The library comprises at least one protection cell defining a protection circuit for an integrated circuit having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2 lower, equal to or higher than the first supply voltage Vdd1. The protection circuit includes: a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus coupled to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device, is provided from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus. A receiving cell is provided for laying out at least the input of the driven device. The protection cell has a cell height that is the same as a cell height of the receiving cell.
In some embodiments, a method of laying out an integrated circuit (IC), comprises: selecting a protection cell from a cell library, the protection cell defining a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus. A receiving cell is selected from the cell library for laying out the input of the driven device. The protection cell has a cell height that is the same as a cell height of the receiving cell. An electronic design automation (EDA) tool is used to lay out the IC so as to include the protection cell and the receiving cell.
Although the subject matter has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments, which may be made by those skilled in the art.
This application is a continuation of U.S. patent application Ser. No. 15/893,022, filed Feb. 9, 2018 which is a continuation of U.S. patent application Ser. No. 14/731,622, filed Jun. 5, 2015, which is a continuation of U.S. patent application Ser. No. 13/339,410, filed Dec. 29, 2011, each of which are expressly incorporated by reference herein in their entireties.
Number | Name | Date | Kind |
---|---|---|---|
5616943 | Nguyen | Apr 1997 | A |
5629544 | Voldman | May 1997 | A |
5679971 | Tamba | Oct 1997 | A |
6137143 | Dabral | Oct 2000 | A |
6351362 | Inoue et al. | Feb 2002 | B1 |
7253453 | Ker et al. | Aug 2007 | B2 |
7411767 | Huang et al. | Aug 2008 | B2 |
7417837 | Chen | Aug 2008 | B2 |
7593202 | Khazhinsky et al. | Sep 2009 | B2 |
9069924 | Chen | Jun 2015 | B2 |
11024625 | Chen | Jun 2021 | B2 |
20010023962 | Pasqualini | Sep 2001 | A1 |
20020030954 | Duvvury et al. | Mar 2002 | A1 |
20020084490 | Ker et al. | Jul 2002 | A1 |
20030023937 | McManus | Jan 2003 | A1 |
20030052367 | Lin | Mar 2003 | A1 |
20040041168 | Hembree | Mar 2004 | A1 |
20080218920 | Vanysacker et al. | Sep 2008 | A1 |
20090045457 | Bobde | Feb 2009 | A1 |
20090097174 | Ker et al. | Apr 2009 | A1 |
20090302347 | Matsunaga | Dec 2009 | A1 |
20100019274 | Uno et al. | Jan 2010 | A1 |
20100127782 | Karp | May 2010 | A1 |
20100147657 | San et al. | Jun 2010 | A1 |
20100321842 | Gebreselasie | Dec 2010 | A1 |
20110063763 | Alvarez et al. | Mar 2011 | A1 |
20110157251 | Lim et al. | Jun 2011 | A1 |
20110233678 | Tsai | Sep 2011 | A1 |
20120182652 | Jung | Jul 2012 | A1 |
20120211749 | Fukuoka et al. | Aug 2012 | A1 |
20130063843 | Chen et al. | Mar 2013 | A1 |
20130170080 | Chen | Jul 2013 | A1 |
20130342940 | Taghizadeh Kaschani | Dec 2013 | A1 |
20140092507 | Lefferts et al. | Apr 2014 | A1 |
20140167106 | Salcedo | Jun 2014 | A1 |
20150270260 | Chen | Sep 2015 | A1 |
Entry |
---|
Ker, M.D. et al., “Layout Design on Multi-Finger Mosfet for On-Chip ESD Protection Circuits in a 0.18-μM Salicided CMOS Process”, The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, 1:361-364. |
Ker, M.D. et al., “ESD Protection Circuits With Novel MOS-Bounded Diode Structures”, IEEE International Symposium an Circuits and Systems, 2002, 5:V533-V535. |
“Electrostatic Discharge (ESD) Technology Roadmap”—ESD Association, Revised Apr. 21, 2010, 6 pages, found at www.esda.org. |
Chen, S.H. et al., “Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology”, Microelectronics Reliabiltiy, 2006, 46:1042-1049. |
Linten, D., et al., “A 4.5 kV HBM, 300 V Cdm, 1.2 kV HMM ESD Protected DC-to-16.1 GHz Wideband LNA in 90 nm CMOS”, 31st EOS/EDS Symposium, 2009, pp. 1-6. |
Number | Date | Country | |
---|---|---|---|
20210210483 A1 | Jul 2021 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 15893022 | Feb 2018 | US |
Child | 17208829 | US | |
Parent | 14731622 | Jun 2015 | US |
Child | 15893022 | US | |
Parent | 13339410 | Dec 2011 | US |
Child | 14731622 | US |