Estimating of the jitter of a clock signal

Abstract

A method and a device for estimating the jitter of a first periodic signal with respect to a second periodic signal, comprising steps of: sampling the first signal by means of the second one; providing the result of the sampling to the input of a shift register triggered by the second signal; comparing at least the first two states and the last state of a current word formed from parallel outputs of the shift register with respect to a reference word; and counting the number of occurrences of the reference word within a given measurement period.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1, previously described, very schematically and partially shows an electronic circuit of the type to which embodiments of the present invention may be applied.

FIG. 2, previously described, is a timing diagram illustrating a clock jitter.

FIG. 3, previously described, is intended to expose the state of the art and the problem to solve.

FIG. 4 illustrates in timing diagrams an example of jitter of a periodic signal generated by an electronic circuit with respect to a reference signal.

FIG. 5 is an enlargement of the timing diagrams of FIG. 4 around a time when the two signals are in phase.

FIG. 6 shows the characteristic of cumulative probability of occurrence of a given state along time, for a clock signal generated by an electronic circuit.

FIG. 7 is a schematic block diagram illustrating an embodiment of a circuit for estimating the jitter of a periodic signal.

FIG. 8 schematically shows a detail of an embodiment of the circuit of FIG. 7.

FIG. 9 shows timing diagrams illustrating the operation of an embodiment of a detection circuit.

FIGS. 10A and 10B illustrate variations of a detection pattern of an embodiment of a device.

Claims

1. A method for estimating jitter of a first periodic signal with respect to a second periodic signal comprising steps of: sampling the first signal by means of the second one;providing a result of the sampling to an input of a shift register triggered by the second signal;comparing at least two first bits and a last bit of a current word formed from parallel outputs of the shift register with respect to a first reference word; andcounting a number of occurrences of the first reference word within a given measurement period.

2. The method of claim 1, wherein the number of occurrences is compared with a threshold and is periodically reset, the jitter being considered as acceptable as long as the threshold has not been reached.

3. The method of claim 1, wherein the first and last bits of the first reference word are identical, the second bit of the first reference word being in an inverse state.

4. The method of claim 1, wherein the first reference word comprises between one and three first bits in a first state, between one and three next bits in a second state inverse to the first state, and between one and three last bits in the first state.

5. The method of claim 1, wherein the current word provided by the shift register is compared with a second reference word inverse with respect to the first reference word.

6. The method of claim 1, wherein the measurement period is selected according to a period of the second periodic signal.

7. The method of claim 1, wherein the number of bits of the first reference word ranges between four and twelve.

8. The method of claim 1, wherein the number of bits of the first reference word ranges between five and seven.

9. The method of claim 1, wherein the current word is formed of all the outputs of the shift register.

10. The method of claim 1, wherein the current word is formed of a portion of the outputs of the shift register.

11. A device for estimating a jitter of a periodic signal with respect to a reference signal, comprising: a shift register having an input receiving the periodic signal, sampled by the reference signal;a first comparator configured to compare a word formed of parallel outputs of the shift register to a reference pattern;a first counter configured to count occurrences of a positive comparison provided by the first comparator; anda second comparator configured to compare a result of the first counter to a threshold.

12. The device of claim 11 wherein the comparator is configured to compare at least two first bits and a last bit of the word to the reference pattern.

13. The device of claim 11 wherein the first and last bits of the reference pattern are identical, the second bit of the reference pattern being an inverse of the first bit.

14. The device of claim 11 wherein the reference pattern comprises between one and three first bits in a first state, between one and three next bits in a second state inverse to the first state, and between one and three last bits in the first state.

15. The device of claim 11, further comprising: a third comparator configured to compare the word to an inverse of the reference pattern; anda second counter configured to count occurrences of a positive comparison by the third comparator, wherein the second comparator is further configured to compare a result of the second counter to the threshold.

16. The device of claim 11 wherein the first counter is configured to periodically reset.

17. The device of claim 11 wherein a number of bits of the reference pattern is between five and seven.

18. The device of claim 11 wherein the word is formed of a portion of the outputs of the shift register.

19. The device of claim 11 wherein an output of the second comparator comprises an error signal.

20. An integrated circuit, comprising: means for sampling a clock signal;means for detecting a match of an output of the means for sampling to a data set; andmeans for determining whether a jitter of the clock signal with respect to a reference clock signal is acceptable.

21. The integrated circuit of claim 20 wherein the means for sampling comprises: a flip-flip; anda shift register.

22. The integrated circuit of claim 20 wherein the means for detecting a match comprises a comparator configured to compare a plurality of bits of the output of the means for sampling to the data set.

23. An integrated circuit, comprising: a sampler configured to sample a clock signal;a pattern detector configured to receive samples from the sampler and to detect occurrences of a pattern in the received samples; andan error detector coupled to the pattern detector and configured to generate a signal indicative of a jitter of the clock signal with respect to a reference clock signal based on an output of the pattern detector.

24. The integrated circuit of claim 23, further comprising a clock generator coupled to the reference clock signal and configured to generate the clock signal.

25. The integrated circuit of claim 23 wherein the sampler comprises: a flip-flop coupled to the clock signal and the reference clock signal; anda shift registered coupled to an output of the flip-flop.

26. The integrated circuit of claim 23 wherein the sampler comprises: a plurality of flip-flops coupled together in series; anda shift register coupled to an output of the plurality of flip-flops.

27. The integrated circuit of claim 23 wherein the pattern detector is configured to compare a set of sampled bits to a set of reference bits.

28. The integrated circuit of claim 27 wherein the set of sampled bits comprises a first bit in a word of sampled bits, a second bit in the word and a last bit in the word.

29. The integrated circuit of claim 23 wherein the pattern detector is configured to determine whether a first and last portion of a word of sampled bits are in a first state and a intermediate portion of the word is in a second state, opposite of the first state.

30. The integrated circuit of claim 29 wherein the first portion has a one-bit length, the last portion has a one-bit length and the intermediate portion has a one-bit length, the intermediate portion being adjacent to the first portion.

31. The integrated circuit of claim 29 wherein the first portion has a two-bit length, the last portion has a two-bit length and the intermediate portion has a two-bit length, the intermediate portion being adjacent to the first portion.

32. The integrated circuit of claim 29 wherein the pattern detector is further configured to determine whether the first and last portion are in the second state and the intermediate portion is in the first state.

33. The integrated circuit of claim 23 wherein the signal generated by the error detector indicates the jitter is too high when a number of occurrences of the pattern exceeds a threshold number within a period of time.

34. The integrated circuit of claim 33 wherein the pattern detector is configured to detect occurrences of a second pattern in the received samples and the signal generated by the error detector indicates the jitter is too high when a number of occurrences of the second pattern exceeds the threshold number within the period of time.

35. A method of estimating a jitter of a clock signal with respect to a reference clock, comprising: sampling the clock signal using the reference clock;detecting occurrences of a first pattern in samples of the clock signal;generating a signal indicating the jitter of the clock signal with respect to the reference clock is too high when a number of detected occurrences of the pattern exceeds a first threshold value within a first period of time.

36. The method of claim 35 further comprising: detecting occurrences of a second pattern in the samples of the clock signal; andgenerating the signal indicating the jitter is too high when a number of detected occurrences of the second pattern exceeds a second threshold value within a second period of time.

37. The method of claim 36 wherein the second pattern is an inverse of the first pattern, the second threshold value equals the first threshold value and the second period of time equals the first period of time.

38. The method of claim 35 wherein detecting occurrences of a first pattern comprises determining whether a first and last portion of a word of sampled bits are in a first state and a intermediate portion of the word is in a second state, opposite of the first state.

39. The method of claim 38 wherein the first portion of the word has a one-bit length, the last portion of the word has a one-bit length, and the intermediate portion of the word is adjacent to the first portion of the word and has a one-bit length.

40. The method of claim 38 wherein the first portion of the word has a three-bit length, the last portion of the word has a three-bit length, and the intermediate portion of the word is adjacent to the first portion of the word and has a three-bit length.