Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn

Abstract

An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

The invention is illustrated in more detail in the drawings on the basis of an exemplary embodiment.

FIG. 1 illustrates a first measurement data flow representation with n error free data words y(1), y(2), . . . , y(n;

FIG. 2 shows a second measurement data flow representation with a faulty measurement data word y′(i);

FIG. 3 illustrates a schematic illustration of a first linear automaton circuit;

FIG. 4 illustrateds a schematic illustration of a second linear automaton circuit;

FIG. 5 illustrates a sequential scheme for determining signature differences ΔS1 and ΔS2 from a measurement data stream T_n; and

FIG. 6 illustrates a flowchart for illustrating the method according to the invention for detecting an error e(i) in a data word y(i).

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

FIG. 1 illustrates a first measurement data flow representation 1.

The first measurement data flow representation 1 comprises a pseudorandom measurement data stream T_n, which is illustrated in rectangular fashion in FIG. 1 and is subdivided into n successive data words y(1), y(2), . . . , y(n) each having an identical data word length of k bits.

An input having the bit width k is shown on the left of the first measurement data flow representation 1, at which input the measurement data words y(1), y(2), . . . , y(n) are output e.g., from a tested integrated circuit in each case in clocked fashion. Therefore, the measurement data words having the higher indices are arranged further on the left in FIG. 1. Such a tested integrated circuit is also referred to hereinafter as Device Under Test/DUT.

An output having the bit width k is illustrated on the right of the first measurement data flow representation 1, via which output the measurement data are forwarded to a shift register 11. The shift register 11 is a shift register with a multiple input linear feedback shift register architecture or with an MILFSR architecture. All n data words are intended to be compressed in a single data word having the length of k bits by means of the shift register 11. The specification for the mapping of n data words y(1), y(2), . . . , y(n) into a single signature is given in equation (1).

S(1→n)=S(y(1), y(2), . . . , y(n))  (1)

The initial state z(t₀) of the shift register 11 with the MILFSR architecture is given by the zero vector 0, z(t₀)=0.

FIG. 2 illustrates a second measurement data flow representation 2 with a faulty measurement data word y′(i).

The second measurement data flow representation 2 differs from the first measurement data flow representation 1 by virtue of the fact that its data stream T_n has an error e(i) in the i-th data word y′(i) of the data stream T_n.

If such an error e(i) is present in the data word y′(i) of the data stream T_n, the specification for the mapping of n data words y(1), y(2), . . . , y(n) by the signature of the shift register 11 is given by equation (2).

S(1→n,i,e)=S(y(1), y(2), . . . , e(i), . . . , y(n)) (2)

This signature is then generated from the data words y(1), y(2), . . . , e(i), . . . , y(n) by means of the shift register 11. The shift register 11 has the MILFSR architecture already mentioned with reference to FIG. 1.

Through skillful comparison of the signatures

S(y(1), y(2), . . . , e(i), . . . ,y(n)) in equation (1) and

S(y(1), y(2), . . . , e(i), . . . , y(n)) in equation (2), it is possible to calculate back to the position i of the faulty data word y′(i) and to the error e(i), that is to say to all of its faulty bits e(i).

If a known digital test response of a DUT contains precisely one error e(i) in the i-th data word of the data stream, then the data word y′(i) and all the faulty bits of its error e(i) can be obtained with the aid of the mapping S(1→n,i,e) calculated from an MILFSR architecture. This is done at an instant t>n at which the data words y(1), y(2), . . . , y(n) of the data stream T_n are no longer available or are no longer required.

In accordance with the present invention, only 2 signatures, that is to say 2 k-bit data words, need be evaluated for the test, for the diagnosis and for the error correction of an error in an arbitrary data word of the data stream T_n comprising n k-bit data words.

FIG. 3 illustrates a schematic illustration of a first linear automaton circuit L1.

The first linear automaton circuit L1 comprises four states z₁, z₂, z₃ and z₄, which are illustrated in rectangular fashion in FIG. 3 and are arranged respectively one after the other and are stored in storage elements, e.g., D-type flip-flops. Provided upstream of the first state z₁ and in each case between the states z₂, z₃ and z₄ are four exclusive-OR gates XOR₁, XOR₂, XOR₃ and XOR₄, the first inputs of which are respectively formed by four measurement data lines y₁, y₂, y₃ and y₄ and the outputs of which are connected to the respective subsequent states z₁, z₂, z₃ and z₄.

The second input of the second OR gate XOR₂ is connected to the output of the first state z₁. The second input of the third OR gate XOR₃ is formed by the output of the second state z₂. The second input of the fourth OR gate XOR₄ is formed by the output of the third state z₃.

Attached to the output of the fourth state z₄ is a first output line 30, which forks into a first feedback line 31 and into a second feedback line 32. The first feedback line 31 forms the third input of the second XOR gate XOR₂, and the second feedback line 32 forms the second input of the first XOR gate XOR₁.

The first linear automaton circuit L1 is accordingly designed as a shift register exhibiting feedback with a primitive polynomial and having four states z₁, z₂, z₃ and z₄.

The state equations of the first linear automaton circuit L1 are calculated from the states z(t+1) at the instant t+1 in a manner dependent on the states z(t) at the instant t. Equations (3)-(6) hold true for the first linear automaton circuit L1:

z ₁(t+1)=z₄(t)⊕y₁(t)  (3)

z ₂(t+1)=z₁(t)⊕z₄(t)⊕y₂(t)  (4)

z ₃(t+1)=z₂(t)⊕y₃(t)  (5)

z ₄(t+1)=z₃(t)⊕y₄(t)  (6)

The following results with A as a state matrix:

$\begin{array}{cc}z\left(t+1\right)=Az\left(t\right)\oplus y\left(t\right)\mathrm{where}\begin{array}{c}A=\left[\begin{array}{cccc}0& 0& 0& 1\\ 1& 0& 0& 1\\ 0& 1& 0& 0\\ 0& 0& 1& 0\end{array}\right],z\left(t+1\right)=\left[\begin{array}{c}{z}_1\left(t+1\right)\\ z_2\left(t+1\right)\\ z_3\left(t+1\right)\\ z_4\left(t+1\right)\end{array}\right],z\left(t\right)=\left[\begin{array}{c}{z}_1\left(t\right)\\ z_2\left(t\right)\\ z_3\left(t\right)\\ z_4\left(t\right)\end{array}\right],\\ y\left(t\right)=\left[\begin{array}{c}{y}_1\left(t\right)\\ y_2\left(t\right)\\ y_3\left(t\right)\\ y_4\left(t\right)\end{array}\right]\end{array}& \left(7\right)\end{array}$

The autonomous behavior of the first linear automaton circuit L1 is calculated from equation (7) where y(t)=0 as

z(t+1)=Az(t)  (8)

Equations (3)-(8) are also referred to as successor equations.

It follows from equations (3), (5) and (6), where y_i(t)=0 for iε{1,2,3,}, that:

z ₄(t)=z₁(t+1)  (9)

z ₂(t)=z₃(t+1)  (10)

z ₃(t)=z₄(t+1)  (11)

It follows from equation (9), inserted into equation (4), that:

z ₂(t+1)=z₁(t+1)⊕z₁(t)

and

z ₁(t+1)⊕z₂(t+1)=z₁(t+1)⊕z₁(t+1)⊕z₁(t)

This results in the following:

z ₁(t)=z₁(t+1)⊕z₂(t+1)  (12)

Equations (9)-(12) are referred to as predecessor equations of the linear automaton circuit L1 for the input 0 or else as autonomous predecessor equations of the linear automaton circuit L1.

In matrix notation, the following predecessor equations are obtained analogously to the successor equations in (8) from (9)-(12)

$\begin{array}{cc}\begin{array}{c}z\left(t\right)=A^{-1}z\left(t+1\right)\\ \mathrm{where}A^{-1}=\left[\begin{array}{cccc}1& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& 1\\ 1& 0& 0& 0\end{array}\right]\end{array}& \left(13\right)\end{array}$

A⁻¹ is the inverse matrix with respect to A. Multiplication of A and A⁻¹ produces the unit matrix E.

$A^{-1}A=E\mathrm{where}E=\left[\begin{array}{cccc}1& 0& 0& 0\\ 0& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& 1\end{array}\right]$

FIG. 4 illustrates a schematic illustration of a second linear automaton circuit L2.

With regard to the signal direction, the second linear automaton circuit L2 is illustrated in mirrorinverted fashion with respect to the first linear automaton circuit L1.

Like the first linear automaton circuit L1, the second linear automaton circuit L2 comprises four states z₁, z₂, z₃, z₄, four exclusive-OR gates XOR₁, XOR₂, XOR₃ and XOR₄, and also four measurement data lines y₁, y₂, y₃ and y₄ which respectively form the first inputs of the exclusive-OR gates XOR₁, XOR₂, XOR₃ and XOR₄.

The exclusive-OR gates XOR₁, XOR₂, XOR₃ and XOR₄ are situated upstream of the fourth state z₄ and respectively between the states z₁, z₂ and z₃. The outputs of the exclusive-OR gates XOR₁, XOR₂, XOR₃ and XOR₄ are connected to the respective subsequent states z₁, z₂, z₃ and z₄.

The output of the first state z₁ forms a second output line 40, which is divided into a third feedback line 41 and into a fourth feedback line 42. The third feedback line 41 leads into the first exclusive-OR gate XOR₁ and the fourth feedback line 42 leads into the fourth exclusive-OR gate XOR₁.

Like the first linear automaton circuit L1, the second linear automaton circuit L2 is also designed as a shift register exhibiting feedback with a primitive polynomial and having four states z₁, z₂, z₃ and z₄.

The state equation of the second linear automaton circuit L2 is given in equation (15).

$\begin{array}{cc}z\left(t+1\right)=Bz\left(t\right)\oplus y\left(t\right)& \left(15\right)\\ \mathrm{where}& \\ B=\left[\begin{array}{cccc}1& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& 1\\ 1& 0& 0& 0\end{array}\right]=A^{-1}& \left(16\right)\end{array}$

B is the inverse matrix of A.

For an assumed error e(i) in a k-bit data word y′(i) of the data stream T_n from FIG. 2, there is obtained from the mapping specification in accordance with equation (2)

S(1→n,i,e)=S(y(1),y(2), . . . , y(i)⊕e(i), . . . , y(n))  (17)

and by application of the superposition principle in the case of linear automata

S(1→n,i,e)=S(y(1), y(2), . . . , y(n))⊕

S(0,0, . . . , e(i), . . . , 0

or

S(1→n,i,e)=S(1→n)⊕S(0,0, . . . , e(i), . . . ,0)

the difference

ΔS1(i,e)=S(1→n,i,e)⊕S(1→n)  (18)

where

ΔS1(i,e)=S(0,0, . . . , e(i), . . . , 0)  (19)

for

y(t)=0, for t≠i and y(t)=e(i), for t=i

With equation (19) in equation (18) it follows that

ΔS1(i,e)=S((n−i)→n,i,e)⊕S((n−i)→n)  (20)

At the instant t=i−1, as yet no error e(i) has occurred in the data word y′(i); it is not until from the instant t=i that this error e(i) occurs in a k-bit data word.

For the formation of the signature from n data words y(1), y(2), . . . , y(n) with precisely one assumed error e(i) in a data word y′(i), we obtain from equations (20) and (7)

ΔS1(i,e)=A⁽ⁿ⁻¹⁾e(i);i ε{1, 2, . . . , n}  (21)

Equation (21) is the difference of two MILFSR signatures, namely of the signature of a 1-word faulty data stream T_n at the position i and of the signature of an error-free data stream T_n. The signature difference ΔS1 (i,e) is formed by a procedure in which the faulty data word y′(i) defines the initial state of the MILFSR architecture and is then accumulated (n−i) times in the MILFSR architecture with the inputting of all 0 vectors.

Upon transforming equation (21) with equation (16)

e(i)=B⁽ⁿ⁻ⁱ⁾ΔS1(i,e)  (22)

it becomes evident that the data word e(i) can be calculated as a new signature by a procedure in which the initial state of the second linear automaton circuit L2 is set at ΔS1(i,e) and is then accumulated (n−i) times.

According to the invention, inverted MILFSR architectures can thus be used for calculating 1-word errors e in data streams T_n without it being necessary to still have these data streams available at the instant of calculating e(i).

From the equation corresponding to equation (20)

ΔS2(i,e)=B⁽ⁿ⁻ⁱ⁾e(i)  (23)

for the second linear automaton circuit L2, we obtain with equation (16) analogously to equation (20) the following equation (24). For an assumed 1-word error e(i), the following is obtained from equation (21) for the first linear automaton circuit L1

e(i)=A⁽ⁿ⁻¹⁾ΔS2(i,e)  (24)

By equating equations (22) and (24), this results in

A ⁽ⁿ⁻ⁱ⁾ ΔS2(i,e)=B⁽ⁿ⁻ⁱ⁾ΔS1(i,e)  (25)

Thus, if the initial state of the first linear automaton circuit L1 is set at ΔS2(i,e) or, respectively, if the initial state of the second linear automaton circuit L2 is set at ΔS1(i,e), and if this value is accumulated (n−i) times, then the error e(i) results as a new signature or as a new state in the case of both linear automaton circuits L1 and L2.

In this case, the value for the position i of the faulty data word y′(i) must lie between 1 and n.

If the equality of the expressions A⁽ⁿ⁻ⁱ⁾ΔS2(i,e) and B⁽ⁿ⁻ⁱ⁾ΔS1(i,e) results for none of the values i, 1≦i≦n, in equation (25), then an error e(i) which corrupts only the position i of the data word is not present, but rather an error which has corrupted at least two different positions in the data stream.

If ΔS1≠0 results, then it is possible, by resetting the linear automaton circuits L1 and L2 to ΔS2 and ΔS1, respectively, and by comparing the signatures accumulated in each step, to detect the position i of the faulty data word y′(i) and the error e(i) after n−i steps on both signatures or states. The signatures of the two linear automaton circuits L1 and L2 are equal in this case to

z ¹(n−i)=z²(n−i)  (26),

where z¹ and z² are L-dimensional state vectors of the linear automaton circuits L1 and L2, and where z¹(n−i) and z²(n−i) are the states of the two linear automaton circuits L1 and L2 after n−i clock cycles.

Given a serial data input, the following holds true for the two linear automaton circuits L1 and L2

y _i(t)=0 for i≠1 (L1)  (27)

y _i(t)=0 for i≠k (L2)  (28)

In this case, k denotes the number of bits of a data word y(i) from the data stream T_n.

The comparison for identity of the signatures calculated back in this MILFSR architecture produces, for an assumed error e in the data word i after n-1 steps,

z ¹(n−i)=z²(L+1−n+i)  (29)

FIG. 5 illustrates a sequential scheme 5 for determining signature differences ΔS1 and ΔS2 from a measurement data stream T_n.

Situated at the top side of the sequential scheme 5 is a measurement data word line 51, on which is present a data stream T_n comprising n successive data words y(1), . . . , y(i−1), y′(i), y(i+1), . . . , y(n) each having an identical data word length of k bits. In this case, the data word y′(i) represents a faulty data word.

The measurement data word line 51 forks into two branches, the left-hand one of which has a first coder C1, the first linear automaton circuit L1, L exclusive-OR gates XOR_L1, which are combined in the form of an XOR gate having the word width L, and also a first output 52, at which the signature difference ΔS1 is output. The right-hand branch comprises a second coder C2, the second linear automaton circuit L2, L exclusive-OR gates XOR_L2, which are likewise combined in the form of an XOR gate having the word width L, and also a second output 53, at which the signature difference ΔS2 is output.

The respective L first inputs of the L exclusive-OR gates XOR_L1 are formed by the outputs of the first linear automaton circuit L1, and the first inputs of the L exclusive-OR gates XOR_L2 are formed by the outputs of the second linear automaton circuit L2.

Good signatures of the two linear automaton circuits L1 and L2 are provided at the second inputs of the L exclusive-OR gates XOR_L1 and XOR_L2 by means of digital circuits that are not shown in FIG. 5. Said good signatures can be determined for a known data stream T_n. This is known to the person skilled in the art.

The measurement data stream T_n is input via the first coder C1 into the first linear automaton circuit L1 and, in parallel with this, via the second coder C2 into the second linear automaton circuit L2.

The data stream T_n respectively present is transformed uniformly by means of the coders C1 and C2. As a result, it is possible also to compare data words y(1), . . . , y(n) of different data streams T_n with one another.

The data words u¹(1), . . . , u¹(n) and u²(1), . . . , u²(n) coded by the coders C1 and C2 are compacted to form signatures S1 and S2 by means of the linear automaton circuits L1 and L2, respectively.

The actual signatures S1 and S2 thus determined are then compared with the known good signatures in the exclusive-OR gates XOR_L1 and XOR_L2. The respective L exclusive-OR gates XOR_L1 and XOR_L2 provide the signature differences ΔS1 and ΔS2 at the outputs 52 and 53.

According to the invention, these signature differences ΔS1 and ΔS2 can be used to ascertain whether errors have occurred in the case of the data stream T_n respectively under consideration.

If the data stream T_n has precisely one faulty data word y′(i), it is possible to directly determine both the position i of the faulty data word and the error e(i) of the faulty data word in the data stream.

The function of the first coder C1 is described precisely below.

The coder C1, for i=1, . . . , n, codes the data word y(i) having the data word length of k bits into a coded data word u¹(i), u¹(i)=Cod1(y(i)) having the word width of K1 bits. In this case, Cod1 designates the coding function of the first coder C1.

If y′(i) is the component-by-component XOR sum of two k bit wide data words y(i) and e(i), namely

y′(i)=y(i)⊕e(i)

then the following is to hold true for the coding function Cod1

$\begin{array}{c}{u}^{1\prime }\left(i\right)=\mathrm{Cod}1\left(y^{\prime }\left(i\right)\right)=\mathrm{Cod}1\left(y\left(i\right)\oplus e\left(i\right)\right)\\ =\mathrm{Cod}1\left(y\left(i\right)\right)\oplus f_1\left(e\left(i\right)\right)=u^1\left(i\right)\oplus f_1\left(e\left(i\right)\right)\end{array}$

so that a function ƒ₁⁻¹ where

ƒ₁⁻¹(f₁(e))=e

holds true for all binary data words e having the word width k that are possible as errors.

If the coder C1 realizes a linear block code with k information positions and with (K1−k) check positions, then the following holds true

$\begin{array}{c}\mathrm{Cod}1\left(y^{\prime }\left(i\right)\right)=\mathrm{Cod}1\left(y\left(i\right)\oplus e\left(i\right)\right)\\ =\mathrm{Cod}1\left(y\left(i\right)\right)\oplus \mathrm{Cod}1\left(e\left(i\right)\right)\end{array}$

and it holds true that

f₁=Cod1.

Linear block codes are described e.g. in document [1].

If e.g., k=3 and K1=5 and it holds true that

$\begin{array}{c}C1\left(y\left(i\right)\right)=C1{\left(\left[y_1\left(i\right)\right),y_2\left(i\right),y_3\left(i\right)\right]}^T)\\ ={\left[y_1\left(i\right),y_2\left(i\right),y_3\left(i\right),1,1\right]}^T,\end{array}$

then it holds true for y′(i)=y(i)⊕e(i) that:

$\begin{array}{c}\mathrm{Cod}1\left(y^{\prime }\left(i\right)\right)=\mathrm{Cod}1\left(y\left(i\right)\oplus e\left(i\right)\right)\\ =\mathrm{Cod}1\left(y\left(i\right)\right)\oplus f\left(e\left(i\right)\right)\end{array}$

where

f ₁(e(i))=f₁([e₁(i), e₂(i), e₃(i)]^T) [e₁(i), e₂(i), e₃(i), 0, 0]

and

ƒ₁⁻¹([e₁(i), e_z(i), e₃(i), 0, 0]^T)=e₁(i), e₂(i), e₃(i).

The function of the first linear automaton circuit L1 is described in detail below.

In the description below, the state matrix of the linear automaton circuits L1 and L2 may assume an arbitrary size and is not fixed at n=4, as described above. A further difference in the description below is that the input values of the linear automaton circuits L1 and L2 are coded data words u¹(1), . . . , u¹(n) and u²(1), . . . , u²(n), respectively, which have been coded by the first coder Cl and by the second coder C2, respectively, from the data words y(1), . . . , y(n).

The first linear automaton circuit L1 is formed over the field GF(2) and has a K1-dimensional state vector z¹(t). K1≧k holds true in this case.

The first linear automaton circuit L1 is generally described by the equation

z ¹(t+1)=A·z¹(t)⊕u¹(t)  (I)

In this case, z¹(t) and z¹(t+1) are K1-dimensional binary state vectors at the discrete instant t and t+1. u¹(t) is the coded data word that is input at the instant t.

A is a uniquely reversible binary (K1×K1) matrix.

The addition and the multiplication of the binary values in equation (I) are effected modulo 2.

After the data stream T_n comprising the n data words y(1), . . . , y(n) has been input into the first coder C1 and after the coded data words u¹(i), . . . , u¹(n) have been input into the first linear automaton circuit L1, the first linear automaton circuit L1 undergoes transition from an initial state z¹(1) to the state z¹(n+1). The following holds true in this case:

$z^1\left(n+1\right)=A^nz^1\left(1\right)\oplus \sum _{j=1}^nA^{n-j}u^1\left(j\right)$

In this case,

z ¹(n+1)=S(L1, u¹(1), . . . , u¹(n))

where u¹(i)=Cod1(y(i)) is designated as the signature of the data sequence y(1), . . . , y(n) of the first linear automaton circuit L1.

The initial state z¹(1) shall hereinafter be equal to the K1-dimensional zero vector 0. For carrying out the method according to the invention it is not necessary for the initial state z¹(1) to be formed as the zero vector. This assumption is made here in order to simplify the subsequent calculations.

If there is an error e(i) in the i-th data word of the data stream, then at the i-th instant, instead of the correct data word y(i), the faulty data word

y′(i)=y(i)⊕e(i)

is input into the first coder C1. In this case, the error e(i) is a k-dimensional binary vector. Those components of this binary vector which assume the value one designate the positions of the faulty bits in the i-th data word.

If only the i-th data word is faulty and all the other data words are correct, then the following holds true where z¹(1)=0 when the data stream that is only faulty in the i-th data word is input into the first coder C1 where

$\begin{array}{cc}\begin{array}{c}{u}^{1\prime }\left(i\right)=\mathrm{Cod}1\left(y^{\prime }\left(i\right)\right)\\ =\mathrm{Cod}1\left(y\left(i\right)\oplus e\left(i\right)\right)\\ =\mathrm{Cod}1\left(u\left(i\right)\right)\oplus f_1\left(e\left(i\right)\right)\\ =u^1\left(i\right)\oplus f_1(e\left(i\right)\end{array}& \\ z^{1\prime }\left(n+1\right)=\sum _{j=1}^nA^{n-i}u^1\left(j\right)\oplus A^{n-1}·f_1\left(e\left(i\right)\right)& \left(\mathrm{II}\right)\\ =z^1\left(n+1\right)\oplus A^{n-i}f_1\left(e\left(i\right)\right)& \left(\mathrm{III}\right)\\ \mathrm{and}\mathrm{hence}& \\ \begin{array}{c}{A}^{n-i}·f_1\left(e\left(i\right)\right)=z^{1\prime }\left(n+1\right)\oplus z^1\left(n+1\right)\\ =S\left(L1,u^1\left(1\right),\dots ,u^{1\prime }\left(i\right),\dots ,u^1\left(n\right)\right)\oplus \\ S\left(L1,u^1\left(1\right),\dots ,u^1\left(i\right),\dots ,u1\left(n\right)\right)\\ =\Delta S1\end{array}& \left(\mathrm{IV}\right)\end{array}$

For the case where f(e(i))=Cod1(e(i)), the following is obtained

A ⁿ⁻ⁱ Cod1(e(i))=ΔS1  (V)

For the case where Cod1(y(i))=y(i), i=1, . . . , n holds true, the following results

A ⁿ⁻ⁱ ·e(i)=ΔS1  (VI)

The function of the second coder C2 is described precisely below.

For i=1, . . . , n, the second coder C2 codes the data word y(i) having the data word length of k bits into the coded data word u²(i), u²(i)=Cod2(y(i)). The coded data word u²(i) has a word width of K2 bits. In this case, Cod2 designates the coding function of the second coder C2.

If y′(i) is the component-by-component XOR sum of two k bit wide words y(i) and e(i).

y′(i)=y(i)⊕e(i),

then the following is intended to hold true for the coding function Cod2

$\begin{array}{c}{u}^{2\prime }\left(i\right)=\mathrm{Cod}2\left(y^{\prime }\left(i\right)\right)\\ =\mathrm{Cod}2\left(y\left(i\right)\oplus e\left(i\right)\right)\\ =\mathrm{Cod}2\left(y\left(i\right)\right)\oplus f_2\left(e\left(i\right)\right)\\ =u^2\left(i\right)\oplus f_2\left(e\left(i\right)\right)\end{array}$

so that there is a function ƒ₂⁻¹ where ƒ₂⁻¹(f₂(e))=e for all binary data words e having the word width k which may be taken into consideration as errors.

The function of the second linear automaton circuit L2 is described in detail below.

The second linear automaton circuit L2 is formed over the field GF(2) and has a K2-dimensional state vector z²(t). K2≧k holds true in this case.

The second linear automaton circuit L2 is described by the equation

z ²(t+1)=B·z²(t)u²(t)  (VII)

where z²(t) and z²(t+11) are K2-dimensional binary state vectors at the discrete instants t and t+1. u²(t) is the coded data word that is input at the instant t. B where B≠A is a uniquely reversible binary (K2×K2) matrix. The addition and multiplication in (VII) are effected modulo 2.

After the data stream T_n comprising the n data words y(1), . . . , y(n) has been input into the second coder C2 and after the coded data words u²(1), . . . , u²(n) have been input into the second linear automaton circuit L2, the second linear automaton circuit L2 undergoes transition from its initial state z²(1) to the state z²(n+1)

$\begin{array}{cc}{z}^2\left(n+1\right)=B^nz^2\left(1\right)\oplus \sum _{j=1}^nB^{n-j}u^2\left(j\right)& \left(\mathrm{VIII}\right)\end{array}$

In this case,

z ²(n+1)=S(L2, u²(1), . . . , u²(n))

where u²(i)=Cod2(y(i)) is designated as the signature of the data stream y(1), . . . , y(n) in the second linear automaton circuit L2.

The K1-dimensional zero vector 0 subsequently forms the initial state z²(1).

If there is then an error e(i) in the i-th data word of the data stream, then at the i-th instant, instead of the correct data word y(i), the faulty data word y′(i)=y(i)⊕e(i) is input into the second coder Cod2.

If only the i-th data word is faulty and all the other data words are correct, then there holds true, where z²(1)=0, where

$\begin{array}{cc}\begin{array}{c}{u}^{2\prime }\left(i\right)=\mathrm{Cod}2\left(y\left(i\right)\oplus e\left(i\right)\right)\\ =u^2\left(i\right)\oplus f_2\left(e\left(i\right)\right)\end{array}& \left(\mathrm{analogous}\mathrm{to}\left(\mathrm{III}\right)\right)\\ \begin{array}{c}{z}^{2\prime }\left(n+1\right)=\sum _{i=1}^nB^{n-i}u^2\left(j\right)+B^{n-i}f_2\left(e\left(i\right)\right)\\ =z^2\left(n+1\right)\oplus B^{n-i}f_2\left(e\left(i\right)\right)\end{array}& \left(\mathrm{IX}\right)\\ \mathrm{and}\mathrm{where}& \\ \begin{array}{c}{z}^{2\prime }\left(n+1\right)\oplus z^2\left(n+1\right)\\ =S(L2,u^2\left(1\right),\dots ,u^{2\prime }\left(i\right),\dots ,\\ u^2\left(n\right))\oplus S(L2,u^2\left(1\right),\dots ,\\ u^2\left(i\right),\dots ,u^2\left(n\right))\\ =\Delta S2\end{array}& \end{array}$

the following equation:

ΔS2=Bⁿ⁻¹ƒ₂(e(i))  (X)

For the case where f₂(e(i))=Cod2(e(i)) the following holds true instead of (X)

ΔS2=Bⁿ⁻¹Cod2(e(i))  (XI)

For the case where Cod2(e(i))=e(i) holds true, the following results

ΔS2=Bⁿ⁻ⁱ·e(i)  (XII)

If the results of the processing of the data stream in the linear automaton circuits L1 and L2 are combined, then the following are obtained from equations (IV) and (X)

e(i)=ƒ₁⁻¹(Aⁱ⁻ⁿΔS1)  (XIV)

e(i)=ƒ₂⁻¹(Bⁱ⁻ⁿΔS2)  (XV)

which result in the following equation:

ƒ₁⁻¹(aⁱ⁻ⁿΔS2)=ƒ₂⁻¹(Bⁱ⁻ⁿΔS2)  (XVI)

By means of the equation (X-VI) it is possible to calculate i, iε{1, . . . , n}, that is to say the position i of the faulty data word y′(i).

The value for i from equation (XVI) can be calculated e.g., iteratively by calculating for i=1, 2, . . . the value of the left-hand and right-hand sides of equation (XVI) until both sides match.

If the value for i has been determined in this way, then it is possible, by means of equation (XIV), also to directly determine the value for e(i), that is to say the position of the faulty data word in the data stream.

FIG. 6 illustrates a flowchart 6 for illustrating the method according to the invention for detecting an error e(i) in a data word y′(i).

The first flowchart 6 provides a total of seven method processs 61-67, the method processes 62 and 65 being formed as decision fields and the remaining method processes being formed as execution fields.

The first method process 61 involves generating the signature differences ΔS1 and ΔS2 and also a data stream T_n, as is illustrated e.g., in FIGS. 1 and 2. Said data stream T_n may be formed from a sequence of measurement data of a DUT.

As described thoroughly with reference to FIG. 5, said data stream T_n is fed via the first coder C1 to the first linear automaton circuit L1 and, at the same time as this, via the second coder C1 to the second linear automaton circuit L2. From the signatures generated by the linear automaton circuits L1 and L2 and from the good signatures provided, the exclusive-OR gates XOR_L1 and XOR_L2 determine the signature differences ΔS1 and ΔS2 from the difference between the good and poor signatures in accordance with equation (1) and equation (2) and provide the signature differences ΔS1 and ΔS2 at the outputs 52 and 53.

In the second method process 62, the signature difference ΔS1 present at the first output 52 is compared with zero. If the signature difference ΔS1 is equal to zero, this means that no error could be detected in the data stream T_n. In this case, the method continues with the checking of the next data stream T_n. If the signature difference ΔS1 is not equal to zero, this means that one or arbitrarily many faulty data words y(1), . . . , y(n) are faulty. In this case, the method continues with the method step 63.

In the method process 63, the states z(t=n+1) of the linear automaton circuits L1 and L2 are in each case reset to the values of the respective other signature differences ΔS1 and ΔS2.

The method process 64 involves calculating back for y(t)=0, to be precise the linear automaton circuits L1 and L2 are accumulated in (n−i) steps for y(t)=0 and the states according to equation (26) are checked for identity. This process of calculating back is known to the person skilled in the art and need not be explained any further here.

The method process 65 involves checking whether a solution exists. If this is not the case, then more than one data word y(1), . . . , y(n) of the data stream T_n is faulty.

If a solution does exist, then the data word y′(i) and the error e(i) are calculated in the method step 66.

In this case, firstly the data word y′(i) is determined from the number of traversed cycles of the linear automaton circuit L1 and L2.

The error e(i) is then calculated from equation (30):

e(i)=z(t) for t=i, 1≦i≦N  (30)

z(t=i) is the state of the two linear automaton circuits L1 and L2 at the instant t=i.

In a further exemplary embodiment, it is also possible to check two serial, that is to say successive, data streams T_n.

In this case, the left-hand branch of the measurement data word line 51 is traversed twice in succession and the right-hand branch of the measurement data word line 51 is not traversed at all, in the second pass the first coder C1 being replaced by the second coder C2 if the first coder C1 differs from the second coder C2 and the first linear automaton circuit L1 with the state matrix A being replaced by the second linear automaton circuit L2 with the state matrix B, B≠A, which may be effected technically e.g., in a simple manner using multiplexers.

If the method is realized on a computer system, then that program part which realizes the first linear automaton circuit L1 is quite simply to be replaced in the second pass by that program part which realizes the second linear automaton circuit L2. Likewise, if the coders C1 and C2 differ from one another, the function Cod1 of the first coder C1 in the first pass is to be replaced by the function Cod2 of the second coder C2 in the second pass.

In this case, S1 is the signature calculated in the first pass and S2 is the signature calculated in the second pass. The method essentially matches the method described in the previous exemplary embodiment.

The implementation of the method is readily possible for a person skilled in the art on the basis of the information given in this patent specification.

The following document has been cited in the context of this patent specification:

[1] Rohling H., Einführug in die Informations- und Codierungstheorie, Teubner Verlag, 1995 [Introduction to information and coding theory]

In order to unambiguously identify and diagnose an error e(i) at the position i of the data stream T_n, it is, surprisingly, not necessary for the feedback polynomial to be primitive or irreducible. It actually suffices here for the matrix B to be the inverse of the matrix A.

Thus, the value of the position of the error i, which must naturally occur in the data stream from 1 to n, is determined from the equation

f ₁ ⁻¹ (Aⁱ⁻ⁿ ΔS₁)=f₂⁻¹ (B^i-n ΔS₂)

and where then =A⁻¹ as

f ₁ ⁻¹ (A^i-n ΔS₁)=f₂⁻¹ (Aⁿ⁻ⁱ ΔS₂)

Moreover, for e(i), the faulty bit positions in the faulty i-th data word, the following results

e(i)=f₁⁻¹ (Aⁱ⁻ⁿ ΔS₁).

If the matrix A has an inverse matrix A⁻¹, then A^ke(i)≠0 holds true for e(i)≠0 for any k. Thus, and because a linear superposition principle holds true for linear shift registers, an individual error e(i) which has corrupted different bits at the position i can never be masked. By virtue of the fact that the signature is furthermore also provided in two different multi-input signature registers with mutually inverse matrices A and B=A⁻¹, it is even possible to determine the position i and the value e(i) exactly.

A masking of errors in a signature which is identical to the good signature can only occur with a vanishingly small probability if a plurality of errors occur at a plurality of bit positions which cancel out randomly in their signature. In the case of a single faulty position this is not possible, as explained.

The probability, when a plurality of errors are present, of the equation

f ₁ ⁻¹ (ΔS₁)=f₂⁻¹ (Aⁿ⁻ⁱ ΔS₂)

having a solution for i where 1≦i≦n is negligibly small and if it happens that no solution can be found for i, this means that there is no individual error e(i) present which has only faulty bits at the position i in the data stream. The property whereby the feedback polynomial is intended to be primitive is an advantageous configuration for which the error masking probability that is inherently already practically negligibly small is especially small for errors which relate to a plurality of positions in the data stream T_n.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims

1-29. (canceled)

30. An evaluation circuit comprising: a first linear automation circuit;a second linear automation circuit connected in parallel with the first linear automation circuit, each having a set of states, which have a common input line for receiving a data stream, wherein the first linear automaton circuit and the second linear automation circuit are configured such that a first signature and a second signature can be calculated;a first logic combination gate and a second logic combination gate that compare the first signature and the second signature, respectively, with a predeterminable good signature and an output comparison-value.

31. The evaluation circuit as claimed in claim 30, comprising wherein the first logic combination gate and the second combination logic gate are exclusive-OR gates having first inputs, respectively, connected to the outputs of the associated first and second linear automaton circuit and to whose second inputs good signatures can be applied.

32. The evaluation circuit as claimed in claim 30, comprising wherein arranged upstream of the first linear automaton circuit is a first coder, that codes the data word having the data word length of k bits into a coded data word u1(i), u1(i)=Cod1 having the word width of K1 bits, for i=1, . . . , n, and where Cod1 represents the coding function of the first coder.

33. The evaluation circuit as claimed in claim 32, comprising wherein the following holds true for the coding function of the first coder (C1): Cod1(y′(i))=u1(i)⊕fi(e(i)),

34. The evaluation circuit as claimed in one of claim 30, comprising wherein arranged upstream of the second linear automaton circuit is a second coder, which codes the data word y(i) having the data word length of k bits into a coded data word u2(i), u2(i)=Cod2(y(i)) having the word width of K2 bits, for i=1, . . . , n, and where Cod2 represents the coding function of the second coder (C2).

35. An evaluation circuit for detecting and/or locating faulty data words in a data stream Tn comprising: a first linear automaton circuit and a second linear automaton circuit connected in parallel, each having a set of states, wherein the first linear automaton circuit and the second linear automaton circuit have a common input line for receiving a data stream Tn comprising n successive data words y(1), . . . , y(n) each having a width of k bits, wherein the first linear automaton circuit can be described by the following equation z(t+1)=Az(t)⊕y(t)

36. The evaluation circuit as claimed in claim 35, comprising wherein the logic combination gates are present as exclusive-OR gates whose first inputs are respectively connected to the outputs of the associated linear automaton circuit (L1, L2) and to whose second inputs good signatures can be applied.

37. The evaluation circuit as claimed in claim 35, comprising wherein arranged upstream of the first linear automaton circuit is a first coder, that codes the data word y(i) having the data word length of k bits into a coded data word u1(i), u1(i)=Cod1 having the word width of K1 bits, for i=1, . . . , n, and where Cod1 represents the coding function of the first coder.

38. The evaluation circuit as claimed in claim 37, comprising wherein the following holds true for the coding function of the first coder: Cod1(y′(i))=u1(i)⊕f1(e(i)),

39. The evaluation circuit as claimed in one of claim 35, comprising wherein arranged upstream of the second linear automaton circuit is a second coder, which codes the data word y(i) having the data word length of k bits into a coded data word u2(i), u2(i)=Cod2(y(i)) having the word width of K2 bits, for i=1, . . . , n, and where Cod2 represents the coding function of the second coder.

40. The evaluation circuit as claimed in claim 39, comprising wherein the following holds true for the coding function of the second coder:

41. The evaluation circuit as claimed in one of claim 37, comprising wherein that the word width K1 of the data words u1(i) coded by the first coder is equal to the word width K2 of the data words u2(i) coded by the second coder.

42. The evaluation circuit as claimed in one of claim 37, comprising wherein the first coder matches the second coder with regard to its construction and its function.

43. The evaluation circuit as claimed in one of claim 37, comprising wherein the word width K1 of the data words u1(i) coded by the first coder and the word width K2 of the data words u2(i) coded by the second coder are in each case equal to the word width k of the data words y(1), . . . , y(n) of the data stream Tn.

44. The evaluation circuit as claimed in one of claim 37, comprising wherein the coding functions Cod1 and Cod2 of the first coder and of the second coder are designed as follows: Cod1(y1(i), y2(i), . . . , yk(i))=P1(y1(i), y2(i), . . . , yk(i), 0, . . . , 0)Cod2(y1(i), y2(i), . . . , yk(i))=P2(y1(i), y2(i), 0, . . . , 0)

45. The evaluation circuit as claimed in claim 37, comprising wherein the coding functions Cod1 and Cod2 of the first coder and of the second coder are designed as follows: Cod1(y1(i), y2(i), . . . , yk(i))=P1(yi(i), y2(i), . . . , yk(i), b11 . . . , bK1 k1)Cod2(y1(i), y2(i), . . . , yk(i))=P2(y1(i), y2(i), . . . , yk(i), b12 . . . , bK2 k2)

46. The evaluation circuit as claimed in one of claim 37, comprising wherein the coding function Cod1 of the first coder is designed such that it realizes a linear block code, f1=Cod1.

47. The evaluation circuit as claimed in one of claim 37, comprising wherein the coding function Cod2 of the second coder is designed such that it realizes a linear block code, f2=Cod2.

48. The evaluation circuit as claimed in one of claim 35, comprising wherein the state matrix A of the first linear automaton circuit and the state matrix B of the second linear automaton circuit are related to one another as follows: B=An

49. The evaluation circuit as claimed in claim 35, comprising wherein the state matrix B of the second linear automaton circuit is equal to the inverted state matrix A−1 of the first linear automaton circuit.

50. The evaluation circuit as claimed in claim 35, comprising wherein the first linear automaton circuit is designed as a linear feedback shift register and the second linear automaton circuit is designed as an inverse linear feedback shift register, both linear automaton circuits having a parallel input.

51. The evaluation circuit as claimed in claim 35, comprising wherein the first linear automaton circuit is designed as a linear feedback, K1-dimensional multi-input shift register and/or the second linear automaton circuit is designed as a linear feedback, K2-dimensional multi-input shift register.

52. The evaluation circuit as claimed in claim 51, comprising wherein the multi-input shift register/registers has/have a primitive feedback polynomial of maximum length.

53. A method for detecting and/or locating faulty data words in a data stream Tn, the method having the following method steps of: inputting data words y(1), . . . , y(i−1), y′(i), y(i+1), . . . , y(n) of a data stream Tn into a first coder,coding the data words y(1), . . . , y(n) into coded data words u1(1), . . . , u1(n) having the word width K1 where K1≧k by means of the coding function Cod1 of the first coder,inputting the coded data words u1(1), . . . , u1(i−1), u1′(i) or u1(i), u1(i), . . . , u1(n) into the inputs of a first linear automaton circuit, which is described by the automaton equation; z1(t+1)=A·z1(t)+u1(t)

54. The method as claimed in claim 53, comprising wherein the method is carried out by means of an evaluation circuit as claimed in one of claim 35.

55. The evaluation circuit as claimed in one of claim 35, comprising wherein the evaluation circuit is monolithically integrated on an integrated circuit.

56. A loadboard for receiving at least one needle card for testing integrated circuits and/or having at least one test socket for testing integrated circuits and/or for connecting a handler to a tester of integrated circuits, the loadboard having an evaluation circuit as claimed in one of claim 35.

57. A needle card for testing integrated circuits, in which an evaluation circuit as claimed in one of claim 35 is integrated.

58. A tester for testing integrated circuits having the following features: the tester is provided with a plurality of instruments for generating signals or data streams and with a plurality of measuring sensors, in particular for currents and voltages, the tester has a loadboard which is provided for receiving at least one needle card for testing integrated circuits and/or for connecting a handler to a tester of integrated circuits and/or which is equipped with at least one test socket for testing integrated circuits, and the tester has an evaluation circuit as claimed in one of claim 35.

59. A computer program for executing a method for detecting and/or locating faulty data words in a data stream Tn, which is designed for executing a portion of the method of claim 53.

60. The computer program as claimed in claim 59, which is contained on a storage medium, in particular in a computer memory or in a random access memory.

61. The computer program as claimed in claim 59, which is transmitted on an electrical carrier signal.

62. A data carrier having a computer program as claimed in claim 59.

63. A method in which a computer program as claimed in claim 57 is downloaded from an electronic data network onto a computer connected to the data network.